CN216119932U - Multilayer ceramic capacitor - Google Patents

Abstract

The utility model provides a laminated ceramic capacitor. The internal electrode layer includes: a1 st internal electrode layer having an opposing portion and a1 st lead-out portion extending from the opposing portion to a1 st end surface side; and a2 nd internal electrode layer alternately arranged with the 1 st internal electrode layer and having an opposing portion and a2 nd lead-out portion extending from the opposing portion to the 2 nd end surface side. A1 st dummy electrode layer extending to a1 st end surface side is arranged closer to the 1 st main surface side than a1 st inner electrode layer positioned closest to the 1 st main surface side, a2 nd dummy electrode layer extending to a2 nd end surface side is arranged closer to the 2 nd main surface side than a2 nd inner electrode layer positioned closest to the 2 nd main surface side, a1 st lead-out portion positioned closest to the 1 st main surface side has a1 st bent portion bent toward a center side in a laminating direction, a1 st lead-out portion positioned closest to the 2 nd main surface side has a2 nd bent portion bent toward the center side in the laminating direction, and a bending depth of the 1 st bent portion in the laminating direction is deeper than a bending depth of the 2 nd bent portion.

Description

Multilayer ceramic capacitor

Technical Field

The present invention relates to a laminated ceramic capacitor.

Background

A multilayer ceramic capacitor is provided with: a laminate body including an inner layer portion in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated with each other, and an outer layer portion disposed on both sides of the inner layer portion in a lamination direction; and external electrodes provided on both end surfaces of the laminate.

Conventionally, in such a multilayer ceramic capacitor, there is a problem that peeling occurs at the interface between the inner layer portion and the outer layer portion. Therefore, for example, a technique has been developed in which the sintering temperature of the outer layer portion is lowered to bring the sintering temperatures of the outer layer portion and the inner layer portion close to each other, thereby preventing delamination (see patent document 1).

Prior art documents

Patent document

Patent document 1: japanese laid-open patent publication No. 9-97733

However, although the shrinkage behavior of the outer layer portion and the inner layer portion during firing can be made close to each other in the conventional art, the shrinkage ratio of the outer layer portion after firing becomes larger than that of the inner layer portion, and as a result, there is a problem that peeling occurs.

SUMMERY OF THE UTILITY MODEL

Problem to be solved by utility model

The present invention aims to provide a multilayer ceramic capacitor in which the possibility of peeling between an outer layer portion and an inner layer portion and between inner layer portions is reduced.

Means for solving the problems

In order to solve the above problem, the present invention provides a multilayer ceramic capacitor including: a laminate body having an inner layer portion in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated with each other, and an outer layer portion disposed on both sides in a lamination direction in the inner layer portion; and external electrodes provided on a1 st end surface of one side and a2 nd end surface of the other side in a longitudinal direction intersecting the stacking direction of the stacked body, wherein the internal electrode layers include: a1 st internal electrode layer having facing portions facing each other between the internal electrode layers adjacent to each other and a1 st lead-out portion extending from the facing portions to a1 st end surface side; and a2 nd internal electrode layer which is arranged alternately with the 1 st internal electrode layer and has the facing portion and a2 nd lead-out portion extending from the facing portion to a2 nd end surface side, wherein when one of the lamination directions of the laminated body is a1 st main surface and the other is a2 nd main surface, a1 st dummy electrode layer extending to the 1 st end surface side similarly to the 1 st internal electrode layer is arranged on the 1 st main surface side of the 1 st internal electrode layer on the most 1 st main surface side, a2 nd dummy electrode layer extending to the 2 nd end surface side similarly to the 2 nd internal electrode layer is arranged on the 2 nd main surface side of the 2 nd internal electrode layer on the most 2 nd main surface side, and the 1 st lead-out portion on the most 1 st main surface side has a1 st bent portion bent to a center side in the lamination direction, the 1 st lead-out portion on the 2 nd principal surface side has a2 nd bent portion bent toward the center side in the stacking direction, and the 1 st bent portion has a bending depth in the stacking direction larger than a bending depth of the 2 nd bent portion.

Effect of the utility model

According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the possibility of peeling between the outer layer portion and the inner layer portion and between the inner layer portions is reduced.

Drawings

Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1.

Fig. 2 is a partial cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II.

Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.

Fig. 4 is a flowchart illustrating a method of manufacturing the laminated ceramic capacitor 1.

In fig. 5, (a) is a partial sectional view illustrating a state of the laminate 2A immediately after the parent block dividing step S4, (B) is a partial sectional view illustrating a state of the laminate 2B immediately after the preliminary pressing step S5, and (C) is a partial sectional view illustrating a state of the laminate 2C immediately after the final pressing step S6.

Description of the reference numerals

A1: a1 st main surface;

a2: a2 nd main surface;

c1: 1 st end face;

c2: a2 nd end surface;

k1: a bending section;

k2: a bending section;

1: a laminated ceramic capacitor;

2: a laminate;

3: an external electrode;

3A: 1 st external electrode;

3B: a2 nd external electrode;

4: a dielectric layer;

5: an internal electrode layer;

5A: 1 st internal electrode layer;

5 Aa: a1 st contraposition part;

5Ab, 5Ab1, 5Ab 2: the 1 st lead-out part;

5B: 2 nd internal electrode layer;

5 Ba: a2 nd contraposition part;

6: an inner layer portion;

7: an outer layer part;

8: a dummy electrode layer;

31: sintering the electrode layer;

32: and a resin electrode layer.

Detailed Description

The multilayer ceramic capacitor 1 according to the embodiment of the present invention will be described below. Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1. Fig. 2 is a partial cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II. Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.

(multilayer ceramic capacitor 1)

The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape, and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The laminate 2 includes an internal layer portion 6 in which a plurality of dielectric layers 4 and a plurality of internal electrode layers 5 are laminated.

In the following description, as a term indicating the orientation of the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1 is referred to as the longitudinal direction L. The direction in which the dielectric layers 4 and the internal electrode layers 5 are stacked is referred to as a stacking direction T. A direction intersecting both the longitudinal direction L and the stacking direction T is defined as a width direction W. In the embodiment, the width direction W is orthogonal to both the longitudinal direction L and the stacking direction T.

Among the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the lamination direction T are defined as a1 st main surface a1 and a2 nd main surface a2, a pair of outer surfaces facing each other in the width direction W are defined as a1 st side surface B1 and a2 nd side surface B2, and a pair of outer surfaces facing each other in the longitudinal direction L are defined as a1 st end surface C1 and a2 nd end surface C2. Fig. 2 shows the 1 st end face C1 side of a cross section passing through the center in the width direction W and extending in the stacking direction T and the longitudinal direction L. In addition, the laminated ceramic capacitor 1 of the embodiment is often used in a state where the 2 nd main surface a2 side is the mounting direction and the 1 st main surface a1 is directed upward.

In addition, when the description is not particularly made for the 1 st main surface a1 and the 2 nd main surface a2, they are collectively described as the main surface a, when the description is not particularly made for the 1 st side surface B1 and the 2 nd side surface B2, they are collectively described as the side surface B, and when the description is not particularly made for the 1 st end surface C1 and the 2 nd end surface C2, they are collectively described as the end surfaces.

(laminate 2)

The laminate 2 includes an inner layer 6 and outer layers 7 arranged on both main surfaces a of the inner layer 6. The laminate 2 of the embodiment is not limited thereto, but in the embodiment, the lamination direction T and the width direction W are 0.27mm to 0.33mm, and the longitudinal direction L is 0.57mm to 0.63 mm.

(inner layer part 6)

The inner layer portion 6 is formed by stacking a plurality of dielectric layers 4 and a plurality of internal electrode layers 5. The inner layer portion 6 includes 30 layers or more and 50 layers or less of the internal electrode layer 5 and the dielectric layer 4, respectively.

(outer layer portion 7)

The outer layer portion 7 is disposed on the 1 st main surface a1 side and the 2 nd main surface a2 side of the inner layer portion 6, and is made of the same ceramic material as the dielectric layer 4 of the inner layer portion 6.

(dielectric layer 4)

The thickness of the dielectric layer 4 in the stacking direction T is not limited to this, but is 0.7 μm to 0.9 μm in the embodiment. The dielectric layer 4 is made of, for example, barium titanate (BaTiO)₃) Etc. ceramic material.

(internal electrode layer 5)

The thickness of the internal electrode layers 5 in the stacking direction T in the embodiment is not limited to this, but is 0.5 μm to 0.6 μm in the embodiment. The internal electrode layers 5 include a plurality of 1 st internal electrode layers 5A and a plurality of 2 nd internal electrode layers 5B. The 1 st internal electrode layers 5A and the 2 nd internal electrode layers 5B are alternately arranged. In addition, when it is not necessary to particularly distinguish between the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B, the description will be given collectively as the internal electrode layers 5.

The 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are alternately arranged with the dielectric layer 4 interposed therebetween. The 1 st and 2 nd internal electrode layers 5A and 5B are opposite in the longitudinal direction L, but have the same shape and the same size.

The 1 st internal electrode layer 5A includes a1 st facing portion 5Aa facing the 2 nd internal electrode layer 5B and a1 st lead-out portion 5Ab led out from the 1 st facing portion 5Aa to the 1 st end face C1 side. The end of the 1 st lead-out portion 5Ab is exposed at the 1 st end face C1 and is electrically connected to the 1 st external electrode 3A described later.

The 2 nd internal electrode layer 5B includes a2 nd opposing portion 5Ba opposing the 1 st internal electrode layer 5A and a2 nd lead-out portion (not shown) led out from the 2 nd opposing portion 5Ba to the 2 nd end face C2. The end of the 2 nd lead-out portion is electrically connected to a2 nd external electrode 3B described later.

The electric charges are accumulated in the 1 st opposed portion 5Aa of the 1 st internal electrode layer 5A and the 2 nd opposed portion 5Ba of the 2 nd internal electrode layer 5B, and the characteristics of the capacitor are exhibited.

In the following, when it is not necessary to particularly distinguish between the 1 st facing portion 5Aa and the 2 nd facing portion 5Ba, the description will be given collectively as the facing portion 5 a. When the 1 st lead-out portion 5Ab and the 2 nd lead-out portion do not need to be particularly described separately, they are collectively described as the lead-out portion 5 b.

As shown in fig. 3, the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are not exposed at the side surface B in the width direction W of the laminate 2, and this portion serves as a side spacer.

As shown in fig. 2, the inner electrode layer 5 closest to the 1 st main surface a1 is the 1 st inner electrode layer 5A, and the 1 st dummy electrode layer 8A extending to the 1 st end surface C1 side in the same manner as the 1 st inner electrode layer 5A is arranged on the 1 st main surface a1 side of the 1 st inner electrode layer 5A. In the embodiment, the 1 st internal electrode layer 5A and the 1 st dummy electrode layer 8A on the most 1 st main surface a1 side are substantially parallel.

The inner electrode layer 5 closest to the 2 nd main surface a2 is the 2 nd inner electrode layer 5B, and the 2 nd dummy electrode layer 8B extending to the 2 nd end surface C2 side similarly to the 2 nd inner electrode layer 5B is arranged on the 2 nd main surface a2 side of the 2 nd inner electrode layer 5B. In the embodiment, the 2 nd inner electrode layer 5B and the 2 nd dummy electrode layer 8B located on the 2 nd main surface a2 side are substantially parallel.

In the following, when the 1 st dummy electrode layer 8A and the 2 nd dummy electrode layer 8B are not particularly described separately, they will be collectively described as the dummy electrode layers 8. The dummy electrode layer 8 is connected to the same external electrode as the adjacent internal electrode layer 5, is an electrode that does not substantially contribute to formation of capacitance, and protects the internal electrode layer 5 and the like.

Further, the interval between each of the 1 st dummy electrode layer 8A and the 2 nd dummy electrode layer 8B and the adjacent internal electrode layer 5 is narrower than the interval between the mutually adjacent internal electrode layers 5, that is, the interval between the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B.

That is, the interval T1A in the stacking direction T between the 1 st dummy electrode layer 8A and the 1 st internal electrode layer 5A closest to the 1 st main surface a1 is narrower than the interval T2 between the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B.

Further, the interval T1B in the stacking direction T between the 2 nd dummy electrode layer 8B and the 2 nd internal electrode layer 5B closest to the 2 nd main surface a2 is also narrower than the interval T2 between the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B.

The interval between adjacent internal electrode layers 5 is the interval between the 1 st internal electrode layers 5A or the interval between the 2 nd internal electrode layers 5B in the portion of the lead portion 5B. Even in this case, the 1 st dummy electrode layer 8A and the 2 nd dummy electrode layer 8B are narrower in interval with the adjacent internal electrode layers 5 than in interval with the mutually adjacent internal electrode layers 5.

(bending of the drawn part)

The 1 st lead-out portion 5Ab1 located closest to the 1 st main surface side has a bent portion K1 bent toward the center side in the stacking direction T, and the 1 st lead-out portion 5Ab2 located closest to the 2 nd main surface side has a bent portion K2 bent toward the center side in the stacking direction T. The bending depth T1 of the bent portion K1 in the stacking direction T is deeper than the bending depth T2 of the bent portion K2. That is, the degree of curvature of the 1 st lead-out portion 5Ab1 is greater than the degree of curvature of the 1 st lead-out portion 5Ab2, and is bent sharply or largely.

Further, the bent portion K1 of the 1 st lead-out portion 5Ab1 is bent from the 1 st end surface C1 side toward the center portion in the stacking direction T, and then the direction is switched to be bent toward the 1 st main surface a1 side. On the other hand, the bent portion K2 of the 1 st lead-out portion 5Ab2 is bent from the 1 st end surface C1 toward the 2 nd main surface a2 side without being directed toward the center portion in the stacking direction T.

The multilayer ceramic capacitor 1 can be confirmed by polishing the surfaces in the longitudinal direction L and the stacking direction T to substantially the center in the width direction W, and observing the exposed cross sections in the longitudinal direction L and the stacking direction T with a microscope or the like.

(external electrode 3)

The external electrode 3 includes: a1 st external electrode 3A provided on the 1 st end face C1 of the laminate 2; and a2 nd external electrode 3B provided on the 2 nd end face C2 of the laminate 2. In addition, when it is not necessary to particularly distinguish between the 1 st external electrode 3A and the 2 nd external electrode 3B, the description will be given collectively as the external electrodes 3.

The external electrode 3 includes: the sintered electrode layer 31; a resin electrode layer 32 disposed outside the sintered electrode layer 31; and a plating layer 33 disposed outside the sintered electrode layer 31 and the resin electrode layer 32.

The sintered electrode layer 31 covers the end face C, and further covers a part of the main face a side and the side face B side. The resin electrode layer 32 covers only the end face C side of the sintered electrode layer 31, and does not extend to the main face a side and the side face B side. The plating layer 33 covers the end face C side of the sintered electrode layer 31 and the resin electrode layer 32, and extends to the main face a side and the side face B side.

(sintered electrode layer 31)

The sintered electrode layer 31 is formed by, for example, applying and firing a conductive paste containing a conductive metal and glass. The sintered electrode layer 31 preferably contains at least one metal selected from the group consisting of Cu, Ni, Ag, Pd, Ag — Pd alloy, Au, and the like, for example.

(resin electrode layer 32)

The resin electrode layer 32 has any structure including a thermosetting resin and a metal component. As a specific example of the thermosetting resin, for example, various known thermosetting resins such as epoxy resin, phenol resin, polyurethane resin, silicone resin, polyimide resin, and the like can be used. As the metal component, for example, Ag or metal powder in which Ag is coated on the surface of base metal powder can be used.

Since resin electrode layer 32 contains a thermosetting resin, it is more flexible than sintered electrode layer 31 made of a baked product of a plating film or a conductive paste, for example. Therefore, even when physical impact or impact due to thermal cycle is applied to the multilayer ceramic capacitor 1, the resin electrode layer 32 functions as a buffer layer, prevents cracks from occurring in the multilayer ceramic capacitor 1, easily absorbs piezoelectric vibration, and has an effect of suppressing "ringing".

The plating layer 33 is preferably a layer containing at least one metal selected from the group consisting of Cu, Ni, Ag, Pd, Ag — Pd alloy, Au, Sn, and the like, for example. In an embodiment, the plating 33 is a two-layer configuration of the Ni plating 33A, Sn plating 33B.

(method of manufacturing multilayer ceramic capacitor 1)

Fig. 4 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment. The method for manufacturing the laminated ceramic capacitor 1 includes a ceramic green sheet preparation step S1, an electrode layer printing step S2, a laminating step S3, a mother block dividing step S4, a preliminary pressing step S5, a main pressing step S6, and an external electrode forming step S7. The method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment is an example, and is not limited to this.

Fig. 5 is a partial cross-sectional view illustrating the state of the laminate 2 in each step of stacking the ceramic capacitors 1, where (a) is the laminate 2A immediately after the parent block dividing step S4, (B) is the laminate 2B immediately after the preliminary pressing step S5, and (C) is the laminate 2C immediately after the main pressing step S6.

(ceramic Green sheet preparation step S1)

First, a ceramic green sheet 10 in which a ceramic slurry containing a ceramic powder, a binder, and a solvent is held on a support film is prepared. As the ceramic green sheet 10, an internal electrode layer ceramic green sheet 10A, a dummy electrode layer ceramic green sheet 10B, and an external layer portion ceramic green sheet 10C were prepared. The ceramic slurry of the dummy electrode layer ceramic green sheet 10B is thinner than that of the internal electrode layer ceramic green sheet 10A. The ceramic slurry of the ceramic green sheet 10C for the outer layer portion is thicker than the ceramic green sheet 10A for the internal electrode layer.

(electrode layer printing step S2)

Next, the 1 st green sheet 11A on which an internal electrode layer pattern was printed on the internal electrode layer ceramic green sheet 10A was produced. Further, a2 nd green sheet 11B was produced in which a dummy electrode layer pattern was printed on the ceramic green sheet 10B for a dummy electrode layer.

(laminating step S3)

A plurality of the 1 st green sheets 11A are stacked so that the internal electrode layer patterns are shifted by half pitch in the longitudinal direction L between the 1 st green sheets 11A adjacent to each other in the stacking direction T.

The 2 nd green sheets 11B are stacked on both sides in the stacking direction T of the plurality of 1 st green sheets 11A stacked.

At this time, the 2 nd green sheet 11B was disposed so that the internal electrode layer pattern and the dummy electrode layer pattern of the 1 st green sheet 11A located on the stacked surfaces were at the same position. That is, the dummy electrode layer pattern and the adjacent internal electrode layer pattern are not shifted by half pitch, but are at the same position.

Further, ceramic green sheets 10C for the outer layer portion to be the outer layer portion 7 are stacked on both sides in the stacking direction T of the 1 st green sheet 11A and the 2 nd green sheet 11B stacked, respectively, to form a mother block.

(Master block dividing step S4)

Next, the mother block is divided to manufacture a plurality of laminated bodies 2. Fig. 5 (a) is a partial cross-sectional view of the laminate 2A immediately after the parent block dividing step S4.

(Pre-pressing step S5)

Fig. 5 (B) is a partial cross-sectional view of the laminate 2B immediately after the preliminary pressing step S5.

In the preliminary pressing step S5, the portion of the laminated body 2 extending from the 1 st lead-out portion 5Ab is preliminarily pressed from both the principal surfaces a.

In this preliminary pressing, the 1 st main surface a1 side is pressed more strongly than the 2 nd main surface a2 side, so that the 1 st main surface side of the 1 st lead-out portion 5Ab portion is recessed more greatly than the 2 nd main surface side in the laminate 2B. Thus, the bending portion K1 of the 1 st lead-out portion 5Ab1 on the 1 st main surface side is bent larger than the bending portion K2 of the 1 st lead-out portion 5Ab2 on the 2 nd main surface side.

The 1 st lead portion 5Ab1 is bent from the 1 st end surface C1 side toward the center portion in the stacking direction T at the bending portion K1, and then is turned to be bent toward the 1 st main surface a1 side. On the other hand, the 1 st lead portion 5Ab2 is bent at the bent portion K2 from the 1 st end surface C1 toward the 2 nd main surface a2 side without being directed toward the center portion in the stacking direction T.

(official pressing step S6)

Fig. 5 (C) is a partial cross-sectional view of the laminate 2C immediately after the main pressing step S6. In the main pressing step, the laminated body 2B in which the 1 st lead-out portion 5Ab is recessed is entirely pressed by, for example, isostatic pressing from the outer surface. Then, the ceramic slurry of the ceramic green sheet 10C for the outer layer portion flows while the curved shape of the 1 st lead-out portion 5Ab is maintained substantially as it is, and a laminate 2C in which the recess of the outer surface is eliminated can be produced as shown in fig. 5 (C).

As described above, in the embodiment, the 1 st bent portion K1 and the 2 nd bent portion K2 are formed in the preliminary pressing step S5 and the main pressing step S6, but the present invention is not limited to this. For example, the 1 st bent portion K1 and the 2 nd bent portion K2 may be formed by partially increasing the thickness of the ceramic green sheet 10C for the outer layer portion to be the outer layer portion 7.

(external electrode Forming Process S7)

Next, the external electrodes 3 are formed at both end portions of the laminate 2. The external electrode 3 includes the sintered electrode layer 31, the resin electrode layer 32, and the plating layer 33 as described above. First, for example, a conductive paste containing a conductive metal and glass is applied and fired to form the sintered electrode layer 31. Next, the resin electrode layer 32 containing a thermosetting resin and a metal component is applied to form the resin electrode layer 32. Further, an Ni plating layer 33A and an Sn plating layer 33B are formed.

In the embodiment, since the dummy electrode layer 8 is provided, it is possible to suppress the internal electrode layer 5 closest to the dummy electrode layer 8 and closest to the main surface a from being damaged at the time of baking. In the above-described embodiment, only the firing of the sintered electrode layer 31 is described, but the firing is not limited to this, and the multilayer body 2 may be fired before the external electrodes 3 are formed, and even in this case, the internal electrode layer 5 closest to the dummy electrode layer 8 and closest to the main surface a can be prevented from being damaged at the time of firing.

Through the above steps, the multilayer ceramic capacitor 1 of the embodiment can be manufactured.

(Effect of the multilayer ceramic capacitor 1 of the embodiment)

In the case of a general multilayer ceramic capacitor having a lead-out portion without a bent portion, which is different from the embodiment, separation may occur between an inner layer portion and an outer layer portion.

However, in the multilayer ceramic capacitor 1 of the embodiment, the 1 st bent portion K1 is provided in the 1 st lead-out portion 5Ab1 on the 1 st main surface a1 side of the 1 st inner electrode layer 5A, and the 2 nd bent portion K2 is provided in the 1 st lead-out portion 5Ab2 on the 2 nd main surface a2 side.

Therefore, the contact area between the internal electrode layer 5 and the adjacent dielectric layer 4 or external layer portion 7 increases, and the adhesion between these layers improves. Further, the anchoring effect between the inner layer portion 6 and the outer layer portion 7 by the 1 st bend portion K1 and the 2 nd bend portion K2 reduces the possibility of separation between the inner layer portion 6 and the outer layer portion 7.

In general, when the laminated ceramic capacitor is used with the 1 st main surface facing upward, a gravity is applied to a portion between the inner layer and the outer layer on the 2 nd main surface side, which is higher than a portion between the inner layer and the outer layer on the 2 nd main surface side. Therefore, the inner layer portion and the outer layer portion on the 2 nd principal surface side are less likely to be peeled off than between the inner layer portion and the outer layer portion on the 1 st principal surface side.

In the embodiment, the 1 st bend K1 provided on the side closest to the 1 st main surface a1 is bent further than the 2 nd bend K2 provided on the side closest to the 2 nd main surface a 2.

Further, the 1 st bent portion K1 provided on the most 1 st main surface a1 side is bent from the 1 st end surface C1 side toward the central portion in the stacking direction T, and then changes direction to be bent toward the 1 st main surface a1 side. On the other hand, the 2 nd bent portion K2 provided on the most 2 nd main surface a2 side, which is the opposite side, is bent from the 1 st end surface C1 toward the 2 nd main surface a2 side without toward the central portion in the stacking direction T.

That is, the anchoring effect between the inner layer portion 6 and the outer layer portion 7 on the 1 st main surface a1 side where peeling easily occurs is stronger than that between the inner layer portion 6 and the outer layer portion 7 on the 2 nd main surface side where peeling does not easily occur, and therefore, interlayer peeling can be efficiently prevented while bending of the 2 nd bent portion K2 is minimized.

While the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made.

Claims (7)

1. A laminated ceramic capacitor is provided with:

a laminate having: an inner layer portion in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked; and an outer layer section disposed on both sides of the inner layer section in the stacking direction; and

external electrodes provided on a1 st end surface and a2 nd end surface of the other end surface in a longitudinal direction intersecting the stacking direction of the stacked body,

it is characterized in that the preparation method is characterized in that,

the internal electrode layer includes:

a1 st internal electrode layer having facing portions facing each other between the internal electrode layers adjacent to each other and a1 st lead-out portion extending from the facing portions to a1 st end surface side; and

a2 nd internal electrode layer arranged alternately with the 1 st internal electrode layer and having the facing portion and a2 nd lead-out portion extending from the facing portion to a2 nd end face side,

when one of the lamination directions of the laminated body is set as a1 st main surface and the other is set as a2 nd main surface,

a1 st dummy electrode layer extending to the 1 st end surface side in the same manner as the 1 st internal electrode layer is arranged on the 1 st main surface side of the 1 st internal electrode layer which is located closest to the 1 st main surface side,

a2 nd dummy electrode layer extending to the 2 nd end face side in the same manner as the 2 nd inner electrode layer is arranged on the 2 nd main face side of the 2 nd inner electrode layer positioned on the 2 nd main face side,

the 1 st lead-out portion located closest to the 1 st main surface side has a1 st bent portion bent toward a center side in the stacking direction, the 1 st lead-out portion located closest to the 2 nd main surface side has a2 nd bent portion bent toward the center side in the stacking direction, and a bending depth in the stacking direction of the 1 st bent portion is deeper than a bending depth of the 2 nd bent portion.

2. The laminated ceramic capacitor according to claim 1,

the 1 st bend portion is bent from the 1 st end face side toward the center portion in the stacking direction, and then is turned to bend toward the 1 st main face side,

the 2 nd bent portion is bent from the 1 st end surface toward the 2 nd main surface side without being directed toward the center portion in the stacking direction.

3. The laminated ceramic capacitor according to claim 1 or 2,

the external electrode includes resin electrode layers on the 1 st end face side and the 2 nd end face side, and the resin electrode layers do not extend to the 1 st main face side and the 2 nd main face side.

4. The laminated ceramic capacitor according to claim 1 or 2,

the 1 st dummy electrode layer and the 2 nd dummy electrode layer have a narrower interval between adjacent internal electrode layers than between adjacent internal electrode layers.

5. The laminated ceramic capacitor according to claim 1 or 2,

the dielectric layer has a thickness of 0.7 to 0.9 μm.

6. The laminated ceramic capacitor according to claim 1 or 2,

the thickness of the internal electrode layer is 0.5 to 0.6 μm.

7. The laminated ceramic capacitor according to claim 1 or 2,

the stacking direction and the width direction are 0.27mm to 0.33mm,

the length direction is 0.57mm to 0.63 mm.

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