CN217061783U - Multilayer ceramic capacitor - Google Patents
Multilayer ceramic capacitor Download PDFInfo
- Publication number
- CN217061783U CN217061783U CN202220118035.5U CN202220118035U CN217061783U CN 217061783 U CN217061783 U CN 217061783U CN 202220118035 U CN202220118035 U CN 202220118035U CN 217061783 U CN217061783 U CN 217061783U
- Authority
- CN
- China
- Prior art keywords
- layer
- ceramic capacitor
- laminate
- electrode
- internal electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Ceramic Capacitors (AREA)
Abstract
Provided is a multilayer capacitor having high resistance to substrate warpage. A multilayer ceramic capacitor is provided with: a laminate body having an inner layer section as an effective region in which a plurality of dielectric layers and internal electrode layers are alternately laminated, and outer layer sections disposed on both sides of the inner layer section in the lamination direction; and external electrodes provided on the 1 st end face on one side and the 2 nd end face on the other side in the longitudinal direction of the multilayer body, respectively, the multilayer ceramic capacitor including: a laminate body in which a plurality of dielectric layers made of a ceramic material and a plurality of internal electrode layers are laminated, the laminate body having two main surfaces facing each other in a lamination direction, two side surfaces facing each other in a width direction intersecting the lamination direction, and two end surfaces facing each other in a longitudinal direction intersecting the lamination direction and the width direction; and two external electrodes respectively disposed on both end faces of the laminate, wherein the height of the inner layer portion is equal to or greater than 1/3 of the height of the laminate, and at least one of the two outer layer portions has a recess.
Description
Technical Field
The utility model relates to a range upon range of ceramic capacitor.
Background
In recent years, there has been a growing demand for a multilayer ceramic capacitor that is widely used in electronic devices to have a smaller size and a larger capacitance.
Such a ceramic capacitor cannot accommodate warpage or bending of a substrate on which the ceramic capacitor is mounted, and as a result, there is a case where a defect such as a crack occurs in the capacitor.
In order to solve such a problem, patent document 1 proposes a technique of joining a heat-resistant member forming a space portion to a bottom surface of a capacitor.
Prior art documents
Patent document
Patent document 1: japanese patent laid-open publication No. 2007-273867
However, in view of the above-described demand for miniaturization, it is desirable that the laminated ceramic capacitor itself have a resistance to warpage of the substrate, and it is useful if such a laminated ceramic capacitor can be provided.
SUMMERY OF THE UTILITY MODEL
Problems to be solved by the utility model
An object of the present invention is to provide a laminated ceramic capacitor having a resistance to warpage of a substrate.
Means for solving the problems
In order to solve the above problem, the present invention provides a multilayer ceramic capacitor or the like, comprising:
a laminate body having an inner layer portion as an effective region in which a plurality of dielectric layers and internal electrode layers are alternately laminated, and an outer layer portion disposed on both sides of the inner layer portion in a lamination direction; and
external electrodes provided on the 1 st end surface on one side and the 2 nd end surface on the other side in the longitudinal direction of the laminate body intersecting the lamination direction,
the multilayer ceramic capacitor is provided with:
a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers, each of which is made of a ceramic material, are laminated, the laminate having two main surfaces facing in the lamination direction, two side surfaces facing in a width direction intersecting the lamination direction, and two end surfaces facing in a length direction intersecting the lamination direction and the width direction; and two external electrodes respectively disposed on the two end faces of the laminate,
the height of the inner layer portion is equal to or greater than 1/3, and at least one of the two outer layer portions has a recess.
Effect of utility model
According to the present invention, a laminated ceramic capacitor having a high resistance to warpage of a substrate can be provided.
Drawings
Fig. 1 is a perspective view showing a multilayer ceramic capacitor according to the present embodiment.
Fig. 2 is a sectional view (LT section) taken along line II-II of the laminated ceramic capacitor shown in fig. 1.
FIG. 3 is a cross-sectional view taken along line IIIa-IIIa (WT cross-section a) of the laminated ceramic capacitor shown in FIG. 1.
FIG. 4 is a cross-sectional view taken along line IIIb-IIIb (WT cross-section b) of the laminated ceramic capacitor shown in FIG. 1.
Description of the reference numerals
1: a laminated ceramic capacitor;
10: a laminate;
20: a dielectric layer;
30: an internal electrode layer;
31: 1 st internal electrode layer;
311: a 1 st counter electrode section;
312: 1 st leading-out electrode part;
32: 2 nd internal electrode layer;
321: a 2 nd counter electrode section;
322: a 2 nd leading electrode section;
40: an external electrode;
41: 1 st external electrode;
415: 1 st base electrode layer;
416: 1 st inner plating layer;
417: 1, plating a coating layer on the surface;
42: a 2 nd external electrode;
425: the 2 nd base electrode layer;
426: 2, inner plating layer;
427: 2, plating a coating layer;
100: an inner layer portion (effective region);
101: the 1 st outer layer part;
102: the 2 nd outer layer part;
l30: an electrode opposing portion;
LG 1: 1 st end spacer;
LG 2: a 2 nd end spacer;
w30: an electrode opposing portion;
WG 1: a 1 st lateral spacer;
WG 2: a 2 nd lateral spacing part;
l: a length direction;
t: a stacking direction;
w: a width direction;
LS 1: 1 st end face;
LS 2: a 2 nd end face;
TS 1: a 1 st main surface;
TS 2: a 2 nd main surface;
WS 1: the 1 st side;
WS 2: a 2 nd side;
r: a recess.
Detailed Description
Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals.
< multilayer ceramic capacitor >
Fig. 1 is a perspective view showing a laminated ceramic capacitor according to the present embodiment, fig. 2 is a sectional view taken along line II-II of the laminated ceramic capacitor shown in fig. 1, fig. 3 is a sectional view taken along line IIIa-IIIa of the laminated ceramic capacitor shown in fig. 1, and fig. 4 is a sectional view taken along line IIIb-IIIb of the laminated ceramic capacitor shown in fig. 1.
The multilayer ceramic capacitor 1 shown in fig. 1 to 4 includes a multilayer body 10 and external electrodes 40. The external electrodes 40 include a 1 st external electrode 41 and a 2 nd external electrode 42.
An XYZ rectangular coordinate system is shown in fig. 1 to 4. The X direction is the longitudinal direction L of the multilayer ceramic capacitor 1 (and the multilayer body 10 of the multilayer ceramic capacitor 1 and the effective region thereof), the Y direction is the width direction W of the multilayer ceramic capacitor 1 (and the multilayer body 10 of the multilayer ceramic capacitor 1 and the effective region thereof), and the Z direction is the stacking direction T of the multilayer ceramic capacitor 1 (and the multilayer body 10 of the multilayer ceramic capacitor 1 and the effective region thereof).
Accordingly, the cross section shown in fig. 2 may be referred to as an LT cross section, and the cross sections shown in fig. 3 and 4 may be referred to as WT cross sections (the cross sections shown in fig. 3 and 4 may be referred to as a WT cross section a and a WT cross section b, respectively, by distinguishing the two sections).
The longitudinal direction L, the width direction W, and the stacking direction T are not necessarily orthogonal to each other, and may be orthogonal to each other.
The laminate 10 has a substantially rectangular parallelepiped shape, and has a 1 st main surface TS1 and a 2 nd main surface TS2 facing each other in the lamination direction T, a 1 st side surface WS1 and a 2 nd side surface WS2 facing each other in the width direction W, and a 1 st end surface LS1 and a 2 nd end surface LS2 facing each other in the longitudinal direction L.
The thickness of the dielectric layer may be, for example, 15 μm or more and 22 μm or less.
The thickness of the dielectric layer may be, for example, 0.5 μm or more and 1.0 μm or less.
The size of the laminate is not particularly limited, and is preferably 01005 (L0.4 mm, W0.2 mm, and T0.2 mm) to 0201 (L0.6 mm, W0.3 mm, and T0.3 mm) in the EIA standard, for example.
Here, the "height of the laminated body 10" may be the longest distance among the distances between the two main surfaces in the laminating direction T.
The substantially rectangular parallelepiped shape of the laminate 10 has the recessed portions R on at least one of the two main surfaces (the 1 st main surface TS1 and the 2 nd main surface TS 2).
In the present specification, the term "recess" of the recess R means a distance (i.e., a distance by which a perpendicular line drawn from the straight line descends) measured from a straight line connecting two points, i.e., a point at which the 1 st end surface LS1 intersects the 1 st main surface and a point at which the 2 nd end surface LS2 intersects the 1 st main surface in the LT cross section of the laminate 10 [ or a straight line connecting two points, i.e., a point at which the 1 st end surface LS1 intersects the 2 nd main surface and a point at which the 2 nd end surface LS2 intersects the 2 nd main surface ] to a portion where the main surfaces are most recessed in the LT cross section (i.e., the deepest point of the recess), and in this case, the distance is 0.5% or more of the height of the laminate 10. The number of the recesses R is preferably 1.
The shape of the recess R is not limited, and may be, for example, a shape formed in a straight line like a V-shape in the LT cross section, a shape curved like a U-shape, or a combination thereof.
The recessed portions R may be provided on one or both main surfaces of the laminate 10, but are preferably provided only on one main surface.
The corner portions and ridge portions of the laminate 10 are preferably rounded. The corner portion is a portion where three surfaces of the laminated body 10 intersect, and the ridge portion is a portion where two surfaces of the laminated body 10 intersect.
As shown in fig. 2 to 4, the multilayer body 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in the stacking direction T. The laminate 10 includes an inner layer 100 and a 1 st outer layer 101 and a 2 nd outer layer 102 arranged to sandwich the inner layer 100 in the lamination direction.
The inner layer portion 100 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged to face each other with the dielectric layer 20 interposed therebetween. The inner layer 100 is a portion (i.e., an effective region) that generates electrostatic capacitance and substantially functions as a capacitor.
The 1 st outer layer section 101 is disposed on the 1 st main surface TS1 side of the laminate 10, and the 2 nd outer layer section 102 is disposed on the 2 nd main surface TS2 side of the laminate 10. More specifically, the 1 st outer layer section 101 is disposed between the inner electrode layer 30 closest to the 1 st main surface TS1 among the plurality of inner electrode layers 30 and the 1 st main surface TS1, while the 2 nd outer layer section 102 is disposed between the inner electrode layer 30 closest to the 2 nd main surface TS2 among the plurality of inner electrode layers 30 and the 2 nd main surface TS 2.
The 1 st outer layer section 101 and the 2 nd outer layer section 102 each include the dielectric layer 2 and do not include the internal electrode layer 30.
These 1 st outer layer part 101 and 2 nd outer layer part 102 can function as a protective layer for the inner layer part 100.
The recessed portion R is present in one or both of the 1 st outer layer portion 101 and the 2 nd outer layer portion 102 in the LT cross section.
As the material of the dielectric layer 20, for example, BaTiO-containing material can be used 3 、CaTiO 3 、SrTiO 3 Or CaZrO 3 And the like as a main component. In addition to the main component, a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like may be added as a subcomponent.
The thickness of the dielectric layer 20 is not particularly limited, but is preferably 0.5 μm or more and 1.0 μm or less.
The number of the dielectric layers 20 is not particularly limited, but is preferably 7 or more and 22 or less in total number of the dielectric layers as the inner layer portion and the dielectric layers as the outer layer portion in relation to the number of the internal electrodes 30 described later.
The internal electrode layers 30 include a 1 st internal electrode layer 31 and a 2 nd internal electrode layer 32.
In the effective region 100, a plurality of 1 st internal electrode layers 31 and a plurality of 2 nd internal electrode layers 32 are alternately arranged.
The 1 st internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312, and the 2 nd internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322.
The opposite electrode portion 311 and the opposite electrode portion 321 face each other with the dielectric layer 20 interposed therebetween in the lamination direction T of the laminate 10. The shapes of the counter electrode portion 311 and the counter electrode portion 321 are not particularly limited, and may be, for example, substantially rectangular. The counter electrode portion 311 and the counter electrode portion 321 are portions that generate electrostatic capacitance and substantially function as capacitors.
The lead electrode portion 312 extends from the opposite electrode portion 311 toward the 1 st end surface LS1 of the laminate 10 and is exposed at the 1 st end surface LS 1. The lead electrode portion 322 extends from the opposite electrode portion 321 toward the 2 nd end surface LS2 of the laminate 10 and is exposed at the 2 nd end surface LS 2. The shapes of the lead electrode portion 312 and the lead electrode portion 322 are not particularly limited, and may be, for example, substantially rectangular.
Thus, the 1 st internal electrode layer 31 is connected to the 1 st external electrode 41, and a gap is formed between the 1 st internal electrode layer 31 and the 2 nd end surface LS2 of the laminate 10, that is, between the 1 st internal electrode layer 31 and the 2 nd external electrode 42. The 2 nd internal electrode layer 32 is connected to the 2 nd external electrode 42, and a gap is present between the 2 nd internal electrode layer 32 and the 1 st end surface LS1 of the laminate 10, that is, between the 2 nd internal electrode layer 32 and the 1 st external electrode 41.
The 1 st internal electrode layer 31 and the 2 nd internal electrode layer 32 contain, for example, metal Ni as a main component. The 1 st internal electrode layer 31 and the 2 nd internal electrode layer 32 may contain, for example, at least one selected from metals such as Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag — Pd alloys, as a main component, or may contain components other than the main component. Further, the 1 st internal electrode layer 31 and the 2 nd internal electrode layer 32 may contain, as components other than the main component, particles of a dielectric having the same composition system as the ceramic contained in the dielectric layer 20. In the present specification, the metal as the main component is defined as the metal component having the highest mass%.
The thickness of the 1 st internal electrode layer 31 and the 2 nd internal electrode layer 32 is not particularly limited, and is preferably 0.5 μm or more and 1.0 μm or less, for example.
The number of the 1 st internal electrode layer 31 and the 2 nd internal electrode layer 32 is not particularly limited, but is preferably, for example, 5 to 20 pieces depending on the number of the dielectric layers 20.
As shown in fig. 3, the laminate 10 includes, in the width direction W, electrode facing portions W30 where the internal electrode layers 30 face each other, and a 1 st lateral spacing portion WG1 and a 2 nd lateral spacing portion WG2 which are arranged so as to sandwich the electrode facing portion W30. The 1 st lateral spacing portion WG1 is located between the electrode facing portion W30 and the 1 st side surface WS1, and the 2 nd lateral spacing portion WG2 is located between the electrode facing portion W30 and the 2 nd side surface WS 2. More specifically, the 1 st lateral partition WG1 is located between the 1 st side surface WS1 and the 1 st side surface WS1 side end of the internal electrode layer 30, and the 2 nd lateral partition WG2 is located between the 2 nd side surface WS2 and the 2 nd side surface WS2 side end of the internal electrode layer 30. The 1 st lateral spacers WG1 and the 2 nd lateral spacers WG2 include only the dielectric layers 20, not the internal electrode layers 30. The 1 st lateral spacers WG1 and the 2 nd lateral spacers WG2 are portions that function as protective layers for the internal electrode layers 30. The 1 st lateral partition WG1 and the 2 nd lateral partition WG2 are also referred to as a W partition.
As shown in fig. 2, the laminate 10 has, in the longitudinal direction L, an electrode facing portion L30, a 1 st end spacer LG1, and a 2 nd end spacer LG2, in which the 1 st internal electrode layer 31 and the 2 nd internal electrode layer 32 of the internal electrode layers 30 face each other. The 1 st end partition LG1 is located between the electrode facing portion L30 and the 1 st end surface LS1, and the 2 nd end partition LG2 is located between the electrode facing portion L30 and the 2 nd end surface LS 2. More specifically, the 1 st end spacer LG1 is located between the 1 st end surface LS1 side end of the 2 nd inner electrode layer 32 and the 1 st end surface LS1, and the 2 nd end spacer LG2 is located between the 2 nd end surface LS2 side end of the 1 st inner electrode layer 31 and the 2 nd end surface LS 2. The 1 st end spacer LG1 includes the 1 st internal electrode layer 31 and the dielectric layers 20 without including the 2 nd internal electrode layer 32, and the 2 nd end spacer LG2 includes the 2 nd internal electrode layer 32 and the dielectric layers 20 without including the 1 st internal electrode layer 31. The 1 st end spacer LG1 functions as an extraction electrode portion of the 1 st inner electrode layer 31 toward the 1 st end surface LS1, and the 2 nd end spacer LG2 functions as an extraction electrode portion of the 2 nd inner electrode layer 32 toward the 2 nd end surface LS 2. The 1 st end spacer LG1 and the 2 nd end spacer LG2 are also referred to as L-spacing.
The counter electrode portion 311 of the 1 st internal electrode layer 31 and the counter electrode portion 321 of the 2 nd internal electrode layer 32 are positioned at the electrode facing portion L30. The lead electrode portion 312 of the 1 st inner electrode layer 31 is located at the 1 st end spacer portion LG1, and the lead electrode portion 322 of the 2 nd inner electrode layer 32 is located at the 2 nd end spacer portion LG 2.
A height T1 of the 1 st outer layer section, which is a region sandwiched between the 1 st main surface and the inner electrode disposed closest to the 1 st main surface in the stacking direction T, and a height T2 of the 2 nd outer layer section, which is a region sandwiched between the 2 nd main surface and the inner electrode disposed closest to the 2 nd main surface in the stacking direction T, satisfy the following equations: t1 > T2, and the height of the laminate (which is the height excluding the external electrodes) is 170 μm or more and 190 μm or less.
As a method for measuring the thickness of the dielectric layers 20 and the internal electrode layers 30, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope is cited. The measurement value may be an average value of measurement values at a plurality of positions in the longitudinal direction and/or an average value of measurement values at a plurality of positions in the stacking direction T, from the viewpoint of obtaining an appropriate representative value.
Similarly, as a method for measuring the height of the laminate 10, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing or a WT cross section near the center in the length direction of the laminate exposed by polishing with a scanning electron microscope is cited. As the measurement value, an average value of measurement values at a plurality of positions in the longitudinal direction or the width direction can be used from the viewpoint of obtaining an appropriate representative value.
Similarly, as a method for measuring the length of the laminate 10, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope can be cited. As the measurement value, an average value of measurement values at a plurality of positions in the stacking direction T can be used from the viewpoint of obtaining an appropriate representative value.
Similarly, as a method for measuring the width of the laminate 10, for example, a method of observing a WT cross section near the center in the longitudinal direction of the laminate exposed by polishing with a scanning electron microscope can be cited. As this value, from the viewpoint of obtaining an appropriate representative value, an average value of measurement values at a plurality of positions in the stacking direction T can be used.
The external electrodes 40 include a 1 st external electrode 41 and a 2 nd external electrode 42.
The 1 st external electrode 41 is disposed on the 1 st end surface LS1 of the laminate 10 and connected to the 1 st internal electrode layer 31. The 1 st outer electrode 41 may extend from the 1 st end surface LS1 to a portion of the 1 st main surface TS1 and a portion of the 2 nd main surface TS 2. In addition, the 1 st external electrode 41 may also extend from the 1 st end surface LS1 to a portion of the 1 st side surface WS1 and a portion of the 2 nd side surface WS 2.
The 2 nd external electrode 42 is disposed on the 2 nd end surface LS2 of the laminate 10 and connected to the 2 nd internal electrode layer 32. The 2 nd external electrode 42 may extend from the 2 nd end surface LS2 to a part of the 1 st main surface TS1 and a part of the 2 nd main surface TS 2. In addition, the 2 nd external electrode 42 may also extend from the 2 nd end surface LS2 to a part of the 1 st side surface WS1 and a part of the 2 nd side surface WS 2.
The 1 st external electrode 41 has a 1 st base electrode layer 415, a 1 st inner plating layer 416, and a 1 st surface plating layer 417, and the 2 nd external electrode 42 has a 2 nd base electrode layer 425, a 2 nd inner plating layer 426, and a 2 nd surface plating layer 427.
The 1 st underlying electrode layer 415 is disposed on the 1 st end surface LS1 of the stacked body 10 and covers the 1 st end surface LS1 of the stacked body 10. The 1 st underlying electrode layer 415 may extend from the 1 st end surface LS1 to a portion of the 1 st main surface TS1, a portion of the 2 nd main surface TS2, a portion of the 1 st side surface WS1, and a portion of the 2 nd side surface WS 2.
The 2 nd base electrode layer 425 is disposed on the 2 nd end surface LS2 of the stacked body 10, and covers the 2 nd end surface LS2 of the stacked body 10. The 2 nd underlying electrode layer 425 may extend from the 2 nd end surface LS2 to a portion of the 1 st main surface TS1, a portion of the 2 nd main surface TS2, a portion of the 1 st side surface WS1, and a portion of the 2 nd side surface WS 2.
The 1 st base electrode layer 415 and the 2 nd base electrode layer 425 may be fired layers containing metal and glass. The glass may be a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, and the like. As a specific example, borosilicate glass can be used. The metal contains Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, and Au, or alloys such as Ag — Pd alloys, as a main component, or may contain other components than the main component.
The fired layer is a layer obtained by applying a conductive paste containing metal and glass to a laminate by a dipping method and firing the paste. The internal electrode layers may be fired after firing, or may be fired simultaneously with the firing of the internal electrode layers. Further, the fired layer may be a multilayer.
Alternatively, the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the fired layer, or may be formed directly on the laminate without forming the fired layer.
The resin layer is a layer obtained by applying a conductive paste containing conductive particles and a thermosetting resin to a laminate by a coating method and firing the applied paste. The internal electrode layers may be fired after firing, or may be fired simultaneously with the firing of the internal electrode layers. Further, the resin layer may be a multilayer.
The thickness of each of the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 which are fired layers or resin layers is not particularly limited, and may be, for example, 1 μm or more and 10 μm or less.
Alternatively, the 1 st lower electrode layer 415 and the 2 nd lower electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film formation method such as a sputtering method or a vapor deposition method and deposited with metal particles.
The 1 st undercoat layer 416 is disposed on the 1 st base electrode layer 415, and covers at least a portion of the 1 st base electrode layer 415. The 2 nd undercoat layer 426 is disposed on the 2 nd base electrode layer 425 and covers at least a portion of the 2 nd base electrode layer 425. The 1 st and 2 nd inner plating layers 416 and 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag — Pd alloys.
The 1 st surface plating layer 417 is disposed on the 1 st inner plating layer 416 and covers at least a part of the 1 st inner plating layer 416. The 2 nd surface plating layer 427 is disposed on the 2 nd inner plating layer 426, and covers at least a part of the 2 nd inner plating layer 426. The 1 st surface plating layer 417 and the 2 nd surface plating layer 427 include, for example, a metal such as Sn.
Preferably, the 1 st inner plating layer 416 and the 2 nd inner plating layer 426 are Ni plating layers, and the 1 st surface plating layer 417 and the 2 nd surface plating layer 427 are Sn plating layers. The Ni plating layer can prevent solder corrosion when the base electrode layer is mounted on the multilayer ceramic capacitor 1, and the Sn plating layer can improve the wettability of the solder when the multilayer ceramic capacitor 1 is mounted, and can be easily mounted. In other words, the 1 st inner plating layer 416 and the 2 nd inner plating layer 426 have lower solder wettability than the 1 st surface plating layer 417 and the 2 nd surface plating layer 427.
Preferably, the external electrode is a combination of a firing electrode of Cu, a Ni plating layer, and a Su plating layer.
The thickness of the 1 st plating layer composed of the 1 st inner plating layer 416 and the 1 st surface plating layer 417 is not particularly limited, and may be 1 μm or more and 10 μm or less. The thickness of the 2 nd plating layer composed of the 2 nd inner plating layer 426 and the 2 nd surface plating layer 427 is not particularly limited, and may be 1 μm or more and 10 μm or less.
The length of the entire multilayer ceramic capacitor 1 in the longitudinal direction L is 400 μm or more and 440 μm or less. Here, the "overall length" is a length including the two external electrodes (the 1 st external electrode 41 and the 2 nd external electrode 42) and the laminate 10.
< production method >
Next, an example of the method for manufacturing the multilayer ceramic capacitor 1 will be described. First, dielectric sheets for the dielectric layers 20 and conductive pastes for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. As the binder and the solvent, known materials can be used.
Next, the internal electrode pattern is formed on the dielectric sheet by printing, for example, a conductive paste in a predetermined pattern on the dielectric sheet. As a method for forming the internal electrode pattern, screen printing, gravure printing, or the like can be used.
Next, a predetermined number of dielectric sheets for the 2 nd outer layer section 102 on which the internal electrode patterns are not printed are stacked. On this, dielectric sheets for the inner layer portion 100 on which the inner electrode patterns are printed are sequentially laminated. On this, a predetermined number of dielectric sheets for the 1 st outer layer section 101 on which the internal electrode patterns are not printed are laminated.
Next, the laminated sheet is pressed in the lamination direction by a method such as isostatic pressing using a die corresponding to the shape of the recess R, thereby producing a laminated block. Next, the laminated block is cut into a predetermined size, and cut into laminated chips having a shape of the recess R. In this case, the corners and ridge portions of the laminated chips are rounded by barrel polishing or the like. Next, the stacked chips are fired to produce a stacked body 10. The firing temperature depends on the materials of the dielectric and the internal electrode, but is preferably 900 ℃ to 1400 ℃.
Next, the 1 st end surface LS1 of the laminate 10 was immersed in a conductive paste as an electrode material for the base electrode layer by an immersion method, and the conductive paste for the 1 st base electrode layer 415 was applied to the 1 st end surface LS 1. Similarly, the 2 nd end surface LS2 of the laminate 10 is immersed in a conductive paste as an electrode material for the base electrode layer by an immersion method, and the conductive paste for the 2 nd base electrode layer 425 is applied to the 2 nd end surface LS 2. Then, by firing these conductive pastes, the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 which are fired layers are formed. The firing temperature is preferably 600 ℃ to 900 ℃.
As described above, the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 which are resin layers may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and firing the paste, or the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 which are thin films may be formed by a thin film forming method such as a sputtering method or a vapor deposition method.
Then, a 1 st undercoat layer 416 is formed on the surface of the 1 st base electrode layer 415, and a 2 nd undercoat layer 426 is formed on the surface of the 2 nd base electrode layer 425. Then, a 1 st surface plating layer 417 is formed on the surface of the 1 st inner plating layer 416, and a 2 nd surface plating layer 427 is formed on the surface of the 2 nd inner plating layer 426.
Then, the 1 st outer electrode 41 is formed by removing the 1 st surface plating layer 417 from the center portion of the 1 st outer electrode 41 to expose the 1 st inner plating layer 416. Further, the 2 nd outer electrode 42 is formed by removing the 2 nd topcoat plating layer 427 to expose the 2 nd inner plating layer 426 in the central portion of the 2 nd outer electrode 42.
Through the above steps, the multilayer ceramic capacitor 1 described above can be obtained.
In contrast to the conventional multilayer ceramic capacitor, which cannot accommodate warpage or warpage of a substrate to be mounted, and as a result, defects such as cracks may occur in the capacitor, the ceramic capacitor of the present invention can suppress the occurrence of such defects.
While the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various changes and modifications can be made.
Claims (5)
1. A multilayer ceramic capacitor is provided with:
a laminate body having an inner layer portion as an effective region in which a plurality of dielectric layers and internal electrode layers are alternately laminated, and an outer layer portion disposed on both sides of the inner layer portion in a lamination direction; and
external electrodes provided on the 1 st end surface on one side and the 2 nd end surface on the other side in the longitudinal direction of the laminate body intersecting the lamination direction,
the multilayer ceramic capacitor is characterized by comprising:
a laminate having two main surfaces facing each other in the lamination direction, two side surfaces facing each other in a width direction intersecting the lamination direction, and two end surfaces facing each other in a longitudinal direction intersecting the lamination direction and the width direction; and two external electrodes disposed on the two end surfaces of the laminate, respectively,
the height of the inner layer portion is equal to or greater than 1/3, and at least one of the two outer layer portions has a recess.
2. The laminated ceramic capacitor according to claim 1,
the thickness T1 of the 1 st outer layer section disposed on one of the two main surfaces is greater than the thickness T2 of the 2 nd outer layer section disposed on the other of the two main surfaces, and the 1 st outer layer section has the recessed portion.
3. The laminated ceramic capacitor according to claim 1,
the number of the internal electrode layers is 5 to 20.
4. The laminated ceramic capacitor according to any one of claims 1 to 3,
the dielectric layer has a thickness of 15 μm or more and 22 μm or less.
5. The laminated ceramic capacitor according to any one of claims 1 to 3,
the thickness of the dielectric layer is 0.5 [ mu ] m or more and 1.0 [ mu ] m or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220118035.5U CN217061783U (en) | 2022-01-17 | 2022-01-17 | Multilayer ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220118035.5U CN217061783U (en) | 2022-01-17 | 2022-01-17 | Multilayer ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217061783U true CN217061783U (en) | 2022-07-26 |
Family
ID=82480479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220118035.5U Active CN217061783U (en) | 2022-01-17 | 2022-01-17 | Multilayer ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217061783U (en) |
-
2022
- 2022-01-17 CN CN202220118035.5U patent/CN217061783U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10366838B2 (en) | Laminated ceramic electronic component and method for manufacturing same | |
| KR102077617B1 (en) | Multilayer ceramic capacitor | |
| KR102044370B1 (en) | Multilayer ceramic capacitor and multilayer-ceramic-capacitor-mounted structure | |
| CN113140405B (en) | Multilayer ceramic capacitor | |
| KR101925286B1 (en) | Laminated ceramic electronic component | |
| CN114334442A (en) | Multilayer ceramic capacitor | |
| CN114334449A (en) | Multilayer ceramic capacitor | |
| CN111755245B (en) | Multilayer ceramic capacitor | |
| CN114334441A (en) | Multilayer ceramic capacitor | |
| CN114334443A (en) | Multilayer ceramic capacitor | |
| CN217061783U (en) | Multilayer ceramic capacitor | |
| CN216773068U (en) | Multilayer ceramic capacitor | |
| CN216015095U (en) | Multilayer ceramic capacitor | |
| JP2023019368A (en) | Multilayer ceramic capacitor | |
| JP2019106443A (en) | Multilayer ceramic capacitor and method of manufacturing the same | |
| CN216773069U (en) | Multilayer ceramic capacitor | |
| CN216015096U (en) | Multilayer ceramic capacitor | |
| CN216773071U (en) | Multilayer ceramic capacitor | |
| CN217214474U (en) | Multilayer ceramic capacitor | |
| CN216119933U (en) | Multilayer ceramic capacitor | |
| CN217544377U (en) | Multilayer ceramic capacitor | |
| CN217035414U (en) | Multilayer ceramic capacitor | |
| CN216749609U (en) | Multilayer ceramic capacitor | |
| CN218351295U (en) | Multilayer ceramic capacitor | |
| CN217562409U (en) | Multilayer ceramic capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |