CN218351295U - Multilayer ceramic capacitor - Google Patents

Abstract

The utility model provides a laminated ceramic capacitor that ESR is low. A multilayer ceramic capacitor is provided with: and a laminate in which dielectric layers and internal electrode layers made of a ceramic material are alternately laminated, the laminate including a1 st external electrode and a 2 nd external electrode that face each other, the laminate including a1 st effective portion and a 2 nd effective portion arranged in a laminating direction, the 1 st effective portion being formed by laminating a plurality of layers of the 1 st dielectric layer and the 1 st internal electrode layer, the 2 nd effective portion being formed by laminating a plurality of layers of the 2 nd dielectric layer and the 2 nd internal electrode layer, and a recess being provided in at least one of the 1 st external electrode and the 2 nd external electrode at a position corresponding to any of the 1 st effective portion and the 2 nd effective portion.

Description

Multilayer ceramic capacitor

Technical Field

The utility model relates to a range upon range of ceramic capacitor.

Background

Patent document 1 discloses a laminated ceramic capacitor. Such a multilayer ceramic capacitor includes: a laminate in which a plurality of dielectric layers containing a ceramic material and a plurality of internal electrode layers are laminated; and an external electrode provided on an end face of the laminate.

Prior art documents

Patent document

Patent document 1: japanese patent laid-open publication No. 2016-76582

For such a multilayer ceramic capacitor, a multilayer ceramic capacitor having a low Equivalent Series Resistance (ESR) is required.

SUMMERY OF THE UTILITY MODEL

Problem to be solved by utility model

The utility model aims to provide a low ESR laminated ceramic capacitor easily.

Means for solving the problems

The laminated ceramic capacitor according to the present invention is a laminated ceramic capacitor comprising,

the disclosed device is provided with: a laminate in which dielectric layers containing a ceramic material and internal electrode layers are alternately laminated,

the laminate includes a1 st external electrode and a 2 nd external electrode opposed to each other,

the laminate comprises a1 st effective part and a 2 nd effective part arranged in the laminating direction,

the 1 st effective part is formed by laminating a plurality of layers of a1 st dielectric layer and a1 st internal electrode layer,

the 2 nd effective part is formed by laminating a plurality of layers of the 2 nd dielectric layer and the 2 nd internal electrode layer,

at least one of the 1 st external electrode and the 2 nd external electrode is provided with a recess at a position corresponding to any one of the 1 st effective part and the 2 nd effective part.

The effect of the present invention is according to the present invention, a laminated ceramic capacitor having a low ESR can be easily provided.

Drawings

Fig. 1 is a perspective view showing a multilayer ceramic capacitor according to the present embodiment.

Fig. 2 is a sectional view taken along line II-II (LT section) of the laminated ceramic capacitor shown in fig. 1.

Fig. 3 is a sectional view taken along line III-III (WT section) of the laminated ceramic capacitor shown in fig. 1.

Description of the reference numerals

1: a laminated ceramic capacitor;

10: a laminate;

20: a dielectric layer;

21: a1 st dielectric layer;

22: a 2 nd dielectric layer;

23: an effective inter-portion dielectric layer;

30: an internal electrode layer;

31: 1 st internal electrode layer;

31A: a1 st internal electrode layer (1 st external electrode side);

311A: a1 st counter electrode portion (1 st outer electrode side);

312A: a1 st extraction electrode portion (1 st external electrode side);

31B: a1 st internal electrode layer (2 nd external electrode side);

311B, a step of: a1 st counter electrode portion (2 nd outer electrode side);

312B: a1 st extraction electrode portion (2 nd external electrode side);

32: 2 nd internal electrode layer;

32A: a 2 nd inner electrode layer (1 st outer electrode side);

321A: a 2 nd counter electrode portion (1 st outer electrode side);

322A: a 2 nd extraction electrode portion (1 st external electrode side);

32B: a 2 nd inner electrode layer (2 nd outer electrode side);

321B, and (3) respectively: a 2 nd counter electrode portion (2 nd outer electrode side);

322B: a 2 nd extraction electrode portion (2 nd external electrode side);

40: an external electrode;

401: an outermost surface of the outer electrode;

41: 1 st external electrode;

415: 1 st base electrode layer;

416: 1 st inner plating layer;

417: 1, plating a layer outside;

42: a 2 nd external electrode;

425: the 2 nd base electrode layer;

426: 2 nd inner plating layer;

427: 2, plating layer;

50: a recess;

51: 1 st recess;

511: 1 st recess top;

512: the abdomen of the 1 st concavity;

513: the bottom of the 1 st recess;

52: a 2 nd recess;

521: the top of the 2 nd recess;

522: the abdomen of the 2 nd concavity;

523: the bottom of the 2 nd recess;

100: an inner layer portion;

101: the 1 st outer layer part;

102: a 2 nd outer layer part;

110: the 1 st effective part;

120: the 2 nd effective part;

l30: an electrode opposing portion;

LG1: 1 st end spacer;

LG2: a 2 nd end spacer;

w30: an electrode opposing portion;

WG1: a1 st lateral spacer;

WG2: a 2 nd lateral spacing part;

l: a length direction;

t: a stacking direction;

w: a width direction;

LS1: 1 st end face;

LS2: a 2 nd end face;

TS1: a1 st main surface;

and (TS 2): a 2 nd main surface;

WS1: a1 st side;

WS2: a 2 nd side;

w1: the top width of the recess (width of the top);

w2: the width of the abdomen (width of the abdomen) of the recess.

Detailed Description

Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals.

< overview of laminated Structure >

Fig. 1 is a perspective view showing a laminated ceramic capacitor according to the present embodiment, fig. 2 is a sectional view taken along line II-II of the laminated ceramic capacitor shown in fig. 1, and fig. 3 is a sectional view taken along line III-III of the laminated ceramic capacitor shown in fig. 1. The multilayer ceramic capacitor 1 shown in fig. 1 to 3 includes a multilayer body 10 and external electrodes 40. The external electrodes 40 include a1 st external electrode 41 and a 2 nd external electrode 42.

< definition of Direction >

An XYZ orthogonal coordinate system is shown in fig. 1 to 3. The X direction is the longitudinal direction L of the multilayer ceramic capacitor 1 and the multilayer body 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10, and the Z direction is the stacking direction T of the multilayer ceramic capacitor 1 and the multilayer body 10. Thus, the cross section shown in fig. 2 is also referred to as LT cross section and the cross section shown in fig. 3 is also referred to as WT cross section. In addition, a cross section orthogonal to both the LT cross section and the WT cross section is referred to as an LW cross section.

The longitudinal direction L, the width direction W, and the stacking direction T are not necessarily orthogonal to each other, and may be orthogonal to each other.

< layered product >

The laminate 10 has a substantially rectangular parallelepiped shape, and has a1 st main surface TS1 and a 2 nd main surface TS2 opposed in the lamination direction T, a1 st side surface WS1 and a 2 nd side surface WS2 opposed in the width direction W, and a1 st end surface LS1 and a 2 nd end surface LS2 opposed in the longitudinal direction L.

The corner portions and ridge portions of the laminate 10 are preferably rounded. The corner portion is a portion where three surfaces of the laminate 10 intersect, and the ridge portion is a portion where two surfaces of the laminate 10 intersect.

As shown in fig. 2 and 3, the stacked body 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in the stacking direction T.

The laminate 10 has an inner layer 100 and a1 st outer layer 101 and a 2 nd outer layer 102 disposed so as to sandwich the inner layer 100 in the lamination direction T.

< inner layer part >

The inner layer portion 100 includes a part of the plurality of dielectric layers 20 and the plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged to face each other with the dielectric layer 20 interposed therebetween. The inner layer 100 is a portion that generates electrostatic capacitance and substantially functions as a capacitor. Therefore, the inner layer portion 100 is also referred to as an effective portion.

< effective section >

In the laminated ceramic capacitor 1 of the present embodiment, the effective portion includes two effective portions, i.e., the 1 st effective portion 110 and the 2 nd effective portion 120. The 1 st effective portion 110 and the 2 nd effective portion 120 are stacked in the stacking direction T. Fig. 2 illustrates a structure in which the 1 st effective portion 110 is located on the 1 st main surface TS1 side and the 2 nd effective portion 120 is located on the 2 nd main surface TS2 side.

< outer layer section >

The 2 nd outer layer section 102 is disposed on the 1 st main surface TS1 side of the laminate 10, and the 1 st outer layer section 101 is disposed on the 2 nd main surface TS2 side of the laminate 10.

More specifically, the 2 nd outer layer section 102 is disposed between the 1 st main surface TS1 and the inner electrode layer 30 closest to the 1 st main surface TS1 among the plurality of inner electrode layers 30, and the 1 st outer layer section 101 is disposed between the 2 nd main surface TS2 and the inner electrode layer 30 closest to the 2 nd main surface TS2 among the plurality of inner electrode layers 30. The 1 st outer layer section 101 and the 2 nd outer layer section 102 do not include the internal electrode layer 30, and each include a portion of the plurality of dielectric layers 20 other than the portion for the inner layer section 100. The 1 st outer layer portion 101 and the 2 nd outer layer portion 102 function as a protective layer of the inner layer portion 100.

< division in the longitudinal direction L >

As shown in fig. 2, the laminate 10 includes, in the longitudinal direction L, an electrode facing portion L30 in which the internal electrode layers 30 face each other, a1 st end spacer LG1, and a 2 nd end spacer LG2. The 1 st end spacer LG1 is located between the electrode facing portion L30 and the 1 st end surface LS1, and the 2 nd end spacer LG2 is located between the electrode facing portion L30 and the 2 nd end surface LS2.

The 1 st end spacer LG1 functions as an extraction electrode portion of the internal electrode layer 30 to the 1 st end surface LS1, and the 2 nd end spacer LG2 functions as an extraction electrode portion of the internal electrode layer 30 to the 2 nd end surface LS2. The 1 st end spacer LG1 and the 2 nd end spacer LG2 are also referred to as L-spaces.

< Cross-sectional Structure in the Width Direction W >

Next, a cross-sectional structure of the multilayer body 10 in the width direction W will be described with reference to fig. 3.

As shown in fig. 3, the laminate 10 includes, in the width direction W, an electrode facing portion W30 in which the internal electrode layers 30 face each other, and a1 st lateral spacing portion WG1 and a 2 nd lateral spacing portion WG2 which are arranged so as to sandwich the electrode facing portion W30. The 1 st lateral spacing portion WG1 is located between the electrode facing portion W30 and the 1 st side surface WS1, and the 2 nd lateral spacing portion WG2 is located between the electrode facing portion W30 and the 2 nd side surface WS 2. More specifically, the 1 st lateral spacer WG1 is located between the 1 st side surface WS1 and the 1 st end surface WS1 of the internal electrode layer 30, and the 2 nd lateral spacer WG2 is located between the 2 nd side surface WS2 and the 2 nd end surface WS2 of the internal electrode layer 30. The 1 st lateral spacers WG1 and the 2 nd lateral spacers WG2 include only the dielectric layers 20, without including the internal electrode layers 30. The 1 st lateral spacers WG1 and the 2 nd lateral spacers WG2 are portions that function as protective layers for the internal electrode layers 30. The 1 st lateral spacing portion WG1 and the 2 nd lateral spacing portion WG2 are also referred to as a W space.

< size of laminate >

The dimension of the laminate 10 is not particularly limited, but for example, the length in the longitudinal direction L is preferably 1.55mm or more and 1.65mm or less, the width in the width direction W is preferably 0.75mm or more and 0.85mm or less, and the thickness in the lamination direction T is preferably 0.75mm or more and 0.85mm or less.

< 1 st and 2 nd internal electrode layers >

The internal electrode layers 30 include a plurality of 1 st internal electrode layers 31 and a plurality of 2 nd internal electrode layers 32.

The 1 st inner electrode layer 31 is an inner electrode layer 30 located closer to the 1 st main surface TS1 side than the 2 nd inner electrode layer 32 in the stacking direction T. On the other hand, the 2 nd inner electrode layer 32 is the inner electrode layer 30 located closer to the 2 nd main surface TS2 side than the 1 st inner electrode layer 31 in the stacking direction T.

As described above, the laminated ceramic capacitor 1 of the present embodiment has the 1 st and 2 nd effective parts 110 and 120 laminated in the lamination direction T. The 1 st internal electrode layer 31 is related to the formation of the 1 st effective part 110, and the 2 nd internal electrode layer 32 is related to the formation of the 2 nd effective part 120.

The 1 st internal electrode layer 31 includes a1 st internal electrode layer 31A on the 1 st external electrode side extending from the 1 st external electrode 41 toward the 2 nd external electrode 42, and a1 st internal electrode layer 31B on the 2 nd external electrode side extending from the 2 nd external electrode 42 toward the 1 st external electrode 41, opposite thereto.

Similarly, the 2 nd internal electrode layer 32 includes a1 st external electrode side 2 nd internal electrode layer 32A extending from the 1 st external electrode 41 toward the 2 nd external electrode 42, and a 2 nd external electrode side 2 nd internal electrode layer 32B extending from the 2 nd external electrode 42 toward the 1 st external electrode 41, opposite thereto.

< suffixes A and B >

Hereinafter, the internal electrode layer 30 may be formed by adding a suffix a to a member extending from the 1 st external electrode side. Similarly, the internal electrode layer 30 may be formed by adding a suffix B to a member extending from the 2 nd external electrode side.

< counter electrode section and extraction electrode section >

The 1 st internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312. Similarly, the 2 nd internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322.

The counter electrode portion is a portion that generates capacitance by facing another counter electrode portion with a dielectric layer interposed therebetween. On the other hand, the lead electrode portion is a portion connecting the counter electrode portion and the external electrode.

Specifically, the 1 st internal electrode layer 31 includes a counter electrode portion 311A and a lead electrode portion 312A extending from the 1 st external electrode side, and a counter electrode portion 311B and a lead electrode portion 312B extending from the 2 nd external electrode side.

Similarly, the 2 nd internal electrode layer 32 includes a counter electrode portion 321A and a lead electrode portion 322A extending from the 1 st external electrode side, and a counter electrode portion 321B and a lead electrode portion 322B extending from the 2 nd external electrode side.

< opposing electrode section >

In the laminated ceramic capacitor 1 of the present embodiment, the counter electrode portion 311A and the counter electrode portion 311B face each other in the lamination direction T with the dielectric layer 20 interposed therebetween. Similarly, the counter electrode portion 321A and the counter electrode portion 321B face each other in the lamination direction T through the dielectric layer 20. Electrostatic capacitance is generated in the facing portion to form an effective portion.

More specifically, the 1 st effective portion 110 is formed by the opposing electrode portion 311A and the opposing electrode portion 311B opposing each other. Similarly, the 2 nd effective portion 120 is formed by the opposing electrode portion 321A and the opposing electrode portion 321B facing each other.

The shapes of the counter electrode portion 311 and the counter electrode portion 321 are not particularly limited, and may be, for example, substantially rectangular.

< extraction electrode section >

The lead electrode portion connects the counter electrode portion and the external electrode.

Specifically, the 1 st lead electrode portion 312A extends from the 1 st counter electrode portion 311A toward the 1 st end surface LS1, and is connected to the 1 st outer electrode 41. The 1 st lead electrode portion 312B extends from the 1 st counter electrode portion 311B toward the 2 nd end surface LS2, and is connected to the 2 nd external electrode 42.

Similarly, the 2 nd lead electrode portion 322A extends from the 2 nd opposite electrode portion 321A toward the 1 st end surface LS1, and is connected to the 1 st outer electrode 41. The 2 nd lead electrode portion 322B extends from the 2 nd opposite electrode portion 321B toward the 2 nd end surface LS2, and is connected to the 2 nd outer electrode 42.

< materials of internal electrode layers >

The internal electrode layers 30 contain, for example, metal Cu as a main component. The internal electrode layers 30 may contain, for example, at least one selected from metals such as Ni, ag, pd, and Au, or alloys containing at least one of these metals, such as Ag — Pd alloys, as a main component, or may contain components other than the main component. Further, the internal electrode layer 30 may contain, as a component other than the main component, particles of a dielectric having the same composition system as the ceramic contained in the dielectric layer 20. In the present specification, the metal as the main component is defined as the metal component having the highest mass%.

< thickness and number of internal electrode layers >

The thickness of the internal electrode layer 30 is not particularly limited, but may be, for example, 0.8 μm or more and 1.2 μm or less. The number of internal electrode layers 30 is not particularly limited, but is preferably 20 or more and 300 or less, for example.

< materials for dielectrics >

As the material of the dielectric layer 20, for example, a dielectric ceramic containing a ceramic material containing at least any one of Ca, zr, and Ti as a main component can be used. A multilayer ceramic capacitor using the dielectric ceramic is more suitable for a high-frequency circuit.

Specifically, for example, the dielectric ceramic can have, as a main component, a ceramic material containing Ca and Zr and having a general formula ABO ₃ The perovskite structure shown. The ceramic material having such a perovskite structure may be, for example, caZrO ₃ (calcium zirconate), tiO ₂ (titanium oxide), but is not limited thereto. The ceramic material forming the dielectric ceramic layer 15 may contain all of Ca, zr, and Ti as a main component. In addition, caZrO can also be used ₃ In which Ti replaces ZrO ₃ Or Ca (Zr0.9Ti0.1) O as a part of Zr ₃ And so on.

Further, (Ca) may be used as a ceramic material for forming the dielectric ceramic layer 15 _1-x-y 、Sr _x 、Ba _y ) _m (Zr _1-z-α 、Ti _z 、Hf _α )O ₃ (wherein x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, and m is 1.0 or more and 1.1 or moreAnd z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less).

In addition to the above-described main component, additives may be added according to the purpose. Examples of such additives include oxides of rare earth elements such as Mn, mg, dy, cr, V, sm, eu, gd, tb, ho, er, tm, yb, Y, oxides of Co, ni, li, B, na, K, and Si, and glass.

< thickness and Material of dielectric layer >

The thickness of the dielectric layer 20 is not particularly limited, but is preferably 1.1 μm or more and 3.0 μm or less, for example.

The number of dielectric layers 20 is not particularly limited, but is preferably 20 to 300, for example. The number of the dielectric layers 20 is the total number of the dielectric layers in the inner layer portion and the dielectric layers in the outer layer portion.

< capacitance of effective portion >

In the laminated ceramic capacitor 1 of the present embodiment, the capacitances can be made different in the 1 st effective part 110 and the 2 nd effective part 120. This makes it possible to easily adjust the total capacitance of the multilayer ceramic capacitor 1.

As a method of making the capacitances of the 1 st effective section 110 and the 2 nd effective section 120 different from each other, for example, there is a method of making a distance in the stacking direction T of the internal electrode layers 30 adjacent to each other in the stacking direction T in the 1 st effective section 110 and a distance in the stacking direction T of the internal electrode layers 30 adjacent to each other in the stacking direction T in the 2 nd effective section 120 different from each other. Specifically, there are methods of making the number of dielectric layers and internal electrode layers to be stacked different or making the dielectric layers different in thickness in the 1 st effective part 110 and the 2 nd effective part 120.

Here, the dielectric layer 20 included in the 1 st effective part 110 is referred to as a1 st dielectric layer 21, and the dielectric layer 20 included in the 2 nd effective part 120 is referred to as a 2 nd dielectric layer 22. As the above method, for example, there is a method in which the thickness of the 1 st dielectric layer 21 is set to 1.5 μm and the thickness of the 2 nd dielectric layer 22 is set to 2.5 μm. This makes it possible to increase the capacitance of the 1 st effective part 110 to be larger than the capacitance of the 2 nd effective part 120.

< dielectric layer between effective sections >

The dielectric layer between the 1 st effective portion 110 and the 2 nd effective portion 120 is an inter-effective-portion dielectric layer 23. The thickness of the effective inter-portion dielectric layer 23 may be different from the thickness of the 1 st dielectric layer 21 and the thickness of the 2 nd dielectric layer 22. Specifically, the thickness of the effective inter-portion dielectric layer 23 is preferably made larger than the thickness of the 1 st dielectric layer 21 and the thickness of the 2 nd dielectric layer 22.

This allows the 1 st and 2 nd effective parts 110 and 120 to be electrically distinguished more clearly. As a result, the total capacitance of the multilayer ceramic capacitor 1 can be adjusted more accurately.

The thickness of the inter-effective-portion dielectric layer 23 means an apparent thickness of the dielectric layer between the 1 st effective portion 110 and the 2 nd effective portion 120. The apparent thickness means the thickness of the entire dielectric layer between the 1 st effective portion 110 and the 2 nd effective portion 120, regardless of whether the inter-effective-portion dielectric layer 23 is formed of one dielectric layer or a plurality of dielectric layers.

Examples of the method for making the thickness of the effective inter-dielectric layer 23 larger than the thickness of the 1 st dielectric layer 21 and the thickness of the 2 nd dielectric layer 22 include a method of increasing the number of dielectric layers forming the effective inter-dielectric layer 23 or a method of increasing the thickness of one dielectric layer.

< external electrode >

Next, the external electrode 40 will be explained.

The external electrodes 40 include a1 st external electrode 41 and a 2 nd external electrode 42.

The 1 st external electrode 41 is disposed on the 1 st end surface LS1 of the laminate 10 and connected to the 1 st internal electrode layer 31. The 1 st external electrode 41 may extend from the 1 st end surface LS1 to a part of the 1 st main surface TS1 and a part of the 2 nd main surface TS 2. The 1 st external electrode 41 may extend from the 1 st end surface LS1 to a portion of the 1 st side surface WS1 and a portion of the 2 nd side surface WS 2.

The 2 nd external electrode 42 is disposed on the 2 nd end surface LS2 of the laminate 10 and connected to the 2 nd internal electrode layer 32. The 2 nd outer electrode 42 may extend from the 2 nd end surface LS2 to a part of the 1 st main surface TS1 and a part of the 2 nd main surface TS 2. The 2 nd external electrode 42 may extend from the 2 nd end surface LS2 to a portion of the 1 st side surface WS1 and a portion of the 2 nd side surface WS 2.

The 1 st external electrode 41 has a1 st base electrode layer 415, a1 st inner plating layer 416, and a1 st outer plating layer 417, and the 2 nd external electrode 42 has a 2 nd base electrode layer 425, a 2 nd inner plating layer 426, and a 2 nd outer plating layer 427.

< underlying electrode layer >

The 1 st underlying electrode layer 415 is disposed on the 1 st end surface LS1 of the stacked body 10, and covers the 1 st end surface LS1 of the stacked body 10. The 1 st base electrode layer 415 may extend from the 1 st end surface LS1 to a portion of the 1 st main surface TS1, a portion of the 2 nd main surface TS2, a portion of the 1 st side surface WS1, and a portion of the 2 nd side surface WS 2.

The 2 nd base electrode layer 425 is disposed on the 2 nd end surface LS2 of the stacked body 10, and covers the 2 nd end surface LS2 of the stacked body 10. The 2 nd underlying electrode layer 425 may extend from the 2 nd end surface LS2 to a portion of the 1 st main surface TS1, a portion of the 2 nd main surface TS2, a portion of the 1 st side surface WS1, and a portion of the 2 nd side surface WS 2.

The 1 st base electrode layer 415 and the 2 nd base electrode layer 425 may be fired layers containing metal and glass. The glass may be a glass component containing at least one selected from B, si, ba, mg, A1, li, and the like. As a specific example, borosilicate glass can be used. The metal contains Cu as a main component. The metal may contain at least one selected from metals such as Ni, ag, pd, and Au, or alloys such as Ag — Pd alloys, as a main component, or may contain other components than the main component.

The fired layer is a layer obtained by applying a conductive paste containing metal and glass to a laminate by a dipping method and firing the paste. The internal electrode layers may be fired after firing, or may be fired simultaneously with the firing of the internal electrode layers. The fired layer may be a plurality of layers.

Alternatively, the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the fired layer, or may be formed directly on the laminate without forming the fired layer.

The resin layer is a layer obtained by applying a conductive paste containing conductive particles and a thermosetting resin to a laminate by a coating method and firing the applied paste. The internal electrode layers may be fired after firing, or may be fired simultaneously with the firing of the internal electrode layers. Further, the resin layer may be a plurality of layers.

The thickness of each of the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 which are fired layers or resin layers is not particularly limited, and may be 1 μm or more and 10 μm or less.

Alternatively, the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film formation method such as a sputtering method or a vapor deposition method and deposited with metal particles.

< inner plating layer >

The 1 st undercoat layer 416 is disposed on the 1 st base electrode layer 415, and covers at least a part of the 1 st base electrode layer 415. The 2 nd undercoat layer 426 is disposed on the 2 nd base electrode layer 425, covering at least a portion of the 2 nd base electrode layer 425. The 1 st and 2 nd inner plating layers 416 and 426 include at least one selected from metals such as Cu, ni, ag, pd, and Au, and alloys such as Ag — Pd alloys.

< overcoat layer >

The 1 st outer plating layer 417 is disposed on the 1 st inner plating layer 416 and covers at least a part of the 1 st inner plating layer 416. The 2 nd outer plating layer 427 is disposed on the 2 nd inner plating layer 426, covering at least a part of the 2 nd inner plating layer 426. The 1 st overcoat layer 417 and the 2 nd overcoat layer 427 include, for example, a metal such as Sn.

< effects of inner plating layer and outer plating layer >

Preferably, the 1 st inner plating layer 416 and the 2 nd inner plating layer 426 are Ni plating layers, and the 1 st outer plating layer 417 and the 2 nd outer plating layer 427 are Sn plating layers. The Ni plating layer can prevent the base electrode layer from being corroded by the solder when the ceramic electronic component is mounted, and the Sn plating layer can improve the wettability of the solder when the ceramic electronic component is mounted, thereby facilitating the mounting.

In other words, the 1 st inner plating layer 416 and the 2 nd inner plating layer 426 have a characteristic of lower solder wettability than the 1 st outer plating layer 417 and the 2 nd outer plating layer 427.

< thickness of plating layer >

The thickness of the 1 st plating layers 416 and 417 made of the 1 st inner plating layer 416 and the 1 st outer plating layer 417 is not particularly limited, and may be 1 μm or more and 10 μm or less. The thicknesses of the 2 nd plating layers 426 and 427 composed of the 2 nd inner plating layer 426 and the 2 nd outer plating layer 427 are not particularly limited, and may be 1 μm or more and 10 μm or less.

Accordingly, the maximum value of the total length of the laminate 10 and the two external electrodes 41 and 42 in the longitudinal direction L may be 1.75mm or more and 1.85mm or less.

< recesses of external electrodes >

In the multilayer ceramic capacitor 1 of the present embodiment, the recess 50 is provided in the external electrode 40. The recess 50 is a recess provided in the external electrode 40. The recess 50 is provided by providing a recess in the base electrode layers 415 and 425, for example.

< position of recess >

The recess 50 is provided at a position corresponding to the 1 st effective portion 110 of the external electrode 40. In addition, the recess 50 is provided in each of the 1 st external electrode 41 and the 2 nd external electrode 42.

In fig. 2, the recess 50 provided at the position corresponding to the 1 st effective portion 110 in the 1 st external electrode 41 is denoted as a1 st recess 51. In addition, the recess 50 provided at a position corresponding to the 1 st effective portion 110 in the 2 nd external electrode 42 is denoted as a 2 nd recess 52.

The recess 50 may be provided in either one of the 1 st external electrode 41 and the 2 nd external electrode 42.

The recess 50 may be provided not in the external electrode 42 corresponding to the 1 st effective portion 110 but in the external electrode 42 corresponding to the 2 nd effective portion 120.

The recess 50 may be provided in both the external electrode 42 corresponding to the 1 st effective portion 110 and the external electrode 42 corresponding to the 2 nd effective portion 120.

< shape of recess >

The shape of the recess 50 is preferably a pot shape. In other words, the shape of the recess 50 is preferably a shape in which the width of the top of the recess 50 is smaller than the width of the web of the recess 50.

Here, the top is a portion of the opening of the recess. The abdomen is a portion having the largest width among portions other than the top portion of the concave portion. The width is a length of the target portion when the recess is viewed in the LT cross section. The LT cross section corresponds to a cross section at a surface including the lamination direction T and the direction in which the 1 st external electrode 41 and the 2 nd external electrode 42 face each other.

In fig. 2, the top of the 1 st concavity 51 is denoted as a top 511, and the abdomen of the 1 st concavity 51 is denoted as an abdomen 512. Similarly, the top of the 2 nd concavity 52 is denoted as a top 521, and the abdomen of the 2 nd concavity 52 is denoted as an abdomen 522.

Here, the width of the top portions 511 and 521 is the top width W1, and the width of the abdomen portions 512 and 522 is the abdomen width W2. As shown in fig. 2, in the recess 50, the top width W1 is smaller than the abdomen width W2, so that the recess 50 can be formed in a pot shape.

In addition, the ratio of the top width W1 to the abdomen width W2 is preferably 1:2 to 1:10, in the above range.

< Structure of recess >

In the recess 50 of the present embodiment, the bottom electrode layers 415 and 425 are partially omitted, so that pot-shaped cavities are formed in the bottom electrode layers 415 and 425. Further, inner plating layers 416 and 426 and outer plating layers 417 and 427 are formed on the inner wall of the hollow portion to have substantially the same thickness as the portions other than the recess 50.

Generally, the thickness of the base electrode layers 415 and 425 is greater than the thickness of the inner plating layers 416 and 426 and the thickness of the outer plating layers 417 and 427. Therefore, the shape of the recess 50 substantially matches the shape of the lack of the underlying electrode layers 415 and 425.

Further, the inner plating layers 416, 426 and the outer plating layers 417, 427 need not be provided so as to cover the entire inner wall of the recess 50, depending on the shape of the recess 50, for example.

< Effect of recesses >

In the laminated ceramic capacitor 1 of the present embodiment, the recess 50 is provided in the external electrode 40. Therefore, the ESR of the multilayer ceramic capacitor 1 can be reduced.

This is because the distance between the internal electrode layer 30 and the inner plating layers 416 and 426 and the outer plating layers 417 and 427 is shortened at the bottom portions 513 and 523 of the recess 50. Here, the bottom portions 513 and 523 of the concave portion 50 are portions facing the top portions 511 and 521 in the concave portion 50.

< pot type Effect >

In the multilayer ceramic capacitor 1 of the present embodiment, the recess 50 has a pot shape. Therefore, the surface area of the inner plating layers 416 and 426 and the outer plating layers 417 and 427 on the outermost surface 401 of the external electrode 40 can be prevented from being reduced by the formation of the recess 50. Here, the outermost surface 401 of the external electrode 40 means a surface of the external electrode 40 that does not include the inner surface of the recess 50.

In the multilayer ceramic capacitor 1 of the present embodiment, an increase in the in-plane resistance value of the outermost surface 401 of the external electrode 40 can be suppressed. Further, the distances between the plating layers 417 and 427 and the internal electrode layers 31B and 31A are shortened, and the resistance value can be kept low.

< measuring method >

Next, the measurement method will be described in order.

As a method for measuring the thickness of the dielectric layers 20 and the internal electrode layers 30, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope is cited. Each value may be an average value of measured values at a plurality of positions in the longitudinal direction, or may be an average value of measured values at a plurality of positions in the stacking direction.

Similarly, as a method for measuring the thickness of the laminate 10, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing or a WT cross section near the center in the length direction of the laminate exposed by polishing with a scanning electron microscope is cited. Each value may be an average value of measured values at a plurality of positions in the longitudinal direction or the width direction.

Similarly, as a method for measuring the length of the laminate 10, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope is cited. Each value may be an average value of measured values at a plurality of positions in the stacking direction.

Similarly, as a method for measuring the width of the laminate 10, for example, a method of observing a WT cross section near the center in the longitudinal direction of the laminate exposed by polishing with a scanning electron microscope is cited. Each value may be an average value of measured values at a plurality of positions in the stacking direction.

< production method >

Next, an example of a general method for manufacturing the laminated ceramic capacitor 1 will be described. First, dielectric sheets for the dielectric layers 20 and conductive pastes for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. As the binder and the solvent, known materials can be used.

Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode layer pattern on the dielectric sheet. As a method for forming the internal electrode layer pattern, screen printing, gravure printing, or the like can be used.

Subsequently, a predetermined number of dielectric sheets for the 2 nd outer layer section 102 on which the internal electrode layer patterns are not printed are stacked.

Dielectric sheets for the internal layer portion 100 on which internal electrode layer patterns are printed are sequentially laminated. The dielectric sheets include a dielectric sheet corresponding to the 1 st dielectric layer 21, a dielectric sheet corresponding to the effective inter-portion dielectric layer 23, and a dielectric sheet corresponding to the 2 nd dielectric layer 22.

A predetermined number of dielectric sheets for the 1 st outer layer section 101 on which internal electrode layer patterns are not printed are stacked. Thus, a laminated sheet was produced.

Next, the laminated sheet is pressed in the laminating direction by means of isostatic pressing or the like to produce a laminated block. Next, the laminated block is cut into a given size and cut into laminated small pieces. At this time, the corners and ridge portions of the stacked small pieces are rounded by barrel polishing or the like. Next, the stacked chips are fired to produce the stacked body 10. The firing temperature depends on the materials of the dielectric and internal electrode layers, but is preferably 900 ℃ to 1400 ℃.

Next, the 1 st end surface LS1 of the laminate 10 is immersed in a conductive paste as an electrode material for the underlying electrode layer by an immersion method, and the conductive paste for the 1 st underlying electrode layer 415 is applied to the 1 st end surface LS1. Similarly, the 2 nd end surface LS2 of the laminate 10 is immersed in a conductive paste as an electrode material for the underlying electrode layer by an immersion method, and the conductive paste for the 2 nd underlying electrode layer 425 is applied to the 2 nd end surface LS2. Then, by firing these conductive pastes, the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 which are fired layers are formed. The firing temperature is preferably 600 ℃ to 900 ℃.

As described above, the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 which are resin layers may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and firing the paste, or the 1 st underlying electrode layer 415 and the 2 nd underlying electrode layer 425 which are thin films may be formed by a thin film forming method such as a sputtering method or a vapor deposition method.

Next, a1 st undercoat layer 416 is formed on the surface of the 1 st base electrode layer 415, and a 2 nd undercoat layer 426 is formed on the surface of the 2 nd base electrode layer 425. Then, a1 st overplate layer 417 is formed on the surface of the 1 st overplate layer 416, and a 2 nd overplate layer 427 is formed on the surface of the 2 nd overplate layer 426.

Then, the 1 st outer plating layer 417 is removed and the 1 st inner plating layer 416 is exposed at the center portion of the 1 st outer electrode 41, thereby forming the 1 st outer electrode 41. Further, the 2 nd outer electrode 42 is formed by removing the 2 nd outer plating layer 427 and exposing the 2 nd inner plating layer 426 in the center portion of the 2 nd outer electrode 42.

Through the above steps, the multilayer ceramic capacitor 1 described above can be obtained.

< formation of concave portion >

The laminated ceramic capacitor 1 of the present embodiment is provided with the recess 50 in the external electrode 40. A method of forming the concave portion 50 will be described below.

As described above, the recess 50 can be provided by forming pot-shaped defects in the base electrode layers 415 and 425. Specifically, after the conductive paste for the 1 st underlying electrode layer 415 is applied to the 1 st end surface LS1, a defect is formed in a desired position of the applied conductive paste in an unfired state. As a method of forming the defect, for example, there is a method of removing a part of the conductive paste by bringing a fine needle or the like into contact with the conductive paste.

After the unfired conductive paste is formed into a defect in this manner, the conductive paste is fired. After firing, formation of a plating layer and the like are performed according to a general manufacturing method of a multilayer ceramic capacitor. Alternatively, the spherical member may be formed by embedding a spherical member made of a resin and burning the spherical member at the time of firing.

The defects in the underlying electrode layers 415 and 425 can also be formed after the conductive paste is fired. In this case, for example, the conductive paste after firing is finely dug to form a defect in the underlying electrode layer.

While the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various changes and modifications can be made.

Claims (5)

1. A laminated ceramic capacitor is characterized in that,

the disclosed device is provided with: a laminate in which dielectric layers containing a ceramic material and internal electrode layers are alternately laminated,

the laminate includes a1 st external electrode and a 2 nd external electrode opposed to each other,

the laminate comprises a1 st effective part and a 2 nd effective part arranged in the laminating direction,

the 1 st effective part is formed by laminating a plurality of layers of the 1 st dielectric layer and the 1 st internal electrode layer,

the 2 nd effective part is formed by laminating a plurality of layers of the 2 nd dielectric layer and the 2 nd internal electrode layer,

at least one of the 1 st external electrode and the 2 nd external electrode is provided with a recess at a position corresponding to any one of the 1 st effective part and the 2 nd effective part.

2. The laminated ceramic capacitor according to claim 1,

the distance in the stacking direction of the internal electrode layers adjacent in the stacking direction in the 1 st effective portion is different from the distance in the stacking direction of the internal electrode layers adjacent in the stacking direction in the 2 nd effective portion.

3. The laminated ceramic capacitor according to claim 1 or 2,

in a cross-sectional view of the recess in a plane including the stacking direction and a direction in which the 1 st external electrode faces the 2 nd external electrode,

the width of the top of the recess, which is the portion of the opening, is smaller than the width of the web, which is the portion of the recess other than the top and whose width is the largest.

4. The laminated ceramic capacitor according to claim 1 or 2,

the thickness of the 1 st dielectric layer and the thickness of the 2 nd dielectric layer are 1.1 μm or more and 3.0 μm or less.

5. The laminated ceramic capacitor according to claim 1 or 2,

the thickness of the 1 st internal electrode layer and the thickness of the 2 nd internal electrode layer are 0.8 μm or more and 1.2 μm or less.

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