CN216749609U - Multilayer ceramic capacitor - Google Patents

Abstract

Provided is a laminated ceramic capacitor capable of simplifying a capacitance design. A multilayer ceramic capacitor (1) is provided with a multilayer body (10) in which a plurality of dielectric layers (20) and a plurality of internal electrode layers (30) are laminated, and external electrodes (40). The number of the plurality of internal electrode layers is 5 or more. When the inner electrode layer closest to the second main surface (TS2) among the plurality of inner electrode layers is set as a main surface-side inner electrode layer (301), the remaining inner electrode layers other than the main surface-side inner electrode layer are set as an inner electrode layer assembly section (302), the interval between the main surface-side inner electrode layer and the inner electrode layer assembly section is T1, and the interval between the inner electrode layers in the inner electrode layer assembly section is T2, T1 > T2. The thickness of the laminate in the lamination direction (T) is 0.17mm to 0.19mm, and the sum of the lengths of the laminate and the external electrodes in the longitudinal direction (L) is 0.40mm to 0.44 mm.

Description

Multilayer ceramic capacitor

Technical Field

The present invention relates to a laminated ceramic capacitor.

Background

There is known a multilayer ceramic capacitor including a multilayer body in which a plurality of dielectric layers made of a ceramic material and a plurality of internal electrode layers are laminated, and external electrodes disposed on end faces of the multilayer body. (see, for example, patent documents 1 and 2).

Prior art documents

Patent document

Patent document 1: japanese patent laid-open publication No. 2019-140374

Patent document 2: japanese patent laid-open publication No. 2017-204627

SUMMERY OF THE UTILITY MODEL

Problem to be solved by utility model

In such a multilayer ceramic capacitor, further miniaturization is required, and for example, the size of 0402 (L0.4 mm, W0.2 mm, and T0.2 mm) is required. However, laminated ceramic capacitors miniaturized to such a size are often used in high-precision electronic circuits, and various capacitance values are required for fine capacitance intervals. In this way, when a small number of multilayer ceramic capacitors having various capacitance values are required at a fine capacitance interval, the capacitance design of the multilayer ceramic capacitor becomes complicated.

The utility model provides a laminated ceramic capacitor capable of simplifying capacitance design.

Means for solving the problems

A multilayer ceramic capacitor of the present invention includes: a laminate body in which a plurality of dielectric layers made of a ceramic material and a plurality of internal electrode layers are laminated, the laminate body having two main surfaces facing in a lamination direction, two side surfaces facing in a width direction intersecting the lamination direction, and two end surfaces facing in a length direction intersecting the lamination direction and the width direction; and two external electrodes disposed on the two end surfaces of the laminate, respectively. The number of the internal electrode layers is 5 or more. When the internal electrode layer closest to any one of the two main surfaces among the plurality of internal electrode layers is a main surface-side internal electrode layer, the remaining internal electrode layers other than the main surface-side internal electrode layer are internal electrode layer assembly portions, the interval between the main surface-side internal electrode layer and the internal electrode layer assembly portions is T1, and the interval between the internal electrode layers in the internal electrode layer assembly portions is T2, T1 > T2. The thickness of the laminate in the lamination direction is 0.17mm to 0.19mm, and the sum of the lengths of the laminate and the external electrode in the longitudinal direction is 0.40mm to 0.44 mm.

Effect of the utility model

According to the present invention, the capacitance design of the laminated ceramic capacitor can be simplified.

Drawings

Fig. 1 is a perspective view showing a multilayer ceramic capacitor according to the present embodiment.

Fig. 2 is a sectional view (LT section) taken along line II-II of the laminated ceramic capacitor shown in fig. 1.

Fig. 3 is a sectional view (WT section) taken along line III-III of the laminated ceramic capacitor shown in fig. 1.

Description of the reference numerals

1 a laminated ceramic capacitor;

10 a laminated body;

20 a dielectric layer;

30 internal electrode layers;

301 main surface side inner electrode layers;

302 an internal electrode layer assembly unit;

31 a first internal electrode layer;

311 a first counter electrode portion;

312 first extraction electrode section;

32 a second internal electrode layer;

321 a second counter electrode part;

322 second extraction electrode section;

40 an outer electrode;

41 a first external electrode;

415 a first base electrode layer;

416 a first plating layer;

42 a second external electrode;

425 a second base electrode layer;

426 a second plating layer;

100 inner layer portion;

101 a first outer layer section;

102 a second outer layer portion;

l30 electrode contraposition part;

LG1 first end gap portion;

LG2 second end gap portion;

w30 electrode contraposition;

a WG1 first side gap portion;

a WG2 second side slot;

l length direction;

t in the stacking direction;

the width direction of W;

LS1 first end face;

LS2 second end face;

TS1 first major face;

TS2 second major face;

WS1 first side;

WS2 second side;

t1, T2 intervals.

Detailed Description

Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals.

< multilayer ceramic capacitor >

Fig. 1 is a perspective view showing a laminated ceramic capacitor according to the present embodiment, fig. 2 is a sectional view taken along line II-II of the laminated ceramic capacitor shown in fig. 1, and fig. 3 is a sectional view taken along line III-III of the laminated ceramic capacitor shown in fig. 1. The multilayer ceramic capacitor 1 shown in fig. 1 to 3 includes a multilayer body 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

Fig. 1 to 3 show an XYZ rectangular coordinate system. The X direction is the longitudinal direction L of the multilayer ceramic capacitor 1 and the multilayer body 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10, and the Z direction is the stacking direction T of the multilayer ceramic capacitor 1 and the multilayer body 10. Thus, the cross section shown in FIG. 2 is also referred to as LT cross section, and the cross section shown in FIG. 3 is also referred to as WT cross section

The longitudinal direction L, the width direction W, and the stacking direction T are not necessarily limited to orthogonal relationships, and may be intersecting relationships.

The laminate 10 is substantially rectangular parallelepiped in shape, and has a first main surface TS1 and a second main surface TS2 opposed in the lamination direction T, a first side surface WS1 and a second side surface WS2 opposed in the width direction W, and a first end surface LS1 and a second end surface LS2 opposed in the longitudinal direction L.

The corners and the ridge portions of the laminate 10 are preferably rounded. The corner portion is a portion where three surfaces of the laminated body 10 intersect, and the ridge portion is a portion where two surfaces of the laminated body 10 intersect.

As shown in fig. 2 and 3, the stacked body 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in the stacking direction T. The laminate 10 has an inner layer 100 and a first outer layer 101 and a second outer layer 102 arranged to sandwich the inner layer 100 in the lamination direction T.

The inner layer portion 100 includes a plurality of internal electrode layers 30 and a plurality of dielectric layers 20. In the inner portion 100, the plurality of internal electrode layers 30 are arranged to face each other with the dielectric layer 20 interposed therebetween. The inner layer 100 is a portion that generates electrostatic capacitance and functions substantially as a capacitor.

The first outer layer section 101 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer section 102 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer section 101 is disposed between the first main surface TS1 and the inner electrode layer 30 closest to the first main surface TS1 among the plurality of inner electrode layers 30, and the second outer layer section 102 is disposed between the second main surface TS2 and the inner electrode layer 30 closest to the second main surface TS2 among the plurality of inner electrode layers 30. The first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30, and include portions other than the portion for the inner layer portion 100 among the plurality of dielectric layers 20. The first outer layer portion 101 and the second outer layer portion 102 are portions functioning as protective layers of the inner layer portion 100.

As the material of the dielectric layer 20, for example, a material containing BaTiO can be used₃、CaTiO₃、SrTiO₃Or CaZrO₃Dielectric ceramics containing the same as main component. As the material of the dielectric layer 20, an Mn compound, an Fe compound, a Cr compound, a Co compound, an Ni compound, or the like may be added as a subcomponent.

The thickness of the dielectric layer 20 is not particularly limited, but is preferably 15 μm or more and 22 μm or less, for example. The number of the dielectric layers 20 is not particularly limited, but is preferably 5 to 100 sheets, for example. The number of the dielectric layers 20 is the total number of the dielectric layers of the inner layer portion and the number of the dielectric layers of the outer layer portion.

The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the stacking direction T of the stacked body 10.

The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312, and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322.

The opposite electrode portion 311 and the opposite electrode portion 321 face each other with the dielectric layer 20 interposed therebetween in the lamination direction T of the laminate 10. The shapes of the counter electrode portion 311 and the counter electrode portion 321 are not particularly limited, and may be, for example, substantially rectangular. The counter electrode portion 311 and the counter electrode portion 321 are portions which generate capacitance and substantially function as capacitors.

The lead electrode portion 312 extends from the opposite electrode portion 311 toward the first end face LS1 of the laminate 10, and is exposed at the first end face LS 1. The lead electrode portions 322 extend from the opposite electrode portions 321 toward the second end face LS2 of the laminate 10, and are exposed at the second end face LS 2. The shapes of the extraction electrode portion 312 and the extraction electrode portion 322 are not particularly limited, and may be, for example, substantially rectangular.

Thereby, the first internal electrode layers 31 are connected to the first external electrodes 41, and a gap is formed between the first internal electrode layers 31 and the second external electrodes 42, which are the second end faces LS2 of the laminate 10. The second internal electrode layers 32 are connected to the second external electrodes 42, and a gap is formed between the second internal electrode layers 32 and the first external electrodes 41, which are the first end surfaces LS1 of the multilayer body 10.

The first and second internal electrode layers 31 and 32 contain metallic Ni as a main component. The first and second internal electrode layers 31 and 32 may contain at least one selected from metals such as Cu, Ag, Pd, and Au, or alloys containing at least one of these metals such as Ag — Pd alloys, as a main component, or as a component other than the main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain, as components other than the main component, particles of a dielectric having the same composition system as the ceramic contained in the dielectric layer 20. In the present specification, the metal of the main component is defined as the metal component having the highest weight%.

The thicknesses of the first internal electrode layers 31 and the second internal electrode layers 32 are not particularly limited, but are preferably 10 μm or more and 30 μm or less, for example. The number of the first internal electrode layers 31 and the second internal electrode layers 32 is not particularly limited, but is preferably 5 to 100 sheets, for example.

As shown in fig. 3, the laminate 10 includes, in the width direction W, an electrode facing portion W30 in which the internal electrode layers 30 face each other, and a first side gap portion WG1 and a second side gap portion WG2 which are arranged so as to sandwich the electrode facing portion W30. First gap WG1 is located between electrode opposing portion W30 and first side WS1, and second gap WG2 is located between electrode opposing portion W30 and second side WS 2. More specifically, the first side surface WS1 side end of the internal electrode layer 30 and the first side surface WS1 are located at the first side WG1, and the second side surface WS2 side end of the internal electrode layer 30 and the second side surface WS2 side end of the internal electrode layer 30 are located at the second side surface WG 2. The first and second side-gap portions WG1 and WG2 do not include the inner electrode layer 30, but only the dielectric layer 20. The first and second side-gap portions WG1 and WG2 are portions that function as protective layers of the internal electrode layers 30. The first and second side gap portions WG1 and WG2 are also referred to as W gaps.

As shown in fig. 2, the laminate 10 includes, in the longitudinal direction L, an electrode facing portion L30, a first gap portion LG1, and a second gap portion LG2, in which the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layers 30 face each other. The first gap LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second gap LG2 is located between the electrode facing portion L30 and the second end face LS 2. More specifically, the first gap LG1 is located between the end of the second inner electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second gap LG2 is located between the end of the first inner electrode layer 31 on the second end face LS2 side and the second end face LS 2. The first gap portion LG1 includes no second internal electrode layer 32, including the first internal electrode layer 31 and the dielectric layer 20, and the second gap portion LG2 includes no first internal electrode layer 31, including the second internal electrode layer 32 and the dielectric layer 20. The first gap LG1 functions as a lead-out electrode portion for leading out the first inner electrode layer 31 to the first end face LS1, and the second gap LG2 functions as a lead-out electrode portion for leading out the second inner electrode layer 32 to the second end face LS 2. The first and second gap portions LG1 and LG2 are also referred to as L-gaps.

The counter electrode portion 311 of the first internal electrode layer 31 and the counter electrode portion 321 of the second internal electrode layer 32 are located at the electrode facing portion L30. The lead electrode portion 312 of the first internal electrode layer 31 is located at the first end gap portion LG1, and the lead electrode portion 322 of the second internal electrode layer 32 is located at the second end gap portion LG 2.

The dimension of the laminate 10 is not particularly limited, but for example, the length in the longitudinal direction L is preferably 0.34mm or more and 0.38mm or less, the width in the width direction W is preferably 0.14mm or more and 0.18mm or less, and the thickness in the lamination direction T is preferably 0.17mm or more and 0.19mm or less. The length of the multilayer ceramic capacitor 1 including the external electrodes 40 described later in the longitudinal direction L is preferably 0.40mm to 0.44mm, for example. In this case, the width of the internal electrode layers 30 in the width direction W is preferably 50% or more and 80% or less of the width dimension of the laminate 10.

As a method for measuring the thickness of the dielectric layers 20 and the internal electrode layers 30, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope is given. Each value may be an average value of measured values at a plurality of positions in the longitudinal direction, or may be an average value of measured values at a plurality of positions in the stacking direction.

Similarly, as a method for measuring the thickness of the laminate 10, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing or a WT cross section near the center in the length direction of the laminate exposed by polishing with a scanning electron microscope is cited. Each value may be an average value of measured values at a plurality of positions in the longitudinal direction or the width direction.

Similarly, as a method for measuring the length of the laminate 10, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope is cited. Each value may be an average value of measured values at a plurality of positions in the stacking direction.

Similarly, as a method for measuring the width of the laminate 10, for example, a method of observing a WT cross section near the center in the longitudinal direction of the laminate exposed by polishing with a scanning electron microscope is cited. Each value may be an average value of measured values at a plurality of positions in the stacking direction.

The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

The first external electrodes 41 are disposed on the first end surface LS1 of the laminate 10 and connected to the first internal electrode layers 31. The first external electrode 41 may extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS 2. In addition, the first external electrode 41 may extend from the first end surface LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS 2.

The second external electrodes 42 are disposed at the second end face LS2 of the laminate 10 and connected to the second internal electrode layers 32. The second external electrode 42 may extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS 2. In addition, the second external electrode 42 may extend from the second end surface LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS 2.

The first external electrode 41 has a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 has a second base electrode layer 425 and a second plating layer 426. The first external electrode 41 may include only the first plating layer 416, and the second external electrode 42 may include only the second plating layer 426.

First base electrode layer 415 and second base electrode layer 425 may also be fired layers comprising metal and glass. The glass includes a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, and the like. As a specific example, borosilicate glass can be used. The metal contains Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, and Au, and alloys such as Ag — Pd alloys, as a main component, or as a component other than the main component.

The fired layer is a layer obtained by applying a conductive paste containing a metal and glass to the laminate by a dipping method and firing the applied conductive paste. The internal electrode layers may be fired after being fired, or may be fired simultaneously with the internal electrode layers. The fired layer may be a plurality of layers.

Alternatively, the first underlying electrode layer 415 and the second underlying electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the fired layer, or may be formed directly on the laminate without forming the fired layer.

The resin layer is a layer obtained by applying a conductive paste containing conductive particles and a thermosetting resin to a laminate by a coating method and firing the paste. The internal electrode layers may be fired after being fired, or may be fired simultaneously with the internal electrode layers. Further, the resin layer may be a plurality of layers.

The thickness of each of the first underlying electrode layer 415 and the second underlying electrode layer 425 which are the fired layer or the resin layer is not particularly limited, and may be 1 μm or more and 10 μm or less.

Alternatively, the first underlying electrode layer 415 and the second underlying electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film formation method such as a sputtering method or a vapor deposition method, and in which metal particles are deposited.

The first plating layer 416 covers at least a portion of the first base electrode layer 415, and the second plating layer 426 covers at least a portion of the second base electrode layer 425. The first plating layer 416 and the second plating layer 426 include at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag — Pd alloys, for example.

The first plating layer 416 and the second plating layer 426 may be formed of a plurality of layers. A two-layer configuration of Ni plating and Sn plating is preferable. The Ni plating layer can prevent the base electrode layer from being corroded by solder when the ceramic electronic component is mounted, and the Sn plating layer can improve the wettability of the solder when the ceramic electronic component is mounted, so that the ceramic electronic component can be easily mounted.

The thickness of each of the first plating layer 416 and the second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

Internal electrode layer

Next, the internal electrode layer 30 will be further described. As shown in fig. 3, the inner electrode layer closest to the second main surface TS2 of the plurality of inner electrode layers 30 is defined as a main surface side inner electrode layer 301, and the remaining inner electrode layers other than the main surface side inner electrode layer 301 are defined as an inner electrode layer assembly 302. The inner electrode layer closest to the first main surface TS1 of the plurality of inner electrode layers 30 may be the main surface side inner electrode layer 301, and the remaining inner electrode layers other than the main surface side inner electrode layer 301 may be the inner electrode layer assembly 302 (not shown).

Further, the distance between the main surface side inner electrode layer 301 and the inner electrode layer assembly 302 is T1, and the distance between the inner electrode layers 30 in the inner electrode layer assembly 302 is T2. Thus, in these intervals, the relationship of T1 > T2 holds. Preferably, in these intervals, the relationship of T1 > T2 × 1.5 holds.

< production method >

Next, a method for manufacturing the multilayer ceramic capacitor 1 will be described. First, dielectric sheets for the dielectric layers 20 and conductive pastes for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. As the binder and the solvent, known materials can be used.

Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. As a method of forming the internal electrode pattern, screen printing, gravure printing, or the like can be used.

Next, a predetermined number of dielectric sheets for the inner layer portion 100 on which the internal electrode pattern is printed are stacked. Thus, the basic shape of the laminate sheet for the internal electrode layer assembly 302 is prepared in advance.

Next, a predetermined number of dielectric sheets for the second outer layer portion 102 on which the internal electrode pattern is not printed are stacked.

On this, a dielectric sheet for the inner layer portion 100 on which the inner electrode pattern is printed, that is, a dielectric sheet for the main surface side inner electrode layer 301 is laminated. A dielectric sheet on which the internal electrode pattern is not printed is laminated. At this time, in order to adjust the interval T1 so that the capacitance value becomes a desired value, for example, the number of laminated dielectric sheets may be adjusted, or the thickness of one dielectric sheet may be adjusted.

The basic shape of the laminate sheet for the internal electrode layer assembly 302 is laminated thereon.

On this, a predetermined number of dielectric sheets for the first outer layer portion 101 on which the internal electrode pattern is not printed are stacked. Thus, a laminate sheet was produced.

Next, the laminated sheet is pressurized in the laminating direction by means of hydrostatic pressure or the like, to produce a laminated block. Next, the laminated block is cut into a predetermined size, and the laminated chip is cut out. At this time, the corners and the ridge portions of the laminated chips are rounded by barrel polishing or the like. Subsequently, the laminated chip is fired to produce a laminated body 10. The firing temperature is also determined based on the materials of the dielectric and the internal electrode, but is preferably 900 ℃ to 1400 ℃.

Next, the first end surface LS1 of the laminate 10 was immersed in a conductive paste as an electrode material for the underlying electrode layer by an immersion method, and thereby the conductive paste for the first underlying electrode layer 415 was applied to the first end surface LS 1. Similarly, the second end face LS2 of the laminate 10 was immersed in a conductive paste as an electrode material for the underlying electrode layer by an immersion method, and thereby the conductive paste for the second underlying electrode layer 425 was applied to the second end face LS 2. Then, these conductive pastes are fired to form a first underlying electrode layer 415 and a second underlying electrode layer 425 as fired layers. The firing temperature is preferably 600 ℃ or higher and 900 ℃ or lower.

As described above, the first underlying electrode layer 415 and the second underlying electrode layer 425 which are resin layers may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and firing the paste, or the first underlying electrode layer 415 and the second underlying electrode layer 425 which are thin films may be formed by a thin film forming method such as a sputtering method or a vapor deposition method.

Then, a first plating layer 416 is formed on the surface of the first base electrode layer 415 to form a first external electrode 41, and a second plating layer 426 is formed on the surface of the second base electrode layer 425 to form a second external electrode 42. Through the above steps, the multilayer ceramic capacitor 1 described above is obtained.

As described above, according to the multilayer ceramic capacitor 1 of the present embodiment, it is possible to reduce the size of the ceramic capacitor to an 0402 size (L is 0.4mm, W is 0.2mm, and T is 0.2mm), for example. However, laminated ceramic capacitors miniaturized to such a size are often used in high-precision electronic circuits, and various capacitance values are required for fine capacitance intervals. In this way, when a small number of laminated ceramic capacitors having various capacitance values are required at a fine capacitance interval, the capacitance design of the laminated ceramic capacitor becomes complicated.

In this regard, according to the multilayer ceramic capacitor 1 of the present embodiment, the relationship of T1 > T2 is established in the interval T1 between the main surface side inner electrode layer 301 and the inner electrode layer assembly 302 and the interval T2 between the inner electrode layers 30 of the inner electrode layer assembly 302. By adjusting the distance T1 between the main surface side internal electrode layers 301 and the internal electrode layer assembly 302 in this way, the capacitance value can be easily adjusted, and multilayer ceramic capacitors of various capacitance values can be obtained at fine capacitance intervals. Therefore, the capacitance design of the laminated ceramic capacitor 1 can be simplified.

While the embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations can be made.

Claims (3)

1. A laminated ceramic capacitor is characterized in that,

the multilayer ceramic capacitor includes:

a laminate body in which a plurality of dielectric layers made of a ceramic material and a plurality of internal electrode layers are laminated, the laminate body having two main surfaces facing in a lamination direction, two side surfaces facing in a width direction intersecting the lamination direction, and two end surfaces facing in a length direction intersecting the lamination direction and the width direction; and

two external electrodes disposed on the two end surfaces of the laminate, respectively,

the number of the internal electrode layers is 5 or more,

t1 > T2 when the inner electrode layer closest to any one of the two main surfaces among the plurality of inner electrode layers is a main surface-side inner electrode layer, the remaining inner electrode layers other than the main surface-side inner electrode layer are inner electrode layer assembly portions, the interval between the main surface-side inner electrode layer and the inner electrode layer assembly portion is T1, and the interval between the inner electrode layers in the inner electrode layer assembly portions is T2,

the thickness of the laminate in the laminating direction is 0.17mm to 0.19mm,

the sum of the lengths of the laminate and the external electrode in the longitudinal direction is 0.40mm to 0.44 mm.

2. The laminated ceramic capacitor according to claim 1,

T1＞T2×1.5。

3. the laminated ceramic capacitor according to claim 1 or 2,

the dielectric layer has a thickness in the stacking direction of 15 to 22 [ mu ] m.

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