CN216773068U - Multilayer ceramic capacitor - Google Patents

Abstract

A multilayer capacitor having a high bending ability is provided. The disclosed device is provided with: a laminate body in which a plurality of dielectric layers and a plurality of internal electrode layers made of a ceramic material are alternately laminated, and which has a first main surface and a second main surface that face each other in a lamination direction, a first side surface and a second side surface that face each other in a width direction that intersects with the lamination direction, and a first end surface and a second end surface that face each other in a longitudinal direction that intersects with the lamination direction and the width direction; and two external electrodes disposed on both end faces of the laminate, respectively, wherein a thickness T1 of a first outer layer portion, which is a region sandwiched between the first main face and the internal electrode disposed closest to the first main face in the lamination direction, and a thickness T2 of a second outer layer portion, which is a region sandwiched between the second main face and the internal electrode disposed closest to the second main face in the lamination direction, satisfy the following expressions: t1 > T2, the thickness of the laminate is 170 to 190 μm, and the length of the laminate is 400 to 440 μm.

Description

Multilayer ceramic capacitor

Technical Field

The present invention relates to a laminated ceramic capacitor.

Background

In recent years, a multilayer ceramic capacitor is required to have a smaller size and a larger capacitance.

In such a small and large-capacity laminated ceramic capacitor, when a mechanical force is applied to the external electrode portion thereof, a crack is generated in the dielectric under the external electrode portion, and a short circuit may occur between adjacent internal electrodes.

In order to solve such a problem, patent document 1 proposes a laminated ceramic capacitor,

the multilayer ceramic capacitor has a plurality of first internal electrodes and a plurality of second internal electrodes connected to the first external electrodes and the second external electrodes, respectively,

the sum of the length of the first internal electrode in the direction toward the second external electrode and the length of the second lower-surface external electrode in the direction toward the first external electrode is shorter than the distance between the first external electrode and the second external electrode,

the sum of the length of the second internal electrode in the direction toward the first external electrode and the length of the first lower-surface external electrode in the direction toward the second external electrode is shorter than the distance between the first external electrode and the second external electrode.

Prior art documents

Patent document

Patent document 1: japanese laid-open patent publication No. 6-163311

SUMMERY OF THE UTILITY MODEL

Problem to be solved by utility model

However, there is a demand for providing a laminated ceramic capacitor having a high bending ability even when cracks are generated.

The present invention aims to provide such a multilayer ceramic capacitor.

Means for solving the problems

In order to solve the above problems, the present inventors have provided a laminated ceramic capacitor,

the multilayer ceramic capacitor includes:

a laminate body in which a plurality of dielectric layers made of a ceramic material and a plurality of internal electrode layers are alternately laminated, the laminate body having a first main surface and a second main surface that face each other in a lamination direction of the laminate body, a first side surface and a second side surface that face each other in a width direction that intersects the lamination direction, and a first end surface and a second end surface that face each other in a longitudinal direction that intersects the lamination direction and the width direction; and

two external electrodes disposed on the two end surfaces of the laminate, respectively,

the thickness T1 of the first outer layer portion and the thickness T2 of the second outer layer portion satisfy the following equation: t1 > T2, the first outer layer portion being a region sandwiched between the first main surface and the inner electrode disposed closest to the first main surface in the stacking direction, the second outer layer portion being a region sandwiched between the second main surface and the inner electrode disposed closest to the second main surface in the stacking direction,

the thickness of the laminate is 170 [ mu ] m or more and 190 [ mu ] m or less,

the overall length is 400 μm or more and 440 μm or less.

Effect of the utility model

According to the present invention, a laminated ceramic capacitor having a high bending ability even when cracks are generated can be provided.

Drawings

Fig. 1 is a perspective view showing a multilayer ceramic capacitor according to the present embodiment.

Fig. 2 is a sectional view (LT section) taken along line II-II of the laminated ceramic capacitor shown in fig. 1.

Fig. 3 is a sectional view (WT section) taken along line III-III of the laminated ceramic capacitor shown in fig. 1.

Description of the reference numerals

1 a laminated ceramic capacitor;

10 a laminated body;

20 a dielectric layer;

30 internal electrode layers;

31 a first internal electrode layer;

311 a first counter electrode portion;

312 first extraction electrode section;

32 a second internal electrode layer;

321 a second counter electrode part;

322 a second extraction electrode section;

40 an outer electrode;

41 a first external electrode;

415 a first base electrode layer;

416 a first inner plating layer;

417 a first topcoat layer;

42 a second external electrode;

425 a second base electrode layer;

426 a second inner plating layer;

427 a second surface plating layer;

100 inner layer portion (effective area);

101 a first outer layer section;

102 a second outer layer portion;

l30 electrode contraposition part;

LG1 first end gap portion;

LG2 second end gap portion;

w30 electrode contraposition;

a WG1 first side gap portion;

a WG2 second side slot;

l length direction;

t in the stacking direction;

the width direction of W;

LS1 first end face;

LS2 second end face;

TS1 first major face;

TS2 second major face;

WS1 first side;

WS2 second side.

Detailed Description

Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals.

< multilayer ceramic capacitor >

Fig. 1 is a perspective view showing a laminated ceramic capacitor according to the present embodiment, fig. 2 is a sectional view taken along line II-II of the laminated ceramic capacitor shown in fig. 1, and fig. 3 is a sectional view taken along line III-III of the laminated ceramic capacitor shown in fig. 1.

The multilayer ceramic capacitor 1 shown in fig. 1 to 3 includes a multilayer body 10 and external electrodes 40. The external electrode 40 includes a first external electrode 41 and a second external electrode 42.

Fig. 1 to 3 show an XYZ rectangular coordinate system.

The X direction is the longitudinal direction L of the multilayer ceramic capacitor 1 and the multilayer body 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10, and the Z direction is the stacking direction T of the multilayer ceramic capacitor 1 and the multilayer body 10.

Based on this, the profile shown in fig. 2 is also referred to as LT profile, and the profile shown in fig. 3 is also referred to as WT profile.

The longitudinal direction L, the width direction W, and the stacking direction T are not necessarily limited to orthogonal relationships, and may be intersecting relationships.

The laminate 10 is substantially rectangular parallelepiped in shape, and has a first main surface TS1 and a second main surface TS2 opposed in the lamination direction T, a first side surface WS1 and a second side surface WS2 opposed in the width direction W, and a first end surface LS1 and a second end surface LS2 opposed in the longitudinal direction L.

The corners and the ridge portions of the laminate 10 are preferably rounded. The corner portion is a portion where three surfaces of the laminate 10 intersect, and the ridge portion is a portion where two surfaces of the laminate 10 intersect.

As shown in fig. 2 and 3, the stacked body 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 stacked in the stacking direction T. The laminate 10 has an inner layer 100 and a first outer layer 101 and a second outer layer 102 arranged to sandwich the inner layer 100 in the lamination direction T.

The inner layer portion 100 includes a plurality of internal electrode layers 30 and a plurality of dielectric layers 20. In the inner portion 100, the plurality of internal electrode layers 30 are arranged to face each other with the dielectric layer 20 interposed therebetween. The inner layer 100 is a portion that generates electrostatic capacitance and functions substantially as a capacitor. Thus, the inner layer portion 100 is also referred to as an effective region.

The first outer layer section 101 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer section 102 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer section 101 is disposed between the first main surface TS1 and the inner electrode layer 30 closest to the first main surface TS1 among the plurality of inner electrode layers 30, and the second outer layer section 102 is disposed between the second main surface TS2 and the inner electrode layer 30 closest to the second main surface TS2 among the plurality of inner electrode layers 30. The first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30, and include portions other than the portion for the inner layer portion 100 among the plurality of dielectric layers 20. The first outer layer portion 101 and the second outer layer portion 102 are portions functioning as protective layers of the inner layer portion 100.

As the material of the dielectric layer 20, for example, BaTiO-containing material can be used₃、CaTiO₃、SrTiO₃Or CaZrO₃And the like as a main component. In addition to the main component, an Mn compound, an Fe compound, a Cr compound, a Co compound, an Ni compound, or the like may be added as a sub-component.

The thickness of the dielectric layer 20 is not particularly limited, but is preferably 1, 1 μm or more and 3.0 μm or less, for example. The number of the dielectric layers 20 is not particularly limited, but is, for example, preferably 5 to 25 sheets, and more preferably 5 to 20 sheets.

The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the stacking direction T of the stacked body 10.

The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312, and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322.

The opposite electrode portion 311 and the opposite electrode portion 321 face each other with the dielectric layer 20 interposed therebetween in the lamination direction T of the laminate 10. The shapes of the counter electrode portion 311 and the counter electrode portion 321 are not particularly limited, and may be, for example, substantially rectangular. The counter electrode portion 311 and the counter electrode portion 321 are portions which generate capacitance and substantially function as capacitors.

The lead electrode portion 312 extends from the opposite electrode portion 311 toward the first end face LS1 of the laminate 10, and is exposed at the first end face LS 1. The lead electrode portions 322 extend from the opposite electrode portions 321 toward the second end face LS2 of the laminate 10, and are exposed at the second end face LS 2. The shapes of the extraction electrode portion 312 and the extraction electrode portion 322 are not particularly limited, and may be, for example, substantially rectangular.

Thereby, the first internal electrode layers 31 are connected to the first external electrodes 41, and a gap is formed between the first internal electrode layers 31 and the second external electrodes 42, which are the second end faces LS2 of the laminate 10. The second internal electrode layers 32 are connected to the second external electrodes 42, and a gap is formed between the second internal electrode layers 32 and the first external electrode 41, which is the first end surface LS1 of the multilayer body 10.

The laminated ceramic capacitor is preferably: in the gap, a first inner electrode not connected to a second end surface is provided on the first end surface, a second inner electrode not connected to the first end surface is provided on the second end surface, and the length L1 in the longitudinal direction of the first inner electrode is desirably longer than the length L2 in the longitudinal direction of the second inner electrode.

The first internal electrode layers 31 and the second internal electrode layers 32 contain, for example, metal Ni as a main component. The first and second internal electrode layers 31 and 32 may contain at least one selected from metals such as Cu, Ag, Pd, and Au, or alloys containing at least one of these metals such as Ag — Pd alloys, as a main component, or as a component other than the main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain, as components other than the main component, particles of a dielectric having the same composition system as the ceramic contained in the dielectric layer 20. In the present specification, the metal of the main component is defined as the metal component having the highest mass%.

The thicknesses of the first internal electrode layer 31 and the second internal electrode layer 32 are not particularly limited, but are preferably 0.8 μm or more and 1.21 μm or less, for example. The number of the first internal electrode layers 31 and the second internal electrode layers 32 is not particularly limited, but is preferably the same as the number of the dielectric layers 20, for example, 5 to 25 sheets, and more preferably 5 to 20 sheets.

As shown in fig. 3, the laminate 10 includes, in the width direction W, an electrode facing portion W30 where the internal electrode layers 30 face each other, and a first side gap portion WG1 and a second side gap portion WG2 which are arranged so as to sandwich the electrode facing portion W30. First gap WG1 is located between electrode opposing portion W30 and first side WS1, and second gap WG2 is located between electrode opposing portion W30 and second side WS 2. More specifically, the first side surface WS1 side end of the internal electrode layer 30 and the first side surface WS1 are located at the first side WG1, and the second side surface WS2 side end of the internal electrode layer 30 and the second side surface WS2 side end of the internal electrode layer 30 are located at the second side surface WG 2. The first and second side-gap portions WG1 and WG2 do not include the inner electrode layer 30, but only the dielectric layer 20. The first and second side gap portions WG1 and WG2 function as protective layers for the internal electrode layer 30. The first and second side gap portions WG1 and WG2 are also referred to as W gaps.

As shown in fig. 2, the laminate 10 includes, in the longitudinal direction L, an electrode facing portion L30, a first gap portion LG1, and a second gap portion LG2, in which the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layers 30 face each other. The first gap LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second gap LG2 is located between the electrode facing portion L30 and the second end face LS 2. More specifically, the first gap LG1 is located between the end portion on the first end face LS1 side of the second inner electrode layer 32 and the first end face LS1, and the second gap LG2 is located between the end portion on the second end face LS2 side of the first inner electrode layer 31 and the second end face LS 2. The first gap portion LG1 includes no second internal electrode layer 32, including the first internal electrode layer 31 and the dielectric layer 20, and the second gap portion LG2 includes no first internal electrode layer 31, including the second internal electrode layer 32 and the dielectric layer 20. The first gap LG1 functions as a lead-out electrode portion for leading out the first inner electrode layer 31 to the first end face LS1, and the second gap LG2 functions as a lead-out electrode portion for leading out the second inner electrode layer 32 to the second end face LS 2. The first and second gap portions LG1 and LG2 are also referred to as L-gaps.

The laminated ceramic capacitor of the present invention can have, as required, non-opposing internal electrodes 33 and 34 in addition to the internal electrodes, the non-opposing internal electrodes 33 and 34 being electrodes connected to external electrodes opposing the external electrodes to which the internal electrodes are connected at the same positions as the internal electrodes in the laminating direction. The non-opposing internal electrodes 33 and 34, which are not opposed to each other, that is, which do not constitute the electrode opposing portions, exist in the endgaps, respectively.

The counter electrode portion 311 of the first internal electrode layer 31 and the counter electrode portion 321 of the second internal electrode layer 32 are located at the electrode facing portion L30. The lead electrode portion 312 of the first internal electrode layer 31 is located at the first end gap portion LG1, and the lead electrode portion 322 of the second internal electrode layer 32 is located at the second end gap portion LG 2.

A thickness T1 of the first outer layer section, which is a region sandwiched between the first main surface and the inner electrode disposed closest to the first main surface in the stacking direction T, and a thickness T2 of the second outer layer section, which is a region sandwiched between the second main surface and the inner electrode disposed closest to the second main surface in the stacking direction T, satisfy the following expressions: t1 > T2, and the thickness of the laminate (here, the thickness excluding the external electrodes) is 170 μm or more and 190 μm or less.

As a method for measuring the thicknesses of the dielectric layers 20 and the internal electrode layers 30, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope is given. Each value may be an average value of measurement values at a plurality of positions in the longitudinal direction, or may be an average value of measurement values at a plurality of positions in the stacking direction T.

Similarly, as a method for measuring the thickness of the laminate 10, there is a method in which an LT cross section near the center in the width direction of the laminate exposed by polishing or a WT cross section near the center in the length direction of the laminate exposed by polishing is observed with a scanning electron microscope, for example. Each value may be an average value of measured values at a plurality of positions in the longitudinal direction or the width direction.

Similarly, as a method for measuring the length of the laminate 10, for example, a method of observing an LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope is cited. Each value may be an average value of measured values at a plurality of positions in the stacking direction T.

Similarly, as a method for measuring the width of the laminate 10, for example, a method of observing a WT cross section near the center in the longitudinal direction of the laminate exposed by polishing with a scanning electron microscope is cited. Each value may be an average value of measured values at a plurality of positions in the stacking direction T.

The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

The first external electrodes 41 are disposed on the first end surface LS1 of the laminate 10 and connected to the first internal electrode layers 31. The first external electrode 41 may extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS 2. In addition, the first external electrode 41 may extend from the first end surface LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS 2.

The second external electrodes 42 are disposed at the second end face LS2 of the laminate 10 and connected to the second internal electrode layers 32. The second external electrode 42 may extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS 2. In addition, the second external electrode 42 may extend from the second end surface LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS 2.

The first external electrode 41 has a first base electrode layer 415, a first inner plating layer 416, and a first surface plating layer 417, and the second external electrode 42 has a second base electrode layer 425, a second inner plating layer 426, and a second surface plating layer 427.

The first base electrode layer 415 is disposed on the first end surface LS1 of the stack 10 and covers the first end surface LS1 of the stack 10. The first underlying electrode layer 415 may extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS 2.

The second base electrode layer 425 is disposed on the second end face LS2 of the stacked body 10 and covers the second end face LS2 of the stacked body 10. The second underlying electrode layer 425 may extend from the second end surface LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS 2.

The first base electrode layer 415 and the second base electrode layer 425 may also be fired layers containing metal and glass. The glass includes a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, and the like. As a specific example, borosilicate glass can be used. The metal contains Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, and Au, and alloys such as Ag — Pd alloys, as a main component, or as a component other than the main component.

The fired layer is a layer obtained by applying a conductive paste containing a metal and glass to the laminate by a dipping method and firing the applied conductive paste. The internal electrode layers may be fired after being fired, or may be fired simultaneously with the internal electrode layers. The fired layer may be a plurality of layers.

Alternatively, the first underlying electrode layer 415 and the second underlying electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the fired layer, or may be formed directly on the laminate without forming the fired layer.

The resin layer is a layer obtained by applying a conductive paste containing conductive particles and a thermosetting resin to a laminate by a coating method and firing the paste. The internal electrode layers may be fired after being fired, or may be fired simultaneously with the internal electrode layers. Further, the resin layer may be a plurality of layers.

The thickness of each of first underlying electrode layer 415 and second underlying electrode layer 425 which are fired layers or resin layers is not particularly limited, and may be 1 μm or more and 10 μm or less.

Alternatively, the first underlying electrode layer 415 and the second underlying electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film formation method such as a sputtering method or a vapor deposition method, and in which metal particles are deposited.

The first undercoat layer 416 is disposed on the first base electrode layer 415, and covers at least a part of the first base electrode layer 415. The second undercoat layer 426 is disposed on the second base electrode layer 425 and covers at least a portion of the second base electrode layer 425. The first and second inner plating layers 416 and 426 include at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag — Pd alloys, for example.

The first surface plating layer 417 is disposed on the first inner plating layer 416 and covers at least a part of the first inner plating layer 416. The second surface plating layer 427 is disposed on the second inner plating layer 426 and covers at least a part of the second inner plating layer 426. The first surface plating layer 417 and the second surface plating layer 427 include, for example, a metal such as Sn.

Preferably, the first inner plating layer 416 and the second inner plating layer 426 are Ni plating layers, and the first top plating layer 417 and the second top plating layer 427 are Sn plating layers. The Ni plating layer can prevent solder corrosion when the base electrode layer is mounted on the multilayer ceramic capacitor 1, and the Sn plating layer can improve the wettability of the solder when the multilayer ceramic capacitor 1 is mounted, and can be easily mounted. In other words, the first inner plating layer 416 and the second inner plating layer 426 have a characteristic of low solder wettability compared to the first surface plating layer 417 and the second surface plating layer 427.

Preferably, the external electrode is a combination of a sintered electrode of Cu, a Ni plating layer, and a Su plating layer.

The thicknesses of the first plating layers 416 and 417 including the first inner plating layer 416 and the first top plating layer 417 are not particularly limited, and may be 1 μm or more and 10 μm or less. The thicknesses of the second plating layers 426 and 427 including the second inner plating layer 426 and the second surface plating layer 427 are not particularly limited, and may be 1 μm or more and 10 μm or less.

The length of the entire multilayer ceramic capacitor 1 in the longitudinal direction L is 400 μm or more and 440 μm or less. That is, in the present invention, the "overall length" is a length including the two external electrodes (the first external electrode 41 and the second external electrode 42) and the laminated body 10.

< production method >

Next, an example of the method for manufacturing the multilayer ceramic capacitor 1 will be described. First, dielectric sheets for the dielectric layers 20 and conductive pastes for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. As the binder and the solvent, known materials can be used.

Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. As a method of forming the internal electrode pattern, screen printing, gravure printing, or the like can be used.

Next, a predetermined number of dielectric sheets for the second outer layer portion 102 on which the internal electrode pattern is not printed are stacked. Dielectric sheets for the inner layer portion 100 on which the inner electrode patterns are printed are sequentially laminated. A predetermined number of dielectric sheets for the first outer layer portion 101 on which the internal electrode pattern is not printed are stacked. The number of dielectric sheets for the first outer layer portion 101 is set to be larger than the number of dielectric sheets for the second outer layer portion 102. Therefore, the first outer layer portion 101 is thicker than the second outer layer portion 102, and satisfies the relationship of T1 > T2. Thus, a laminated sheet was produced. The number of dielectric sheets for the first outer layer portion 101 may be the same as the number of dielectric sheets for the second outer layer portion 102, and the thickness of the dielectric sheets for the first outer layer portion 101 may be set to be larger than the thickness of the dielectric sheets for the second outer layer portion 102, so that the first outer layer portion 101 is thicker than the second outer layer portion 102.

Next, the laminated sheet is pressurized in the laminating direction by means of hydrostatic pressure or the like, to produce a laminated block. Next, the laminated block is cut into a predetermined size, and the laminated chip is cut out. At this time, the corners and the ridge portions of the laminated chips are rounded by barrel polishing or the like. Subsequently, the laminated chip is fired to produce a laminated body 10. The firing temperature is also determined based on the materials of the dielectric and the internal electrode, but is preferably 900 ℃ to 1400 ℃.

Next, the first end surface LS1 of the laminate 10 was immersed in a conductive paste as an electrode material for the underlying electrode layer by an immersion method, and thereby the conductive paste for the first underlying electrode layer 415 was applied to the first end surface LS 1. Similarly, the second end face LS2 of the laminate 10 was immersed in a conductive paste as an electrode material for the underlying electrode layer by an immersion method, and thereby the conductive paste for the second underlying electrode layer 425 was applied to the second end face LS 2. Then, these conductive pastes are fired to form a first underlying electrode layer 415 and a second underlying electrode layer 425 as fired layers. The firing temperature is preferably 600 ℃ or higher and 900 ℃ or lower.

As described above, the first underlying electrode layer 415 and the second underlying electrode layer 425 which are resin layers may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and firing the paste, or the first underlying electrode layer 415 and the second underlying electrode layer 425 which are thin films may be formed by a thin film forming method such as a sputtering method or a vapor deposition method.

Then, a first undercoat layer 416 is formed on the surface of the first base electrode layer 415, and a second undercoat layer 426 is formed on the surface of the second base electrode layer 425. Thereafter, a first surface plating layer 417 is formed on the surface of the first inner plating layer 416, and a second surface plating layer 427 is formed on the surface of the second inner plating layer 426.

Thereafter, the first topcoat layer 417 is removed from the central portion of the first external electrode 41, and the first inner plating layer 416 is exposed, thereby forming the first external electrode 41. The second topcoat layer 427 is removed from the center of the second external electrode 42, and the second inner plating layer 426 is exposed, thereby forming the second external electrode 42.

Through the above steps, the multilayer ceramic capacitor 1 described above is obtained.

In the case of a conventional laminated ceramic capacitor, the bending ability may be weakened when cracks occur, but the laminated ceramic capacitor of the present invention has a relatively high bending ability even when cracks occur because the first outer layer portion is thick. In addition, since the thickness of the second outer layer portion is small, the capacitance is large.

While the embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations can be made.

Claims (5)

1. A laminated ceramic capacitor is characterized in that,

the multilayer ceramic capacitor includes:

a laminate body in which a plurality of dielectric layers made of a ceramic material and a plurality of internal electrode layers are alternately laminated, the laminate body having a first main surface and a second main surface that face each other in a lamination direction of the laminate body, a first side surface and a second side surface that face each other in a width direction intersecting the lamination direction, and a first end surface and a second end surface that face each other in a longitudinal direction intersecting the lamination direction and the width direction; and

two external electrodes disposed on the first end face and the second end face of the laminate, respectively,

the thickness T1 of the first outer layer portion and the thickness T2 of the second outer layer portion satisfy the following equation: t1 > T2, the first outer layer portion being a region sandwiched between the first main surface and the inner electrode disposed closest to the first main surface in the stacking direction, the second outer layer portion being a region sandwiched between the second main surface and the inner electrode disposed closest to the second main surface in the stacking direction,

the thickness of the laminate is 170 [ mu ] m or more and 190 [ mu ] m or less,

the overall length is 400 μm or more and 440 μm or less.

2. The laminated ceramic capacitor according to claim 1,

the thickness T1 is 10% or more and less than 30% of the thickness of the laminate.

3. The laminated ceramic capacitor according to claim 1,

the laminated ceramic capacitor has, in addition to the internal electrodes, non-opposing internal electrodes connected to external electrodes opposing external electrodes to which the internal electrodes are connected, at the same positions in the lamination direction as the internal electrodes.

4. The laminated ceramic capacitor according to any one of claims 1 to 3,

the thickness of the dielectric layer is 15 [ mu ] m or more and 22 [ mu ] m or less.

5. The laminated ceramic capacitor according to claim 4,

the number of the dielectric layers is 5 to 20.

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