CN216354179U - Semiconductor with double-sided bonding pad - Google Patents

Semiconductor with double-sided bonding pad Download PDF

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Publication number
CN216354179U
CN216354179U CN202122646948.2U CN202122646948U CN216354179U CN 216354179 U CN216354179 U CN 216354179U CN 202122646948 U CN202122646948 U CN 202122646948U CN 216354179 U CN216354179 U CN 216354179U
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China
Prior art keywords
pad
pads
semiconductor
lead frame
package body
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Active
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CN202122646948.2U
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Chinese (zh)
Inventor
周刚
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Great Team Backend Foundry Dongguan Co Ltd
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Great Team Backend Foundry Dongguan Co Ltd
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Priority to CN202122646948.2U priority Critical patent/CN216354179U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model relates to a semiconductor with double-sided bonding pads, which comprises a chip, a packaging body and a lead frame, wherein the chip is arranged on the lead frame and is electrically connected with a plurality of bottom bonding pads on the lead frame, a plurality of top bonding pads are arranged on one side, away from the bottom bonding pads, of the packaging body, and the top bonding pads are in one-to-one correspondence with the bottom bonding pads and are electrically connected with the bottom bonding pads. It can solve among the prior art when the product became invalid, need to lift off the back with the semiconductor of welding on the circuit board from the circuit board and can inspect, and the dismantlement process needs waste time and energy, and has the problem with the risk of product destruction.

Description

Semiconductor with double-sided bonding pad
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a semiconductor with double-sided pads.
Background
The semiconductor is a material with a conductive capability between a conductor and a non-conductor, and the semiconductor element belongs to a solid element according to the characteristics of the semiconductor material, and the volume of the semiconductor element can be reduced to a small size, so that the power consumption is low, the integration level is high, and the semiconductor element is widely introduced in the technical field of electronics.
Generally, a semiconductor is required to be integrally soldered on a circuit board for use, and for this reason, pads for heat conduction and telecommunication conduction are generally required to be arranged on the semiconductor. Therefore, the conventional semiconductor has the following defects: when the product is invalid, the semiconductor welded on the circuit board needs to be dismounted from the circuit board and then can be checked, a certain time needs to be consumed in the dismounting process, and the risk of damaging the product exists.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model aims to: the utility model provides a semiconductor with two-sided pad, it can solve among the prior art when the product became invalid, need to lift off the back with the semiconductor of welding on the circuit board from the circuit board and can inspect, and the dismantlement process needs waste time and energy, and has the problem with the risk of product destruction.
In order to achieve the purpose, the following technical scheme is adopted in the application:
the utility model provides a semiconductor with two-sided pad, includes chip, packaging body and lead frame, the chip sets up on the lead frame and with a plurality of bottom pad electricity on the lead frame are connected, the packaging body is kept away from one side of bottom pad is provided with a plurality of top pads, the top pad with bottom pad one-to-one and electric connection.
Optionally, at least one of the top pads is formed by extending the lead frame, and the lead frame is bent towards the direction of the package body far away from the bottom pad and extends to the top of the package body to form the top pad.
Optionally, the chip further comprises a copper clip electrically connected to the bottom pad and the chip, and at least one of the top pads is formed by a portion of the copper clip facing away from the bottom pad.
Optionally, the top pads include a first pad and a second pad, and the first pad is formed by bending the lead frame towards a direction of the package body away from the bottom pad and extending to the top of the package body; the second pad is formed by a portion of the copper clip facing away from the bottom pad.
Optionally, all the top pads are formed by bending the lead frame towards the direction of the package body far away from the bottom pads and extending to the top of the package body.
Optionally, at least one pair of the top pads and the bottom pads are connected by VIA holes penetrating through the package body.
Optionally, all the top pads and the bottom pads are connected by VIA holes penetrating through the package body.
Optionally, the top pads include a first pad and a second pad, and the first pad is formed by bending the lead frame towards a direction of the package body away from the bottom pad and extending to the top of the package body; the second bonding pads and the bottom bonding pads are connected through VIA holes penetrating through the packaging body.
Optionally, the top pads corresponding to the VIA holes are integrally formed with the VIA holes by electroplating.
Optionally, the bottom pad includes a substrate pad and at least one pin pad, the first pad corresponds to the substrate pad, and the second pad corresponds to the pin pad.
The beneficial effect of this application does: the utility model provides a semiconductor with double-sided bonding pads, wherein the bottom and the top of a packaging body are respectively provided with a top bonding pad and a bottom bonding pad which correspond to each other one by one, and the top bonding pads and the bottom bonding pads which correspond to the top bonding pads are respectively electrically connected, so that the semiconductor can be welded on a circuit board by utilizing the bottom bonding pads and can be conducted with the circuit board. When breaking down, can directly utilize the top pad at semiconductor top to inspect, need not to pull down the semiconductor from the circuit board, labour saving and time saving has avoided the risk of destroying the product again. In addition, because the top of the semiconductor is provided with the top bonding pad, other components can be directly connected in series on the top of the semiconductor to carry out lamination packaging, and the beneficial effect of saving space can be achieved.
Drawings
The present application will be described in further detail below with reference to the accompanying drawings and examples.
FIG. 1 is a schematic diagram of a prior art semiconductor structure;
FIG. 2 is a schematic diagram of a semiconductor structure with double-sided bonding pads according to the present invention;
FIG. 3 is a schematic diagram of a semiconductor device having double-sided pads according to another embodiment of the present invention;
fig. 4 is a schematic structural diagram of a semiconductor device having double-sided pads according to still another embodiment of the present invention.
In fig. 1:
1', a lead frame; 11', a substrate pad; 12', a pin pad; 2', a chip; 21' and a bonding material; 22', a metal wire; 3', and packaging body.
In fig. 2:
1. a lead frame; 11. a substrate pad; 12. a pin pad; 2. a chip; 22. a metal wire; 3. a package body; 41. a first pad; 42. a second pad; 5. a copper clip; 6. and (5) VIA holes.
Detailed Description
In order to make the technical problems solved, technical solutions adopted, and technical effects achieved by the present application clearer, the following describes technical solutions of embodiments of the present application in further detail, and it is obvious that the described embodiments are only a part of embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, unless otherwise expressly specified or limited, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
Referring to fig. 1, the conventional semiconductor generally comprises a lead frame 1 ', a chip 2', a metal wire 22 'and a package body 3', wherein the lead frame 1 'comprises a substrate pad 11' for supporting the chip and a pin pad 12 'for conducting the chip 2' to an external device, and the production process generally comprises: the chip 2 ' is fixed on the substrate bonding pad 11 ' through a bonding material 21 ' (generally, conductive and heat-conductive adhesive), contacts on the chip 2 ' are bonded with the lead bonding pads 12 ' through metal wires 22 ', and the chip 2 ' and the metal wires 22 ' are wrapped by the package body 3 ' through a plastic sealing means, so that the internal structure of the semiconductor is sealed and protected.
When the semiconductor lead frame is applied, the semiconductor lead frame 1 'is used as a pad to be soldered on a circuit board, and the chip 2' is fixed on the substrate pad 11 ', so that heat generated in the working process of the chip 2' can be conducted to the circuit board through the substrate 11 'to dissipate heat, and the chip 2' can be electrically conducted with the circuit board through the metal wire 22 'and the pin pad 12'.
The existing semiconductor products are all provided with a bonding pad (single-sided lead frame) on a single side, when the products fail, a semiconductor welded on a circuit board needs to be dismounted from the circuit board and then can be checked, a certain time needs to be consumed in the dismounting process, and the risk of damaging the products exists.
To this end, the present embodiment overcomes the above-described problems by the following improvements:
as shown in fig. 2-4, a semiconductor with double-sided pads comprises a chip 2, a package body 3 and a lead frame 1, wherein the chip 2 is arranged on the lead frame 1 and electrically connected with a plurality of bottom pads on the lead frame 1, a plurality of top pads are arranged on one side of the package body 3 away from the bottom pads, and the top pads are in one-to-one correspondence with the bottom pads and are electrically connected with the bottom pads. The lead frame 1 can provide mechanical support, thermal conduction and electrical conduction for the chip. Specifically, the connection between the bottom pad and the top pad needs to satisfy the condition of electrical and thermal conductivity, and it is generally preferable to use a metal material for the connection.
Therefore, according to the scheme, the semiconductor can be welded on the circuit board by utilizing the bottom welding plate, and the conduction with the circuit board is realized. When breaking down, can directly utilize the top pad at semiconductor top to inspect, need not to pull down the semiconductor from the circuit board, labour saving and time saving has avoided the risk of destroying the product again. In addition, because the top of the semiconductor is provided with the top bonding pad, other components can be directly connected in series on the top of the semiconductor to carry out lamination packaging, and the beneficial effect of saving space can be achieved.
The top pad and the connection scheme of the top pad and the bottom pad of the present solution are described below in preferred feasible manners:
in an alternative, at least one of the top pads is formed by extending the lead frame 1, and the lead frame 1 is bent toward the direction of the package body 3 away from the bottom pad and extends to the top of the package body 3 to form the top pad. In this way, the part of the top of the package body 3 is exposed on the package body 3 to form a top bonding pad, the top bonding pad and the corresponding bottom bonding pad are integrated, and no other connecting structure is needed to be arranged between the top bonding pad and the bottom bonding pad.
Alternatively, the present embodiment further includes a copper clip 5 electrically connected to both the bottom pad and the chip 2, and at least one of the top pads is formed by a portion of the copper clip 5 facing away from the bottom pad. In this way, the bonding between the bottom pad and the chip 2 is directly realized through the copper clip 5, the metal wire 22 is omitted, the top of the copper clip 5 is exposed out of the packaging body 3 to serve as the top pad, and no other connecting structure is needed to be arranged between the top pad and the bottom pad, so that the material is saved, and the manufacturing process is simplified.
Alternatively, at least one pair of the top pads and the bottom pads are connected by VIA holes 6 penetrating the package body 3.
Further, for the top pad corresponding to the VIA hole 6, it is integrally formed with the VIA hole 6 by electroplating.
Namely, through holes are reserved in the packaging body 3 during plastic packaging, then metal is electroplated in the through holes to form VIA holes 6 with electric and thermal conductivity, and meanwhile, the electroplated layer extends to the top of the packaging body 3 to form a top bonding pad. Wherein, the through holes can be fully plated during electroplating, and only the hole walls of the through holes can be plated. The VIA hole 6 and the top bonding pad formed by the connection in the mode are good in combination with the packaging body 3, and the structure is reliable and durable.
As for the specific structure of the lead frame 1, the lead frame includes a plurality of bottom pads, the bottom pads include a substrate pad 11 and at least one lead pad 12, the first pad 41 corresponds to the substrate pad 11, and the second pad 42 corresponds to the lead pad 12. The substrate pad 11 is used for supporting the chip 2 and providing a heat dissipation function for the chip 2; the lead pads 12 are bonded to the chip 2 and primarily provide signal paths for the chip 2. To this end, the top pad of the present solution includes a first pad 41 and a second pad 42 corresponding to the substrate pad 11 and the pin pad 12, respectively.
In particular, various specific semiconductor structure embodiments are provided below:
as one of the ways, referring to fig. 2, all the top pads (including the first pad 41 and the second pad 42) are respectively formed by bending the lead frame 1 toward the direction of the package body 3 away from the bottom pads (the substrate pad 11 and the pin pad 12) and extending to the top of the package body 3.
Alternatively, referring to fig. 3, the first pads 41 are formed by bending the lead frame 1 toward the direction of the package body 3 away from the bottom pads and extending to the top of the package body 3; the second pad 42 is formed by the portion of the copper clip 5 facing away from the bottom pad.
Alternatively, referring to fig. 4, all the top pads (including the first pad 41 and the second pad 42) and the bottom pads (the substrate pad 11 and the lead pad 12) are connected by VIA holes 6 penetrating through the package body 3.
Alternatively (not shown), the first pads 41 are formed by bending the lead frame 1 toward the package body 3 away from the bottom pads and extending to the top of the package body 3; the second pads 42 and the bottom pads are connected by VIA holes 6 penetrating the package body 3.
The above embodiments are only preferred embodiments, and those skilled in the art can combine various embodiments to obtain new embodiments, which will fall into the scope of the present application.
Based on the above solutions, the bottom pad is located at the bottom of the package body 3, and can be used for being soldered on a circuit board to fix a semiconductor and electrically connect the semiconductor, heat generated during the operation of the chip 2 can be conducted to the circuit board through the substrate pad 11 to dissipate heat, and the chip 2 can be electrically connected to the circuit board through the metal wire 22 and the pin pad 12. This scheme still sets up the top pad with bottom pad one-to-one at the semiconductor top, then, when the product that has this semiconductor became invalid, can directly detect the troubleshooting fault point through the top pad, need not to pull down this semiconductor, saves time promptly, has avoided dismantling the risk that the semiconductor caused the destruction to the product again. On the other hand, other components can be directly connected in series on the top of the semiconductor to carry out lamination packaging, and when the other components are installed, the chip 2 and the circuit board can be electrically conducted through bonding with the second bonding pad 42; in addition, the first pad 41 is connected to the substrate pad 11, that is, an efficient heat conduction path is established therebetween, and heat on the first pad 41 can be quickly transferred to the substrate pad 11, so that other components on the top of the semiconductor can realize accelerated heat dissipation through the first pad 41 and the substrate pad 11 by connection with the first pad 41.
In the description herein, it is to be understood that the terms "upper," "lower," "left," "right," and the like are used in an orientation or positional relationship merely for convenience in description and simplicity of operation, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the present application. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principles of the present application have been described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the present application and is not to be construed in any way as limiting the scope of the application. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present application without inventive effort, which shall fall within the scope of the present application.

Claims (10)

1. The utility model provides a semiconductor with two-sided pad, its characterized in that includes chip (2), packaging body (3) and lead frame (1), chip (2) set up on lead frame (1) and with a plurality of bottom pad electricity on lead frame (1) are connected, packaging body (3) are kept away from one side of bottom pad is provided with a plurality of top pads, the top pad with bottom pad one-to-one and electric connection.
2. A semiconductor device with double-sided pads according to claim 1, wherein at least one of the top pads is formed by extending the lead frame (1), and the lead frame (1) is bent toward the package body (3) away from the bottom pad and extends to the top of the package body (3) to form the top pad.
3. A semiconductor with double-sided pads according to claim 2, characterized in that it further comprises a copper clip (5) electrically connected both to the bottom pad and to the chip (2), at least one of the top pads being formed by a portion of the copper clip (5) facing away from the bottom pad.
4. A semiconductor with double-sided pads according to claim 3, wherein the top pads comprise first pads (41) and second pads (42), the first pads (41) are formed by bending the lead frame (1) towards the direction of the package body (3) away from the bottom pads and extending to the top of the package body (3); the second pad (42) is formed by a portion of the copper clip (5) facing away from the bottom pad.
5. The semiconductor with double-sided pads according to claim 1, wherein all the top pads are formed by bending the lead frame (1) towards the direction of the package body (3) away from the bottom pads and extending to the top of the package body (3), respectively.
6. A semiconductor device having double-sided pads according to claim 1, wherein at least one pair of the top pads and the bottom pads are connected by VIA holes (6) penetrating the package body (3).
7. The semiconductor device with double-sided pads according to claim 6, wherein all the top pads and the bottom pads are connected by VIA holes (6) penetrating the package body (3).
8. The semiconductor with double-sided pads according to claim 6, wherein the top pads comprise first pads (41) and second pads (42), the first pads (41) are formed by bending the lead frame (1) towards the direction of the package body (3) away from the bottom pads and extending to the top of the package body (3); the second bonding pad (42) and the bottom bonding pad are connected through a VIA hole (6) penetrating through the packaging body (3).
9. The semiconductor device with double-sided pads according to any one of claims 6 to 8, wherein the top pads corresponding to the VIA holes (6) are formed by electroplating integrally with the VIA holes (6).
10. The semiconductor device with double-sided pads according to claim 4 or 8, wherein the bottom pad comprises a substrate pad (11) and at least one lead pad (12), the first pad (41) corresponds to the substrate pad (11), and the second pad (42) corresponds to the lead pad (12).
CN202122646948.2U 2021-11-01 2021-11-01 Semiconductor with double-sided bonding pad Active CN216354179U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202122646948.2U CN216354179U (en) 2021-11-01 2021-11-01 Semiconductor with double-sided bonding pad

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202122646948.2U CN216354179U (en) 2021-11-01 2021-11-01 Semiconductor with double-sided bonding pad

Publications (1)

Publication Number Publication Date
CN216354179U true CN216354179U (en) 2022-04-19

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Country Status (1)

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CN (1) CN216354179U (en)

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