CN110620094A - Packaging structure and packaging process of power semiconductor device - Google Patents
Packaging structure and packaging process of power semiconductor device Download PDFInfo
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- CN110620094A CN110620094A CN201910969687.2A CN201910969687A CN110620094A CN 110620094 A CN110620094 A CN 110620094A CN 201910969687 A CN201910969687 A CN 201910969687A CN 110620094 A CN110620094 A CN 110620094A
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- heat dissipation
- semiconductor device
- power semiconductor
- ceramic substrate
- packaging
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A packaging structure of a power semiconductor device and a packaging process thereof belong to the technical field of power semiconductor device packaging, the packaging structure of the power semiconductor device comprises a packaging body, an internal circuit and a heat dissipation substrate, wherein the internal circuit and the heat dissipation substrate are formed by a chip, a bonding wire, a circuit carrier and a pin in the packaging body, the chip is connected with the pin through the bonding wire, the internal circuit is insulated and isolated from the heat dissipation substrate through the circuit carrier, the packaging structure realizes the internal insulation of the power semiconductor device, saves the link of adding an insulating sheet when in application and installation, improves the operating efficiency and the installation yield, improves the heat radiation performance of the power semiconductor device, the packaging structure has the advantages of simple packaging process, capability of realizing large-scale mass production, and capability of providing a power semiconductor device with better performance and lower installation cost.
Description
Technical Field
The invention relates to the technical field of power semiconductor device packaging, in particular to a packaging structure of a power semiconductor device and a packaging process thereof.
Background
At present, the packaging structure of the high-power semiconductor device is roughly divided into two types, one is a structure that the back of a packaging body is exposed with a heat dissipation substrate, and the other is a fully-packaged structure.
Fig. 1 is a side view of a package structure with a heat dissipation substrate exposed at the back of the package body, because a chip 2 is connected to a heat dissipation substrate 6 of the package body, an insulation sheet needs to be additionally installed between a heat dissipation surface of the heat dissipation substrate 6 and a heat sink to perform electrical insulation, so as to ensure the insulation performance of the application, when the insulation sheet is installed, the position and the proximity degree of the insulation sheet also relate to the quality of the insulation effect, so that the installation difficulty of an application end is increased, the heat conduction performance of the insulation sheet is generally 1-3W/mk, heat cannot be rapidly dissipated in a short time, and the heat transmission effect is general. As shown in fig. 2, which is a side view of a fully encapsulated package structure, due to the insulation performance of the package body 1 itself, it is not necessary to add an insulation sheet when installing a heat sink, the thickness of the package body 1 on the back of the package structure is usually between 0.4 mm and 0.6mm, the thermal conductivity of the resin material for plastic encapsulation is usually 1W/mk to 2W/mk, and the heat dissipation effect is worse. Therefore, how to simplify the installation process of the application end and improve the heat dissipation performance of the product is the research direction of the invention.
Disclosure of Invention
In order to solve the technical problems, the invention provides a packaging structure of a power semiconductor device, which mainly solves the problems of high installation difficulty of an application end and poor heat dissipation effect of the existing packaging structure.
In order to achieve the purpose, the technical scheme adopted by the invention for solving the technical problems is as follows: the packaging structure of the power semiconductor device comprises a packaging body, an internal circuit and a heat dissipation substrate, wherein the internal circuit and the heat dissipation substrate are arranged in the packaging body and consist of a chip, a bonding wire, a circuit carrier and a pin, the chip is connected with the pin through the bonding wire, and the internal circuit is insulated and isolated from the heat dissipation substrate through the circuit carrier.
Furthermore, the circuit carrier is a double-sided copper-clad ceramic substrate, the double-sided copper-clad ceramic substrate comprises a ceramic substrate and copper plates respectively sintered on two sides of the ceramic substrate, and the two copper plates of the ceramic substrate are respectively connected with the chip and the heat dissipation substrate through bonding materials.
Further, the bonding material is a solder material.
Furthermore, a heat dissipation substrate is arranged on the back of the double-sided copper-clad ceramic substrate, and the double-sided copper-clad ceramic substrate is insulated and isolated from the heat dissipation substrate through the ceramic substrate.
Furthermore, the heat dissipation substrate and the pins are arranged into an integrated frame structure, and the pins penetrate out of the packaging body.
Furthermore, the pins are provided with annular plastic packaging grooves for gathering plastic packaging materials along the length direction of the pins.
Further, the double-sided copper-clad ceramic substrate is arranged in the middle of the heat dissipation substrate, and the distance between the edge of the double-sided copper-clad ceramic substrate and the edge of the heat dissipation substrate in the horizontal direction is larger than 0.8 mm.
The packaging process of the packaging structure of the power semiconductor device comprises the following steps:
1) welding the bottom layer of the double-sided copper-clad ceramic substrate on the heat dissipation substrate through a bonding material;
2) welding the chip on the upper layer of the double-sided copper-clad ceramic substrate through the bonding material;
3) electrically connecting a chip with the pins through bonding wires;
4) and placing the connected chip, the double-sided copper-coated ceramic substrate, the heat dissipation substrate and the pins in an injection mold for plastic package to form a package body, and simultaneously exposing the back surface of the heat dissipation substrate out of the package body to enable the pins to extend out of the package body.
The invention has the beneficial effects that:
1. this packaging structure sets up to the structure that the radiating basal plate is exposed to the packaging body back, through setting up the circuit carrier in the internal circuit, carries out insulation and isolation with internal circuit and radiating basal plate through the circuit carrier, has realized power semiconductor device's internal insulation, has saved the link that needs install the insulating piece additional when using the installation, has improved operating efficiency and installation yield, can in time spill the heat through the mode that exposes the radiating basal plate in addition, has improved heat dispersion.
2. Specifically, the circuit carrier is a double-sided copper-clad ceramic substrate, two copper plates of the double-sided copper-clad ceramic substrate are respectively connected with the chip and the heat dissipation substrate in a welding mode through a bonding material, the heat dissipation coefficient and the heat conductivity coefficient of the ceramic substrate in the double-sided copper-clad ceramic substrate can reach 20W/mk, the heat dissipation performance is good, the ceramic substrate is made of an insulating material, the double-sided copper-clad ceramic substrate is applied to packaging of a power semiconductor device, the heat dissipation performance of the product is improved, the heat conduction and insulation pressure resistance of the power semiconductor device is improved, meanwhile, the risk of insulation failure of the power semiconductor device is avoided, electrical insulation between an internal circuit of the product and the heat dissipation substrate is further realized, and the mounting difficulty of an application end of the power semiconductor device is.
3. Specifically, the packaging structure has a simple overall structure, the packaging process is simple, and meanwhile, the possibility of realizing large-scale mass production is realized, so that the power semiconductor device with better performance and lower installation cost can be provided.
In summary, the present invention provides a novel package structure and a package process thereof, the package structure realizes internal insulation of a power semiconductor device, saves a link of installing an insulating sheet when in application and installation, improves operation efficiency and installation yield, and improves heat dissipation performance of the power semiconductor device.
Drawings
The contents of the expressions in the various figures of the present specification and the labels in the figures are briefly described as follows:
FIG. 1 is a schematic diagram of a package structure in the prior art;
FIG. 2 is a schematic diagram of another package structure in the prior art;
FIG. 3 is a schematic structural diagram of a package structure according to the present invention;
the labels in the above figures are: 1. the packaging structure comprises a packaging body, 2 parts of a chip, 3 parts of bonding wires, 4 parts of a circuit carrier, 41 parts of a ceramic substrate, 42 parts of a copper plate, 5 parts of pins, 51 parts of an annular plastic packaging groove and 6 parts of a heat dissipation substrate.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and the following embodiments are used for illustrating the present invention and are not intended to limit the scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The specific implementation scheme of the invention is as follows: as shown in fig. 3, the side view of the package structure of the power semiconductor device in the present invention is a bilaterally symmetric structure, the package structure includes a package 1, and an internal circuit and a heat dissipation substrate 6, which are formed by a chip 2, a bonding wire 3, a circuit carrier 4, and a pin 5, inside the package 1, the chip 2 and the pin 5 are connected through the bonding wire 3, and the internal circuit is isolated from the heat dissipation substrate 6 through the circuit carrier 4. This packaging structure sets up to the structure that the radiating basal plate 6 is exposed to packaging body 1 back, through set up circuit carrier 4 in the internal circuit, carry out insulation isolation with internal circuit and radiating basal plate 6 through circuit carrier 4, has realized power semiconductor's internal insulation, has saved the link that needs install the insulating piece additional when using the installation, has improved operating efficiency and installation yield, can in time spill the heat through the mode that exposes radiating basal plate 6 in addition, has improved heat dispersion.
Specifically, the circuit carrier 4 is a double-sided copper-clad ceramic substrate, the double-sided copper-clad ceramic substrate is of an integrated structure and comprises a ceramic substrate 41 and copper plates 42 respectively sintered on two sides of the ceramic substrate 41, the two copper plates 42 on the two sides of the ceramic substrate 41 are respectively connected with the chip 2 and the heat dissipation substrate 6 in a welding mode through bonding materials formed by tin paste, tin sheets or tin wires and other tin soldering materials, the ceramic substrate 41 is made of ceramic materials, the heat dissipation coefficient of the ceramic substrate can reach 20W/mk, compared with insulating sheets and resin materials for plastic package in the prior art, the ceramic substrate 41 is high in heat dissipation coefficient and good in heat dissipation performance, the ceramic substrate 41 is made of insulating materials, electrical insulation between an internal circuit of a product and the heat dissipation substrate is achieved, and further the installation difficulty of an application end of a power semiconductor device. The double-sided copper-clad ceramic substrate is applied to packaging of a power semiconductor device, so that the heat dissipation performance of the product is improved, the heat conduction and insulation voltage resistance of the power semiconductor device is improved, the risk of insulation failure of the power semiconductor device is avoided, the electrical insulation between an internal circuit of the product and the heat dissipation substrate is realized, and the problem which is not solved by technical personnel in the field is solved.
Specifically, the heat dissipation substrate 6 is arranged on the back of the double-sided copper-clad ceramic substrate, the heat dissipation substrate 6 is exposed out of the back of the packaging body 1, the heat dissipation substrate 6 is made of a common copper material, an aluminum material or an alloy material, and a heat radiator is additionally arranged on the back of the heat dissipation substrate 6, so that heat generated by an internal circuit can be timely transmitted through the ceramic substrate 41 and the heat dissipation substrate 6 in the double-sided copper-clad ceramic substrate in sequence, the heat is timely and quickly dissipated by the heat radiator, and the heat dissipation performance of the power semiconductor device is further improved.
In addition, the heat dissipation substrate 6 and the pins 5 are arranged into an integrated frame structure, so that the stability of the whole structure is improved, the installation difficulty is reduced, and the pins 5 penetrate out of the packaging body 1 to be electrically connected with other components; the pin 5 is provided with an annular plastic packaging groove 51 for gathering plastic packaging materials along the length direction, and when a product is subjected to plastic packaging, the annular plastic packaging groove 51 can be used for realizing necking sealing of the plastic packaging materials, so that the quality of the plastic packaging is further improved; the double-sided copper-clad ceramic substrate is arranged in the middle of the heat dissipation substrate 6, and the distance between the edge of the double-sided copper-clad ceramic substrate and the edge of the heat dissipation substrate 6 in the horizontal direction is greater than 0.8mm, because under different use conditions, in order to prevent the creepage phenomenon of pollutants possibly occurring on the surfaces of the chip 2 and the double-sided copper-clad ceramic substrate between the heat dissipation substrates 6, the double-sided copper-clad ceramic substrate is polarized, and the insulation failure phenomenon is caused, under various use conditions and environmental factors such as comprehensive rated voltage, pollution conditions, insulating materials, surface shapes, position directions, voltage bearing time lengths and the like, according to experience values, when the distance between the edge of the double-sided copper-clad ceramic substrate and the edge of the heat dissipation substrate 6 in the horizontal direction is greater than 0.8mm, the creepage phenomenon can be prevented, and the internal insulation failure is prevented.
In conclusion, the packaging structure is simple in overall structure, internal insulation of the power semiconductor device is achieved, the link that an insulating sheet needs to be additionally installed in application and installation is omitted, the working efficiency and the installation yield are improved, and the heat dissipation performance of the power semiconductor device is improved.
The packaging process of the packaging structure of the power semiconductor device comprises the following steps:
1) welding the bottom layer of the double-sided copper-clad ceramic substrate on the heat dissipation substrate 6 through the bonding material, wherein the requirement that the distance between the edge of the double-sided copper-clad ceramic substrate and the edge of the heat dissipation substrate 6 in the horizontal direction is more than 0.8mm is met;
2) welding the chip 2 on the upper layer of the double-sided copper-clad ceramic substrate through the bonding material;
3) electrically connecting a chip 2 with pins 5 through bonding wires 3, wherein the chip 2 comprises two electrodes which are respectively connected with the corresponding pins 5 through the bonding wires 3;
4) and placing the connected chip 2, the double-sided copper-clad ceramic substrate, the heat dissipation substrate 6 and the pins 5 in an injection mold for plastic package to form a package body 1, and simultaneously exposing the back surface of the heat dissipation substrate 6 out of the package body 1 to enable the pins 5 to extend out of the package body 1.
The packaging process is simple, has the possibility of realizing large-scale mass production, can provide a power semiconductor device with better performance and lower installation cost, and is suitable for popularization and use.
While the foregoing is directed to the principles of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (8)
1. The packaging structure of the power semiconductor device is characterized by comprising a packaging body (1), an internal circuit and a heat dissipation substrate (6), wherein the internal circuit is formed by a chip (2), a bonding wire (3), a circuit carrier (4) and pins (5) in the packaging body (1), the chip (2) is connected with the pins (5) through the bonding wire (3), and the internal circuit is insulated and isolated from the heat dissipation substrate (6) through the circuit carrier (4).
2. The package structure of a power semiconductor device according to claim 1, wherein: the circuit carrier (4) is a double-sided copper-clad ceramic substrate, the double-sided copper-clad ceramic substrate comprises a ceramic substrate (41) and copper plates (42) which are respectively sintered on two sides of the ceramic substrate (41), and the two copper plates (42) of the ceramic substrate (41) are respectively connected with the chip (2) and the heat dissipation substrate (6) through bonding materials.
3. The package structure of a power semiconductor device according to claim 2, wherein: the bonding material is a solder material.
4. The package structure of a power semiconductor device according to claim 2, wherein: the back of the double-sided copper-clad ceramic substrate is provided with a heat dissipation substrate (6), and the double-sided copper-clad ceramic substrate is insulated and isolated from the heat dissipation substrate (6) through a ceramic substrate (41) in the double-sided copper-clad ceramic substrate.
5. The package structure of a power semiconductor device according to any one of claims 1 to 4, wherein: the heat dissipation substrate (6) and the pins (5) are arranged into an integrated frame structure, and the pins (5) penetrate out of the packaging body (1).
6. The package structure of a power semiconductor device according to claim 5, wherein: the pin (5) is provided with an annular plastic packaging groove (51) for gathering plastic packaging materials along the length direction of the pin.
7. The package structure of a power semiconductor device according to claim 5, wherein: the double-sided copper-clad ceramic substrate is arranged in the middle of the heat dissipation substrate (6), and the distance between the edge of the double-sided copper-clad ceramic substrate and the edge of the heat dissipation substrate (6) in the horizontal direction is larger than 0.8 mm.
8. A packaging process of the packaging structure of the power semiconductor device according to any one of claims 1 to 7, characterized in that: the method comprises the following steps:
1) welding the bottom layer of the double-sided copper-clad ceramic substrate on the heat dissipation substrate (6) through a bonding material;
2) welding the chip (2) on the upper layer of the double-sided copper-clad ceramic substrate through a bonding material;
3) electrically connecting a chip (2) with the pins (5) through bonding wires (3);
4) the connected chip (2), the double-sided copper-clad ceramic substrate, the heat dissipation substrate (6) and the pins (5) are placed in an injection mold for plastic package to form a package body (1), and meanwhile, the back of the heat dissipation substrate (6) is exposed out of the package body (1), so that the pins (5) extend out of the package body (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910969687.2A CN110620094A (en) | 2019-10-12 | 2019-10-12 | Packaging structure and packaging process of power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910969687.2A CN110620094A (en) | 2019-10-12 | 2019-10-12 | Packaging structure and packaging process of power semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| CN110620094A true CN110620094A (en) | 2019-12-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910969687.2A Pending CN110620094A (en) | 2019-10-12 | 2019-10-12 | Packaging structure and packaging process of power semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111987001A (en) * | 2020-07-16 | 2020-11-24 | 杰群电子科技（东莞）有限公司 | Manufacturing method of power semiconductor structure, chip carrier and power semiconductor structure |
| CN112802804A (en) * | 2020-12-22 | 2021-05-14 | 湖南工业大学 | Power semiconductor device packaging structure for rolling mill |
-
2019
- 2019-10-12 CN CN201910969687.2A patent/CN110620094A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111987001A (en) * | 2020-07-16 | 2020-11-24 | 杰群电子科技（东莞）有限公司 | Manufacturing method of power semiconductor structure, chip carrier and power semiconductor structure |
| CN112802804A (en) * | 2020-12-22 | 2021-05-14 | 湖南工业大学 | Power semiconductor device packaging structure for rolling mill |
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Address after: 241000 1803, building 3, service outsourcing park, Wuhu high tech Industrial Development Zone, Anhui Province Applicant after: Anhui Changfei Advanced Semiconductor Co.,Ltd. Address before: 241000 1803, building 3, service outsourcing park, high tech Industrial Development Zone, Yijiang District, Wuhu City, Anhui Province Applicant before: WUHU QIDI SEMICONDUCTOR Co.,Ltd. |
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