CN216084887U - 一种双管芯合封的共源共栅GaN功率器件 - Google Patents
一种双管芯合封的共源共栅GaN功率器件 Download PDFInfo
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Abstract
本实用新型公开了一种双管芯合封的共源共栅GaN功率器件,其中包含合封的GaN‑FET管芯和Si‑LDMOS管芯,Si‑LDMOS管芯的漏极与GaN‑FET管芯的源极相连,GaN‑FET管芯的源、漏极均由正面引出,其中漏极作为GaN功率器件成品的漏极引出,Si‑LDMOS管芯的栅极引出作为GaN功率器件成品的栅极引出,Si‑LDMOS管芯的源极从背面引出,与GaN‑FET管芯的栅极相连并引出作为GaN功率器件成品的源极引出。本实用新型提出了一种新封装结构,通过加大引线框架面积,将Si‑LDMOS管芯焊接在框架上,相应PIN脚直接引出,最大程度降低封装的共源极寄生电感。本实用新型通过若干优化封装方案,显著降低合封器件的源极寄生电感,提升GaN功率器件的开关性能。
Description
技术领域
本实用新型属于功率器件技术领域,具体涉及一种双管芯合封的共源共栅GaN功率器件。
背景技术
目前,常规的共源共栅结构的氮化镓(Cascode GaN)功率器件,通常采用VDMOS(Vertical-Diffused Metal-Oxide-Semiconductor,垂直扩散金属氧化物半导体场效应晶体管)器件与GaN-FET(氮化镓场效应管)进行双管芯合封。其对应的常规结构的VDMOS器件,其漏极通常由背面引出(Drain-down),而栅极、源极分布于管芯的另一侧,在采用单基岛的情况下,很难通过基板和框架结构直接将VDMOS器件的源极引出到外部。这就意味着采用VDMOS器件进行合封设计的Cascode GaN功率器件,其源极需要通过连接线引出,导致其源极串联电感、电阻通常较高。此外对于共源共栅结构的连接方式,MOS管的漏端(Drain)需要与GaN器件的源端(Source)相连,MOS器件的源极(Source)需要与GaN器件的栅极(Gate)相连),而氮化镓场效应管GaN FET通常为平面结构器件,其漏极、栅极、源极均分布于管芯的同一侧,常规的平面封装方案相对复杂,主功率回路电流路径交错曲折,封装引入的寄生杂散较大,这在很大程度上限制了封装后成品器件的整体性能(如器件的开关速度、开关振荡等性能)。
实用新型内容
本实用新型的主要目的在于提供一种双管芯合封的共源共栅GaN功率器件,从而克服现有技术的不足。
为实现前述实用新型目的,本实用新型采用的技术方案包括:一种双管芯合封的共源共栅GaN功率器件,所述GaN功率器件包含合封的GaN-FET管芯和Si-LDMOS管芯,所述Si-LDMOS管芯的漏极与GaN-FET管芯的源极相连,所述GaN-FET管芯的源、漏极均由正面引出,其中漏极作为GaN功率器件成品的漏极引出,所述Si-LDMOS管芯的栅极引出作为GaN功率器件成品的栅极引出,所述Si-LDMOS管芯的源极从背面引出,与GaN-FET管芯的栅极相连并引出作为GaN功率器件成品的源极引出。
在一优选实施例中,所述GaN功率器件采用TO外形的平面封装方式进行封装。
在一优选实施例中,所述GaN功率器件包括第一基板、第二基板和第一引线框架,所述GaN-FET管芯和第二基板均直接固定于所述第一基板上,所述Si-LDMOS管芯固定于一第一引线框架上,所述Si-LDMOS管芯的漏极与GaN-FET管芯的源极相连,所述GaN-FET管芯的漏极从正面引出到第一基板上,作为GaN功率器件的漏极引出,所述Si-LDMOS管芯的栅极通过第二基板引出作为GaN功率器件的栅极,所述GaN-FET管芯的栅极通过第一引线框架与所述Si-LDMOS管芯的源极相连,所述Si-LDMOS管芯的源极从背面引出到第一引线框架上,作为GaN功率器件的源极引出。
在一优选实施例中,所述Si-LDMOS管芯的漏极与GaN-FET管芯的源极之间、所述GaN-FET管芯的栅极与所述第一引线框架之间、所述Si-LDMOS管芯的栅极与第二基板之间通过连接件相连,所述第二基板通过连接件引出GaN功率器件的栅极,以及所述GaN-FET管芯的漏极通过与第一基板相连的第二引线框架引出。
在一优选实施例中,所述连接件为引线或铝带或铜夹。
在一优选实施例中,所述GaN功率器件采用DFN外形的表贴式平面封装方式进行封装。
在一优选实施例中,所述GaN功率器件包括第一基板和第二基板,所述GaN-FET管芯固定于所述第一基板上,所述Si-LDMOS管芯固定于所述第二基板上,所述Si-LDMOS管芯的漏极与GaN-FET器件的源极相连,所述GaN-FET管芯的漏极从正面引出到第一基板上,作为GaN功率器件的漏极引出,所述Si-LDMOS管芯的栅极引出作为GaN功率器件的栅极引出,所述GaN-FET管芯的栅极与第二基板相连,所述Si-LDMOS管芯的源极从背面引出到第二基板,引出作为GaN功率器件的源极。
在一优选实施例中,所述Si-LDMOS管芯的漏极与GaN-FET管芯的源极之间、所述GaN-FET管芯的栅极与第二基板之间、所述GaN-FET管芯的漏极与第一基板之间通过连接件相连,所述Si-LDMOS管芯的栅极通过连接件引出。
与现有技术相比较,本实用新型的有益效果至少在于:本实用新型利用源极背面引出的LDMOS(横向扩散金属氧化物半导体场效应晶体管)器件替代传统的VDMOS器件,配合GaN-FET(碳化硅结型场效应管)形成共源共栅结构,用以实现双管芯合封的Cascode GaN功率器件,与常规Cascode GaN功率器件相比,本实用新型所提出的Cascode GaN功率器件可以简化封装方案,将Cascode器件源极引出的方式由常规的引线绑定(键合)优化为直接通过管芯与基板的焊接,由裸露焊盘或与基板直接相连的框架连接到成品的外部PIN脚。经过优化,Cascode GaN功率器件的源极串联寄生电感大幅下降,在应用中连接驱动电路后,整体电路的CSI(Common Source Inductance,共源极寄生电感感量)大幅下降,这将加快开关速度,提高有效驱动电压,同时显著抑制器件的开关振荡现象。
附图说明
为了更清楚地说明本实用新型实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本实用新型中记载的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本实用新型GaN功率器件的内部结构示意图;
图2是本实用新型实施例1中GaN功率器件的封装结构示意图;
图3是本实用新型实施例2中GaN功率器件的封装结构示意图;
图4是本实用新型实施例3中GaN功率器件的封装结构示意图;
图5是本实用新型实施例4中GaN功率器件的封装结构示意图。
具体实施方式
通过应连同所附图式一起阅读的以下具体实施方式将更完整地理解本实用新型。本文中揭示本实用新型的详细实施例;然而,应理解,所揭示的实施例仅具本实用新型的示范性,本实用新型可以各种形式来体现。因此,本文中所揭示的特定功能细节不应解释为具有限制性,而是仅解释为权利要求书的基础且解释为用于教示所属领域的技术人员在事实上任何适当详细实施例中以不同方式采用本实用新型的代表性基础。
本实用新型所揭示的一种双管芯合封的共源共栅GaN功率器件,利用源极背面引出结构的LDMOS(横向扩散金属氧化物半导体)器件,与GaN器件(管芯)合封形成共源共栅结构的GaN功率器件,通过优化封装方案,显著降低合封器件的共源极寄生电感量,提升器件的开关性能。如图1所示,其具体包括GaN器件1和LDMOS器件2,其中,GaN器件1作为主器件(管芯),在关断状态下承受高源漏电压。优选地,GaN器件1采用耗尽型GaN器件,其在零栅源电压状态下为导通状态,因此也被称为长通型器件。当此器件与LDMOS器件2串联,以LDMOS器件2作为GaN管1的源极驱动器件,则通过LDMOS器件2的导通、关断即可实现共源共栅结构整体的导通和关断。
具体地,如图1所示,LDMOS器件2的漏极d与GaN器件1的源极s相连接,该中点作为合封器件(即GaN功率器件)的内部节点不引到外部;GaN器件1的漏极d引出作为合封器件的漏极D引出到外部,LDMOS器件2的栅极g引出并作为合封器件的栅极G引出到外部;LDMOS器件2的源极s与GaN器件1的栅极g相连并引出作为合封器件的源极S引出到外部。
下面以几个具体实施例,来详细描述GaN器件1与LDMOS器件2合封的封装结构。
实施例1
如图2所示,本实用新型实施例2所揭示的一种双管芯合封的共源共栅GaN功率器件10,封装方式为平面封装方式,具体为TO外形封装。具体包括第一基板11、第二基板12、第一引线框架13、第二引线框架14、GaN-FET管芯16和Si-LDMOS管芯17,其中,GaN-FET管芯16和第二基板12均直接固定于第一基板11上,Si-LDMOS管芯17固定于一第一引线框架13上,Si-LDMOS管芯17的漏极D1与GaN-FET管芯16的源极S2相连,GaN-FET管芯16的漏极D2从对应管芯的背面引出到第一基板11上,作为GaN功率器件10的漏极D引出,Si-LDMOS管芯17的栅极G1通过第二基板12引出作为GaN功率器件10的栅极G,GaN-FET管芯16的栅极G2通过第一引线框架13与Si-LDMOS管芯17的源极相连,Si-LDMOS管芯17的源极从对应管芯的背面引出到第一引线框架13上,作为GaN功率器件10的源极S引出。本实施例1中,Si-LDMOS管芯17的漏极D1与GaN-FET管芯16的源极S2之间、GaN-FET管芯16的栅极G2与第一引线框架13之间、Si-LDMOS管芯17的栅极G1与第二基板12之间通过引线15(具体可为键合线)相连,第二基板12通过引线15引出GaN功率器件20的栅极G,以及GaN-FET管芯16的漏极D2通过与第一基板11相连的第二引线框架14引出。
本实施例2中,该TO外形的封装方案通过定制化的框架设计,将器件10的源极S对应的打线框架部分加长加宽,将Si-LDMOS管芯17直接焊接在第一引线框架13上。该方案将Si-LDMOS管芯17的源极通过第一引线框架13直接引出,与用键合引线的方式相比,最大程度上降低了封装引入的源极寄生参数。
实施例2
如图3所示,本实用新型实施例2所揭示的一种双管芯合封的共源共栅GaN功率器件20,封装方式同样也为平面封装方式,具体为TO外形封装。具体包括第一基板21、第二基板22、第一引线框架23、第二引线框架24、GaN-FET管芯26和Si-LDMOS管芯27,其中,GaN-FET管芯26和第二基板22均直接固定于第一基板21上,Si-LDMOS管芯27固定于一第一引线框架23上,Si-LDMOS管芯27的漏极D1与GaN-FET管芯26的源极S2相连,GaN-FET管芯26的漏极从对应管芯的正面引出到第一基板21上,作为GaN功率器件20的漏极D引出,Si-LDMOS管芯27的栅极G1通过第二基板22引出作为GaN功率器件20的栅极G,GaN-FET管芯26的栅极G2通过第一引线框架23与Si-LDMOS管芯27的源极相连,Si-LDMOS管芯27的源极从对应管芯的背面引出到第一引线框架23上,作为GaN功率器件20的源极S引出。本实施例2中,Si-LDMOS管芯27的漏极D1与GaN-FET管芯26的源极S2之间、GaN-FET管芯26的漏极D2与第一基板21之间通过铜夹28相连,GaN-FET管芯26的栅极G2与第一引线框架23之间、Si-LDMOS管芯27的栅极G1与第二基板22之间通过引线25(具体可为键合线)相连,第二基板22通过引线25引出GaN功率器件20的栅极G,以及GaN-FET管芯26的漏极D通过与第一基板21相连的第二引线框架24引出。与实施例1不同的是,本实施例2将Si-LDMOS管芯27的漏极D1与GaN-FET管芯26的源极S2之间、GaN-FET管芯26的漏极D2与第一基板21之间替换为通过铜夹28方式相连,可进一步降低功率回路的寄生串联电感,抑制器件开关振荡,提高器件性能。
实施例3
如图4所示,本实用新型实施例3所揭示的一种双管芯合封的共源共栅GaN功率器件30,封装方式同样也为平面封装方式,具体为DFN外形的表贴式封装方案,该封装方案采用双基岛结构。具体包括第一基板31、第二基板32、GaN-FET管芯36和Si-LDMOS管芯37,其中,GaN-FET管芯36固定于第一基板31上,Si-LDMOS管芯37固定于第二基板32上,Si-LDMOS管芯37的漏极D1与GaN-FET管芯36的源极S2相连,GaN-FET管芯36的漏极从对应管芯的正面引出到第一基板31,作为GaN功率器件30的漏极D引出,Si-LDMOS管芯37的栅极引出作为GaN功率器件30的栅极G引出,GaN-FET管芯36的栅极G2与第二基板32相连,Si-LDMOS管芯37的源极从对应管芯的背面引出到第二基板32,引出作为GaN功率器件30的源极S。本实施例3中,Si-LDMOS管芯36的漏极D1与GaN-FET管芯36的源极S2之间、GaN-FET管芯36的栅极G2与第二基板32之间通过引线34(具体可为键合线)相连,Si-LDMOS管芯37的栅极G1通过引线34引出。
本实施例4中,该封装方案采用双基岛结构,根据实际合封的管芯尺寸和顶层焊盘(PAD)的位置,可以做调整优化。该方案与现有合封VDMOS的Cascode GaN器件方案相比复杂度降低(减少了一组键合线),且同样实现了源极的直接引出,可显著降低封装引入的源极寄生串联电感(CSI),提高封装性能。
实施例4
如图5所示,本实用新型实施例4所揭示的一种双管芯合封的共源共栅GaN功率器件40,封装方式同样也为平面封装方式,具体为DFN外形的表贴式封装方案,该封装方案采用双基岛结构。具体包括第一基板41、第二基板42、GaN-FET管芯45和Si-LDMOS管芯46,其中,GAN-FET管芯45固定于第一基板41上,Si-LDMOS管芯46固定于第二基板42上,Si-LDMOS管芯46的漏极D1与GaN-FET管芯45的源极S2相连,GaN-FET管芯45的漏极从对应管芯的正面引出到第一基板41上,作为GaN功率器件40的漏极D引出,Si-LDMOS管芯46的栅极引出作为GaN功率器件40的栅极G引出,GaN-FET管芯45的栅极G2与第二基板42相连,Si-LDMOS管芯46的源极从对应管芯的背面引出到第二基板42,引出作为GaN功率器件40的源极S。本实施例5中,Si-LDMOS管芯46的漏极D1与GaN-FET管芯45的源极S2之间替换为通过铜夹47方式相连,GaN-FET管芯45的栅极G2与第二基板42之间通过引线44(具体可为键合线)相连,Si-LDMOS管芯46的栅极G1通过引线44引出,Si-LDMOS管芯46的源极通过与第二基板42相连的引线框架43引出。与实施例3不同的是,本实施例4将Si-LDMOS管芯46的漏极D1与GaN-FET管芯45的源极S2之间替换为通过铜夹47方式相连,相比于引线键合,铜夹焊接方式将提供更低的寄生参数,进一步提高器件性能。
本实用新型提出利用源极背面引出的Si-LDMOS器件替代传统的Si-VDMOS器件,配合GaN-FET形成Cascode结构,用以实现双管芯合封的Cascode GaN功率器件,与常规Cascode GaN功率器件相比,该实用新型所提出的Cascode GaN功率器件可以简化封装方案,将Cascode器件源极引出的方式由常规的引线绑定(键合)优化为直接通过管芯与基板的焊接,由裸露焊盘或与基板直接相连的框架连接到成品的外部PIN脚。经过优化,CascodeGaN功率器件的源极串联寄生电感大幅下降,在应用中连接驱动电路后,整体电路的CSI大幅下降,这将加快开关速度,提高有效驱动电压,同时显著抑制器件的开关振荡现象。
本实用新型的各方面、实施例、特征及实例应视为在所有方面为说明性的且不打算限制本实用新型,本实用新型的范围仅由权利要求书界定。在不背离所主张的本实用新型的精神及范围的情况下,所属领域的技术人员将明了其它实施例、修改及使用。
在本实用新型案中标题及章节的使用不意味着限制本实用新型;每一章节可应用于本实用新型的任何方面、实施例或特征。
Claims (9)
1.一种双管芯合封的共源共栅GaN功率器件,其特征在于,所述GaN功率器件包含合封的GaN-FET管芯和Si-LDMOS管芯,所述Si-LDMOS管芯的漏极与GaN-FET管芯的源极相连,所述GaN-FET管芯的源、漏极均由正面引出,其中漏极作为GaN功率器件成品的漏极引出,所述Si-LDMOS管芯的栅极引出作为GaN功率器件成品的栅极引出,所述Si-LDMOS管芯的源极从背面引出,与GaN-FET管芯的栅极相连并引出作为GaN功率器件成品的源极引出。
2.根据权利要求1所述的一种双管芯合封的共源共栅GaN功率器件,其特征在于:所述GaN功率器件采用TO外形的平面封装方式进行封装。
3.根据权利要求2所述的一种双管芯合封的共源共栅GaN功率器件,其特征在于:所述GaN功率器件包括第一基板、第二基板和第一引线框架,所述GaN-FET管芯和第二基板均直接固定于所述第一基板上,所述Si-LDMOS管芯固定于一第一引线框架上,所述Si-LDMOS管芯的漏极与GaN-FET管芯的源极相连,所述GaN-FET管芯的漏极从正面引出到第一基板上,作为GaN功率器件的漏极引出,所述Si-LDMOS管芯的栅极通过第二基板引出作为GaN功率器件的栅极,所述GaN-FET管芯的栅极通过第一引线框架与所述Si-LDMOS管芯的源极相连,所述Si-LDMOS管芯的源极从背面引出到第一引线框架上,作为GaN功率器件的源极引出。
4.根据权利要求3所述的一种双管芯合封的共源共栅GaN功率器件,其特征在于:所述Si-LDMOS管芯的漏极与GaN-FET管芯的源极之间、所述GaN-FET管芯的栅极与所述第一引线框架之间、所述Si-LDMOS管芯的栅极与第二基板之间通过连接件相连,所述第二基板通过连接件引出GaN功率器件的栅极,以及所述GaN-FET管芯的漏极通过与第一基板相连的第二引线框架引出。
5.根据权利要求4所述的一种双管芯合封的共源共栅GaN功率器件,其特征在于:所述连接件为引线或铝带或铜夹。
6.根据权利要求1所述的一种双管芯合封的共源共栅GaN功率器件,其特征在于:所述GaN功率器件采用DFN外形的表贴式平面封装方式进行封装。
7.根据权利要求6所述的一种双管芯合封的共源共栅GaN功率器件,其特征在于:所述GaN功率器件包括第一基板和第二基板,所述GaN-FET管芯固定于所述第一基板上,所述Si-LDMOS管芯固定于所述第二基板上,所述Si-LDMOS管芯的漏极与GaN-FET器件的源极相连,所述GaN-FET管芯的漏极从正面引出到第一基板上,作为GaN功率器件的漏极引出,所述Si-LDMOS管芯的栅极引出作为GaN功率器件的栅极引出,所述GaN-FET管芯的栅极与第二基板相连,所述Si-LDMOS管芯的源极从背面引出到第二基板,引出作为GaN功率器件的源极。
8.根据权利要求7所述的一种双管芯合封的共源共栅GaN功率器件,其特征在于:所述Si-LDMOS管芯的漏极与GaN-FET管芯的源极之间、所述GaN-FET管芯的栅极与第二基板之间、所述GaN-FET管芯的漏极与第一基板之间通过连接件相连,所述Si-LDMOS管芯的栅极通过连接件引出。
9.根据权利要求8所述的一种双管芯合封的共源共栅GaN功率器件,其特征在于:所述连接件为引线或铝带或铜夹。
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