CN102983114A - 具有超薄封装的高性能功率晶体管 - Google Patents

具有超薄封装的高性能功率晶体管 Download PDF

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CN102983114A
CN102983114A CN2012103745360A CN201210374536A CN102983114A CN 102983114 A CN102983114 A CN 102983114A CN 2012103745360 A CN2012103745360 A CN 2012103745360A CN 201210374536 A CN201210374536 A CN 201210374536A CN 102983114 A CN102983114 A CN 102983114A
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thickness
pad
attached
linear
chip
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CN102983114B (zh
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J·A·和布搜摩
O·J·洛佩兹
J·A·诺奇尔
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

场效应晶体管封装包含具有第一线性厚度(150a)的引线框架和减小厚度的引线框架垫(151)；场效应晶体管芯片(140)的第一端附接到垫以及第二和第三端远离垫；第二线性厚度(1l0a)的金属板(110)连接第二晶体管端至封装端；第三线性厚度(112a)的金属板(112)连接第三晶体管端至封装端；第一线性厚度(约0.125mm)和第二线性厚度(约0.125mm)的总和加上附接材料(约0.05mm)构成封装厚度(约0.3mm)。

Description

具有超薄封装的高性能功率晶体管
发明领域
本发明通常涉及半导体器件和工艺领域，并且更具体的，涉及能有高电流、高功率和高速度的超薄QFN封装功率晶体管的结构和制造方法。
背景技术
对于当今多数功率转换器件来说，功率MOSFET芯片作为单个元件组装。器件使用金属引线框架，典型地，其具有由引线围绕的矩形垫；垫作为衬底，用于附接半导体芯片，而引线作为输出端。一般地，引线被形成为没有悬臂，并且以方形扁平无引线(QFN)或小外形无引线(SON)器件的方式设置。可以以多种方式提供芯片到引线的电连接。
在一类器件中，通过粘结导线来提供连接。由于导线的长度和电阻的原因，这些导线会将显著的寄生电感引入到功率电路中。典型地，每个组件封装在塑料外罩中，并且被封装元件用作离散构造块，用于电源系统的板组装。在其他类器件中，金属夹替代了多个或所有的连接导线。这些夹较宽，并且跟导线相比，引入较小的寄生电感和电阻。
这些类的器件是几毫米的。为了将器件厚度减少至约1.5mm，另一最近引入的功率MOSFET组件通过提供具有组件垫的引线框架而避免了连接夹和导线粘结，且其中组件垫针对功率芯片分为两部分，其中在一个芯片侧上具有第一和第二端以及在相反芯片侧上具有第三端。芯片是倒装安装(使用金属凸块或者由注射器分配的焊膏)在引线框架垫上，以致第一端接触一个垫部分，并且第二端接触另一垫部分。这两个引线框架部分具有弯曲边沿，以致，在倒装安装后，边沿变得与第三端共面；所有的三个MOSFET端均可以这样附接至印刷电路板(PCB)。在这样的附接后，引线框架垫远离PCB，但是由于其分成了作为两个管芯端的两个部分，所以热沉不能附接于垫。
在又一最近引入的功率MOSFET封装中，引线框架具有分成两部分的平垫，其可以附接至PCB。功率芯片的第一和第二端附接到这些垫部分。远离引线框架垫的第三芯片端与金属夹接触，其具有朝向引线框架的引线弯曲的边沿，从而允许所有的三个管芯端均被安装在PCB上。这些夹是由金属形成，其足够厚以允许热沉附接到夹以用于冷却第三芯片端。
另一最近提出的功率MOSFET封装，通过无引线粘结或夹的封装结构，将器件厚度减小至1.0至1.5mm。该结构需要引线框架垫是半刻蚀的以形成较厚和较薄的部分。这意味着，引线框架不能被冲压。在芯片装配工艺中，垫的共面侧是面向下的。作为其他需求，需要研发特殊的倒装芯片设备，其可以从底面附接芯片；FET源极附接到较厚的垫部分，并且FET栅极附接至较薄的垫部分。在封罩工艺中，封装化合物覆盖了这个较薄的部分。另外，分离件部分需要使得封装端与FET漏极在一个水平上，并且必须沉积额外的金属层并且图案化以模仿标准QFN占地面积。
发明内容
申请人认识到，在市场中种类繁多的手持式、笔记本式、汽车的和医药的产品中功率转换器的广泛应用，需要MOS场效应晶体管(FETS)的封装，其不仅允许直接应用至已建立的印刷电路板(PCB)，还具有远小于传统1.5mm的厚度。此外，功率FETS应该提供包括接近理论最大值的电流、功率和速度的性能。申请人看到了，从非常接近接头/结(junction)的两个表面冷却晶体管封装将会降低操作接头温度，以致可以处理更高的电流；通过减少寄生电阻和电感，降低导通损失将会减小功率损失，因此可以增加效率；以及，降低封装相关电容将会减少转换损失，因此提高了速度性能。
申请人解决了减小高功率MOSFET封装的整体厚度的问题，这是因为当他们发现约0.3mm厚度的封装可以获得作为工业可行性线性厚度0.125mm的夹和工业可行生线性厚度0.125mm的引线框架的总和，其中引线框架具有垫，该垫具有为了附接与线性引线框架厚度共面的芯片而减小的厚度。金属引线框架和夹暴露在相反封装面上，接近接头的双重冷却将使得电流处理增加至约35A。申请人进一步发现，新的组件允许没有弯曲边沿的夹，从而降低了寄生电阻和电感，从而增加了效率和速度。作为意外的得益，申请人发现，没有边缘的夹降低了晶体管“关-开-关”操作的常规“扰动”。
在示意性优选实施例中，功率FET封装具有6mm的长度和5mm的宽度。第一FET端是源极，第二端是漏极，以及第三端是栅极。漏极附接到引线框架垫，源极和栅极附接到夹。所有的三个端在具有标准QFN占地面积的一个封装侧面上并且可以附接至PCB；在相反封装表面上的引线框架垫的暴露金属可以用于附接热沉。封装的厚度由引线框架的线性厚度和夹的线性厚度之和构成，总共0.3mm，包括粘结材料。由于热沉附接到夹并且引线框架垫也被冷却，FET封装能够处理约25至40A的电流。
引线框架垫具有比引线框架线性厚度(第一线性厚度)更小的厚度；在将芯片附接到垫之后，芯片和垫的总共厚度等于第一线性厚度。当制造与原始第一线性厚度相比厚度减小的垫时，围绕垫的至少一个周边保留原始线性厚度的边沿可以具有技术优势的，因为这样的边沿利于组件工艺。例如，围绕所有四个垫侧的边沿作为容纳芯片附接材料(例如焊锡)的蔓延的止挡。
示意性功率FET封装的制造开始于选择第一线性厚度的引线框架。最小的商业可获得的厚度是0.125mm。可以通过部分刻蚀引线框架的一部分来获得减小厚度的垫(例如0.075mm)；然而，引线框架的一个表面保持共面，并且这样针对封装端提供了一个平面。然后，FET芯片附接到垫；在示意性示例中引用的，FET漏极附接到垫。附接材料包括导电胶粘剂和焊锡。如表述的，在芯片附接后，芯片和垫具有第一线性厚度。FET的源极和栅极通过夹连接到封装端，源极通过第二线性厚度的夹并且栅极通过厚度减小(相对第二厚度减小)的夹。与传统的使用具有弯曲边沿和无刻蚀垫的功率FET封装相比，这些夹都没有弯曲边沿，并且因此减少了20至30％的寄生电阻和电感，并且减少了与封装有关的电容。因此，功率和转换损失减少了，并且效率和速度提高了。
在后面的封罩工艺中，前面提到的减小厚度的夹被封罩化合物所覆盖，同时较厚夹的表面留下用于附接适于直接冷却由FET操作电流引起的热的热沉。
附图说明
图1示出了在引线框架和夹间装配的并且封罩在透明封装材料中的功率场效应晶体管的顶视图。
图2勾画了沿图1中所示的线的图1的封装FET的截面。
图3图示了沿图1中所示的线的图1的封装FET的截面。
图4A勾画了沿图1中线记号图2的图1的封装FET的另一实施例的截面。
图4B是在图4A中实施例中采用的引线框架的透视图，示出了刻蚀进引线框架垫内的腔。
图5是图1的FET示意性电路图，其强化了寄生电阻和电感。
具体实施方式
图1、图2和图3图示了发明的示意性实施例，半导体功率芯片140的封装预计安装在例如母板的衬底上。典型地，封装用于封装功率场效应晶体管(FET)、功率开关、功率转换器，其处理大电流(例如，25至40A)并且因此产生显著的热。芯片140具有厚度140a；例如示出的，厚度140a优选约0.05mm；在其他实施例中，芯片140可以更厚些或者更薄些。FET具有第一、第二和第三端。通常标注为100的功率器件，以顶视(图1)和截面(图2和3)示出。图1中的剖面线指示截面的位置。为清楚目的，图1的顶视图在假定封装化合物130是透明的情况下示出；在实际中，为了保护半导体芯片抵抗可见波长状态下的光，绝缘化合物必须是不透明的(例如黑色环氧基模制化合物)。
图2和3示出了器件100的封装具有平的顶表面101、平的底表面102、与顶和底表面成直角的侧表面103以及与器件的横向尺寸相比要小的厚度104。优选厚度范围是0.3mm或者更小，例如在0.26和0.28mm之间。在顶表面101上露出的大金属区域111属于标识为110的平板。于此，板110被称为夹；通常，它是平的，并且具体地在周边的任何部分处都没有弯曲，然而可以包括少量的凹槽、沟槽或者类似的有意识的表面不平坦(优选由部分刻蚀产生的)，以用于改进夹和封罩化合物间的粘结，或者用于抑制在将夹110附接至引线150的附接步骤中例如焊锡的粘结材料170的扩散。
通过金属区域111，夹110可以将显著量的热耗散到环境中；在功率芯片140的操作过程中，产生热能量，其中该功率芯片140附接至引线框架垫151的表面152。当热沉附接到金属区域111时，可以大大增加热耗散。为了便于附接热沉，提供具有可焊接冶金制备的金属区域111是有利的，例如提供锡或镍层。夹110优选由铜或铜合金形成；其他可替换物包括铁-镍合金(例如合金42)、铝和KovarTM。夹厚度110a优选介于约0.12和0.13mm之间，更优选0.125mm，但是也可以更薄或更厚。于此，板厚度110a被称为第二线性厚度110a。
如于此定义的，板的线性厚度指的是板的两个相反表面间的最大厚度。这个定义适用于平面板(所谓平板)和曲(或弯曲)板。
如图1、图2和图3进一步示出的，具有通常QFN型配置的金属引线框架具有引线150和160以及平器件组件垫(DAP)151。在示例中示出的，垫151具有矩形形状并且平行于矩形垫151的一个或更多个侧面来设置引线150和160。应该意识到的是，其他实施例可以具有不同的引线配置，特别对于特定热分配需求而言。垫151的表面区域153和引线150和160的表面154暴露在封装表面102上并且与表面102共面。
引线框架的优选制造方法是通过在低成本批量过程中在初始金属板上冲压。优选，引线框架的占地面积(footprint)是标准QFN/SON占地面积，因此之后不需要额外的矫正金属层被沉积且图案化为模仿标准QFN占地面积。
如图2所示，引线框架具有厚度150a；其在此被称为第一线性厚度150a。引线框架厚度150a优选在约0.120和0.130mm之间，更优选是0.125mm，但是也可以更薄或更厚。引线框架优选由铜或铜合金形成；其他可替换物包括铁-镍合金(例如合金42)、铝和KovarTM。图2和图3进一步指示了具有厚度151a的垫151，其与厚度150a相比减小了。制造被减小厚度的优选的方法是对引线框架的部分刻蚀。选择被减小厚度151a的值，以致厚度151a、附接到垫151的半导体功率芯片140的厚度140a以及粘结材料的总和等于引线框架的厚度150a。
对于将芯片140组装到垫151上的工艺步骤，与引线表面154共面的垫表面153面向下。在芯片组装过程中，不需要特殊的倒装芯片设备来将芯片面朝上地附接到垫表面152上。
在器件100的示意性实施例中，附接到垫151的FET140的第一端是晶体管漏极。第二端(晶体管的源极)以及第三端(晶体管的栅极)远离垫。源极连接到夹110，其依次连接到封装端150(应该提到的是，夹110与端150的连接，就不需要夹在电功能中仅仅为连接热沉来服务)。栅极连接到夹112，其依次连接封装端160。与夹110的第二线性厚度110a相比，夹112具有减小的厚度112a，其被称为第三线性厚度。由于减小的厚度112a的原因，夹112可以在封罩工艺中由封装化合物130覆盖。因此，仅仅夹110的表面111保持未封罩并且因此用于将热沉附接到夹110；这个热沉现在可以在器件100的整个表面101上延伸，以最大化热沉的尺寸，并且因此最大化了冷却效果。
如图1、图2和图3图示，器件100的结构使得封装厚度104是引线框架的第一线性厚度150a和夹110的第二线性厚度110a再加上任何粘结材料170的和。如陈述的，这个和产生约0.3mm的厚度104。粘结材料170选自包括焊锡、导电粘结胶、z轴线导体、碳管和石墨烯所构成的组。
当引线框架垫151的减小厚度151a被限制成用于附接FET芯片140(器件组件垫，DAP)的垫部分，同时垫的剩余部分保留第一线性厚度150a，则这些陈述仍然有效。如图4A和图4B中示例，沿DAP(402)的一个或多个周边部分401可以保留第一线性厚度，形成DAP的边沿状边界。这样的边界有助于防止不希望的焊锡喷溅。如陈述的，在一个或多个周边段处带有边界的减小厚度的结构可通过部分刻蚀技术由原始引线框架制造。在图4A所示的截面中和如在图4B中的透视图中，引线框架垫呈现出包含DAP402，其好像是由边沿401围绕的空腔。在其他实施例中，边沿401可以仅仅沿着一个或两个或三个垫侧。
如图4A所示，在引线框架垫中刻蚀出空腔，以致FET芯片140可被浸入空腔中。然后，使用例如焊锡或导电粘结胶的粘结剂，将芯片140附接到空腔。如图2中所示，在将芯片底端附接到垫空腔(表面152)后，顶部芯片端是与边沿表面402共面的。边沿表面402和垫底部153之间的距离是引线框架第一线性厚度150a。如上面陈述的，第一线性厚度优选是0.125mm；夹110的第二线性厚度110a优选为0.125mm；以及粘结材料170(选自包括焊锡、导电粘结胶、z轴线导体、碳管和石墨烯所构成的组)优选约0.05mm。总之，功率封装具有优选0.3mm的优选厚度。如图4A中进一步所示，将顶部芯片端互连至封装端的夹110没有与夹平面成角度的边沿弯曲。与传统的具有弯曲边沿的夹相比，使用平夹将寄生电阻和电感降低了20至30％(见下)。没有弯曲边沿进一步将晶体管关-开-关扰动减少了约50％。
封装材料130封罩被组装在引线框架上的晶体管芯片，以致在器件100的一侧上共面垫表面153和封装端表面154保持未被封罩，并且在相反的器件表面上夹表面111保持未被封罩。如表述的，两个表面均可用于冷却和附接热沉。封装材料埋住第三线性厚度的金属板112。
图5的示意性电路图概括了电子元件，其对功率FET器件的性能改进做出贡献，这基于图1、图2和图3中表述的封装结构中的最小化元件。由于图仅仅考虑封装贡献，所以通常这样的模型被称为无管芯电阻/无管芯电感模型。从电性能的角度看，主要的有益贡献由夹110和引线框架垫151产生，其中夹110是平夹且没有传统的弯曲边沿的延展，引线框架垫151与第一线性引线框架厚度相比具有减小的垫厚度。与传统功率FET封装相比，可以在较高性能、较高速度和较高电流方面表现出性能改进。
功率FET器件的性能可以通过降低功率损耗而提高：
效率＝输出功率/输入功率
＝输出功率/(输出功率-功率损耗)
功率损耗由此确定：
功率损耗＝导电损耗+转换损耗；
功率损耗＝I2R+PSW；
其中I＝电流，R包括固有和寄生电阻以及固有和寄生电感。对转换损耗PSW有贡献的是芯片内的寄生电容和封装内的寄生电阻R，该寄生电容减少了移动电荷，该寄生电阻R延长了对芯片电容充电的时间。通过沿着三个途径进行来降低功率损耗并且因此提高效率：通过降低FET源极的寄生电阻和电感降低导电损耗；通过降低FET漏极的寄生电阻而降低器件水平的转换损失和因此的热生成；以及提高板水平的热耗散。
功率FET的速度的特征在于晶体管从“关”到“开”操作以及回到“关”的转换。当可通过减小封装电阻而减少对芯片电容的充电时间时，FET可更快转换。最后，在达到接头温度限制之前允许通过FET的电流，可以通过改进FET接头冷却效率而增加。如上面表述的，由于图1、图2和图3中的器件100的厚度原因，通过器件100的两侧上的热沉，可以获得有效的双重冷却。
在图5的电路图中，封装端是给出标识的，其与图1至3中的相关标识是一样的：漏极端垫151(作为第一FET端)，源极端垫150(作为第二FET端)，以及栅极端垫160(作为第三FET端)。由于避免了具有弯曲边沿的传统细长夹，通常约0.4nH的寄生源极电感LS(标识501)被降低了约20％至30％。由于避免了具有弯曲边沿的传统细长夹，通常约0.2mΩ的寄生源极电阻RS(502)被降低了约20％至30％。由于基于引线框架垫的减小厚度减小了引线框架的影响，所以寄生漏极电感LD(标识511)实际可忽略。由于基于引线框架垫的减小厚度减小了引线框架的影响，所以寄生漏极电阻RD(标识512)实际可忽略，其通常约0.001mΩ。通过使用无边沿夹和减小厚度的垫，寄生栅极电感LG(标识521)(约1.54nH)不受影响。通过使用无边沿夹和减小厚度的垫，寄生栅极电阻RG(标识522)(约22mΩ)不受影响。
如图1至图4A中所示的器件100的模制封装结构，允许具有附接到夹110的第一热沉和附接到相反封装表面上的引线框架垫151的第二热沉的双路冷却操作。FET接头的有效冷却允许在接头温度到达150℃之前流过25至40A的电流。
虽然本发明参考说明性的实施例进行表述，但是说明不意指解释为限制的意思。说明性实施例的各种改变和组合，以及发明的其他实施例，在参考说明书的基础上，对于本领域技术人员来说是显而易见的。作为示例，发明不仅仅用作场效应晶体管中，还用在其他适合的功率晶体管中。
作为其他示例，通过连接夹到热沉，优选通过焊锡，以及同时连接引线框架垫到冷却的衬底或者热沉，电源模块的高电流容量可进一步扩展，并且效率可进一步增加。在这样的配置中，模块可以从两个表面散发热到热沉，并且在达到150℃的限制接头温度之前，晶体管接头可以处理更大电流。
因此，意指附加的权利要求包含任何这样的改进和实施例。

Claims (12)

1.一种场效应晶体管封装，包括：
具有第一线性厚度的引线框架，该引线框架具有减小厚度的垫；
附接到所述垫的场效应晶体管芯片，该晶体管具有与所述垫接触的第一端以及远离所述垫的第二和第三端；
连接所述第二晶体管端至封装端的具有第二线性厚度的金属板，以及连接所述第三晶体管端至封装端的具有第三线性厚度的金属板；以及
所述第一和第二线性厚度的总和构成封装厚度。
2.根据权利要求1所述的封装，其中所述封装厚度等于或小于0.3mm。
3.根据权利要求2所述的封装，进一步包括沿所述垫周缘的至少一部分的边沿，其中边沿和垫的厚度等于所述第一线性厚度。
4.根据权利要求3所述的封装，进一步包括封装材料，其封罩被附接到所述垫的所述晶体管芯片，以致与所述芯片相反的所述垫表面和引线表面保持未封罩。
5.根据权利要求4所述的封装，进一步包括未封罩与附接的第二晶体管端相反的板表面。
6.根据权利要求1所述的封装，其中所述第三线性厚度比所述第二线性厚度小。
7.根据权利要求6所述的封装，其中所述封装材料封罩具有所述第三线性厚度的板。
8.根据权利要求7所述的封装，进一步包括与附接的第二晶体管端相反地附接到未封罩板表面的第一热沉。
9.根据权利要求8的封装，进一步包括与所述芯片相反地附接到未封罩垫表面的第二热沉。
10.根据权利要求7所述的封装，其中所述封装端具有标准QFN占地面积。
11.根据权利要求5所述的封装，其中所述未封罩垫和板表面是共面的。
12.根据权利要求1所述的封装，其中所述第一晶体管端是漏极，所述第二端是源极，以及所述第三端是栅极。
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