CN214477437U - 双电晶体的封装结构 - Google Patents
双电晶体的封装结构 Download PDFInfo
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Abstract
一种双电晶体的封装结构,包括有一基板,其内部设有第一、第二、第三及第四导电部,其中第一导电部延伸至基板正面形成有一第一接点,且延伸至基板背面形成有一漏极输出接点;第二导电部延伸至基板正面形成有一第二接点,且延伸至基板正面形成有一源极输出接点;第三导电部延伸至基板正面形成有一第三接点,且延伸至基板正面形成有一第四接点。一第一电晶体以其漏极连接第一接点,栅极连接第二接点,源极连接第三接点。一第二电晶体以其源极连接源极输出接点,栅极连接栅极输出接点,漏极连接第四接点。本实用新型通过基板内部的导通电路设计以串接两个电晶体,进而减少电晶体之间的打线连接以减少寄生电感,亦可帮助散热,确保电晶体的工作效率。
Description
技术领域
本实用新型与半导体元件封装结构有关,尤指一种双电晶体的封装结构。
背景技术
相较于传统的硅质金氧半场效电晶体(Si metal oxide semiconductor fieldeffect transistor;Si MOSFET),氮化镓高电子迁移率电晶体(GaN high electronmobility transistor;GaN HEMT)拥有较宽的能隙、较大的崩溃电压以及较高的载子迁移率,可在较快的切换速度下实现较低的导通电阻。然而,氮化镓高电子迁移率电晶体先天是属于空乏型操作的元件,为了配合其他增强型操作的电子元件进行应用,一种串迭式(cascode)电晶体架构即被提出。
串迭式电晶体是由一氮化镓高电子迁移率电晶体与一场效电晶体通过打线接合(wire bonding)技术串接而形成。通过将场效电晶体设置于串迭式电晶体的栅极端,可使串迭式电晶体成为增强型操作的电子元件并同时拥有氮化镓高电子迁移率电晶体所具有的优点。
然而,通过打线接合技术将氮化镓高电子迁移率电晶体与一场效电晶体进行串接会产生一些问题。第一,连接导线会造成额外的寄生电感(parasitic inductance),进而限制元件的频率响应,导致元件特性变差。第二,若以打线接合技术实现串迭式电晶体,场效电晶体必须以平面的架构来实现,而平面架构相较于垂直架构制作成本较高。第三,为了避免氮化镓高电子迁移率电晶体的漏极与其他电极之间发生重叠,必须增加氮化镓高电子迁移率电晶体本身的钝化层(passivation layer)的厚度,将导致制造成本提高。
有鉴于此,如何改进上述问题即为本实用新型所欲解决的首要课题。
实用新型内容
本实用新型的主要目的在于提供一种双电晶体的封装结构,其通过基板内部的导通电路设计以串接两个电晶体,进而减少电晶体之间的打线连接以减少寄生电感,此外亦可帮助散热,达到确保电晶体工作效率的功效。
为达前述的目的,本实用新型提供一种双电晶体的封装结构,其包括有:
一基板,其定义具有一正面及一背面;
一设于该基板内部的第一导电部,其一端延伸至该正面形成有一第一接点,且另一端延伸至该背面形成有一漏极输出接点;
一设于该基板内部的第二导电部,其一端延伸至该正面形成有一第二接点,且另一端延伸至该正面形成有一源极输出接点;
一设于该基板内部的第三导电部,其一端延伸至该正面形成有一第三接点,且另一端延伸至该正面形成有一第四接点;
一设于该基板正面的第四导电部,其形成有一栅极输出接点;
一设于该基板正面的第一电晶体,其面对该正面的一侧具有一第一漏极、一第一栅极及一第一源极,其中该第一漏极连接该第一接点,该第一栅极连接该第二接点,该第一源极连接该第三接点;
一设于该基板正面的第二电晶体,其面对该正面的一侧具有一第二漏极,且背对该正面的一侧具有一第二栅极及一第二源极,其中该第二源极连接该源极输出接点,该第二栅极连接该栅极输出接点,该第二漏极连接该第四接点。
较佳地,该第一漏极与该第一接点之间、该第一栅极与该第二接点之间、该第一源极与该第三接点之间、该第二漏极与该第四接点之间分别以可导电的固晶胶固定连接。
较佳地,该第一电晶体及该第二电晶体分别以一封装胶密封。
更进一步地包括有一导线架,该导线架具有一可导电的座体、一与该座体电性连接的第一引脚、一与该座体分离的第二引脚及一与该座体分离的第三引脚,该基板设于该座体上,且以该漏极输出接点直接电性连接该座体,以该栅极输出接点通过导线电性连接该第二引脚,以该源极输出接点通过导线电性连接该第三引脚。
上述该第一电晶体为氮化镓高电子迁移率电晶体,该第二电晶体为金属氧化物半导体场效电晶体。上述该氮化镓高电子迁移率电晶体包括有依序相叠的一第一氮化镓窄禁带层、一氮化铝镓宽禁带层、一第二氮化镓窄禁带层、一缓冲层、一基层及一背镀金属层。
本实用新型的优点在于:
本实用新型提供的双电晶体的封装结构,其通过基板内部的导通电路设计以串接两个电晶体,进而减少电晶体之间的打线连接以减少寄生电感,此外亦可帮助散热,达到确保电晶体工作效率的功效。
本实用新型的上述目的与优点,不难从以下所选用实施例的详细说明与附图中获得深入了解。
附图说明
图1、2为本实用新型的构造示意图;
图3为本实用新型氮化镓高电子迁移率电晶体的构造示意图;
图4为本实用新型组装于导线架的构造示意图。
具体实施方式
请参阅图1、2,所示为本实用新型提供的双电晶体的封装结构,包括有一以氮化铝或氧化铝为材质的基板1,其具有高绝缘性及高导热性。定义该基板1具有一正面11及一背面12,内部设有三个彼此不相连通的通道13、14、15,其中通道13在该基板1的正面11及背面12分别形成出口,通道14、15在该基板1的正面11形成出口。
上述各通道13、14、15中分别以导电材料填充而形成有一第一导电部21、一第二导电部22及一第三导电部23,其中该第一导电部21的一端延伸至该正面11形成有一第一接点211,且另一端延伸至该背面12形成有一漏极输出接点212。该第二导电部22的一端延伸至该正面11形成有一第二接点221,另一端延伸至该正面11形成有一源极输出接点222。该第三导电部23的一端延伸至该正面11形成有一第三接点231,且另一端延伸至该正面11形成有一第四接点232。此外,该基板1的正面11上以导电材料铺设有一第四导电部24,该第四导电部24形成有一栅极输出接点241。
该基板1的正面11上设有一第一电晶体3及一第二电晶体4,再以一封装胶16密封,该封装胶16可为黑色硅胶或黑色环氧树脂。于本实施例中更进一步地界定该第一电晶体3为氮化镓高电子迁移率电晶体(GaN HEMT),该第二电晶体4为金属氧化物半导体场效电晶体(MOSFET)。如图3所示,上述该氮化镓高电子迁移率电晶体包括有依序相叠的一第一氮化镓窄禁带层34、一氮化铝镓宽禁带层35、一第二氮化镓窄禁带层36、一缓冲层37、一基层38及一背镀金属层39,其中该背镀金属层39可以反射光线,以免电晶体的运作效能受到影响。
该第一电晶体3面对该正面11的一侧具有一第一漏极31、一第一栅极32及一第一源极33,其中该第一漏极31连接该第一接点211,该第一栅极32连接该第二接点221,该第一源极33连接该第三接点231。该第二电晶体4面对该正面11的一侧具有一第二漏极41,且背对该正面11的一侧具有一第二栅极42及一第二源极43,其中该第二源极43连接该源极输出接点222,该第二栅极42连接该栅极输出接点241,该第二漏极41连接该第四接点232。
上述第一漏极31与第一接点211之间、第一栅极32与第二接点221之间、第一源极33与第三接点231之间、第二漏极41与第四接点232之间分别以可导电的固晶胶51固定连接;第二源极43与源极输出接点222之间、第二栅极42与栅极输出接点241之间是以导线52连接。上述该固晶胶51可为锡、金、金锡或银胶。
依上述方式将该第一电晶体3与该第二电晶体4组装到该基板1上后,可再将其组装到一导线架上。如图4所示,该导线架6具有一可导电的座体61、一第一引脚62、一第二引脚63及一第三引脚64,其中该第一引脚62是由该座体61一体伸出而与该座体61电性连接,而该第二引脚63及该第三引脚64与该座体61分离。该基板1以其背面靠合于该座体61上,并以该漏极输出接点直接电性连接该座体61,且以该栅极输出接点241通过导线53电性连接该第二引脚63,以该源极输出接点222通过导线54电性连接该第三引脚64。
通过上述结构的配置,该第一电晶体3与该第二电晶体4可通过该第一导电部21、该第二导电部22、该第三导电部23及该第四导电部24电性连接而构成串迭式(cascode)的电晶体架构,其中由于各导电部21、22、23、24是与该基板1构成一个整体,使该第一电晶体3与该第二电晶体4只要在各极的预定位置上简单地靠合该基板1,并以固晶胶固定即可完成组装,除了该第二电晶体4的第二栅极42与第二源极43由于位置因素仍须使用导线连接之外,其他部分无须通过打线连接,据此可减少寄生电感的发生。
此外,由于该第一导电部21、该第二导电部22、该第三导电部23及该第四导电部24与该基板1构成一个整体,而氮化铝基板1具有绝缘性高及导热性高的特性,使该第一电晶体3与该第二电晶体4在工作时所产生的热可被该基板1迅速导出散热,避免局部累积而影响效能。
只是以上实施例的揭示仅用以说明本实用新型,并非用以限制本实用新型,举凡等效元件的置换仍应隶属本实用新型的范畴。
综上所述,可使本领域技术人员明了本实用新型确可达成前述目的,实已符合专利法的规定,爰依法提出申请。
Claims (6)
1.一种双电晶体的封装结构,其特征在于,其包括有:
一基板,其定义具有一正面及一背面;
一设于该基板内部的第一导电部,其一端延伸至该正面形成有一第一接点,且另一端延伸至该背面形成有一漏极输出接点;
一设于该基板内部的第二导电部,其一端延伸至该正面形成有一第二接点,且另一端延伸至该正面形成有一源极输出接点;
一设于该基板内部的第三导电部,其一端延伸至该正面形成有一第三接点,且另一端延伸至该正面形成有一第四接点;
一设于该基板正面的第四导电部,其形成有一栅极输出接点;
一设于该基板正面的第一电晶体,其面对该正面的一侧具有一第一漏极、一第一栅极及一第一源极,其中该第一漏极连接该第一接点,该第一栅极连接该第二接点,该第一源极连接该第三接点;
一设于该基板正面的第二电晶体,其面对该正面的一侧具有一第二漏极,且背对该正面的一侧具有一第二栅极及一第二源极,其中该第二源极连接该源极输出接点,该第二栅极连接该栅极输出接点,该第二漏极连接该第四接点。
2.如权利要求1所述的双电晶体的封装结构,其特征在于,该第一漏极与该第一接点之间、该第一栅极与该第二接点之间、该第一源极与该第三接点之间、该第二漏极与该第四接点之间分别以可导电的固晶胶固定连接。
3.如权利要求1所述的双电晶体的封装结构,其特征在于,该第一电晶体及该第二电晶体分别以一封装胶密封。
4.如权利要求1所述的双电晶体的封装结构,其特征在于,更包括有一导线架,该导线架具有一可导电的座体、一与该座体电性连接的第一引脚、一与该座体分离的第二引脚及一与该座体分离的第三引脚,该基板设于该座体上,且以该漏极输出接点直接电性连接该座体,以该栅极输出接点通过导线电性连接该第二引脚,以该源极输出接点通过导线电性连接该第三引脚。
5.如权利要求1所述的双电晶体的封装结构,其特征在于,该第一电晶体为氮化镓高电子迁移率电晶体,该第二电晶体为金属氧化物半导体场效电晶体。
6.如权利要求5所述的双电晶体的封装结构,其特征在于,该氮化镓高电子迁移率电晶体包括有依序相叠的一第一氮化镓窄禁带层、一氮化铝镓宽禁带层、一第二氮化镓窄禁带层、一缓冲层、一基层及一背镀金属层。
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