CN215933588U - Full-bridge semiconductor device - Google Patents
Full-bridge semiconductor device Download PDFInfo
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- CN215933588U CN215933588U CN202122302799.8U CN202122302799U CN215933588U CN 215933588 U CN215933588 U CN 215933588U CN 202122302799 U CN202122302799 U CN 202122302799U CN 215933588 U CN215933588 U CN 215933588U
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- chip
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- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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Abstract
The utility model discloses a full-bridge semiconductor device, comprising: the first chip substrate and the second chip substrate are wrapped in the epoxy packaging body, and one end of the first pin and one end of the second pin extend out of the epoxy packaging body; the area of the supporting parts is smaller than that of the lower surface of the chip, and each supporting part is positioned right below the central area of the corresponding chip. The utility model can reduce the position offset and rotation of the chip in the high-temperature welding process, improve the position precision of chip welding and ensure the position precision and connection stability of the chip, thereby improving the overall yield and quality of products.
Description
Technical Field
The utility model relates to the technical field of semiconductor packaging, in particular to a full-bridge type semiconductor device.
Background
In recent years, the trend of miniaturization and light weight development of power supply products is more and more remarkable, and higher requirements are also put forward on the power density of patch type rectifier bridge products. The existing packaging structure is limited by the inner space of a product, a chip with a larger size is difficult to package, and the improvement of the power density of a rectifier bridge product is limited.
The existing packaging structure mainly has the following defects: firstly, when a large-size chip is packaged, the distance between the chips is insufficient, and the risk of product failure caused by collision of the chips is high; secondly, the position deviation of the chip in the high-temperature welding process is large, and under the condition that the chip spacing is insufficient, the risk that the chips collide together is increased.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a full-bridge semiconductor device which can reduce the position deviation and rotation of a chip in the high-temperature welding process, improve the position precision of chip welding, ensure the position precision and the connection stability of the chip and further improve the overall yield and quality of products.
In order to achieve the purpose, the utility model adopts the technical scheme that: a full bridge semiconductor device comprising: the first chip substrate and the second chip substrate are wrapped in the epoxy packaging body, and one end of the first chip substrate extend out of the epoxy packaging body;
the junction in second support region and second lead wire district is located and has a breach near a first portion of bending side edge, the setting is pressed close to with first portion of bending on the horizontal plane to the breach, the region that is used for being connected with the chip on first chip base plate, the second chip base plate separately is provided with a supporting part, the area of supporting part is less than the area and every of chip lower surface the supporting part is located under corresponding chip central zone.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the side surface at the edge of the support part is a slope.
2. In the above scheme, the notch is a semicircular notch.
3. In the above scheme, the notch is located below the chip on the second support area.
4. In the above scheme, one end of each of the first lead region and the second lead region, which is far away from the first support region and the second support region, extends outward from the same side of the epoxy package body.
5. In the above scheme, the first chip substrate and the second chip substrate are copper substrates.
Due to the application of the technical scheme, compared with the prior art, the utility model has the following advantages and effects:
1. according to the full-bridge semiconductor device, the two chip substrates which are close to each other in the horizontal direction are separated in the vertical direction through the arrangement of the first bending part on the second lead area, so that the chips can be arranged at the edge of the chip substrates and extend outwards from the edge of the chip substrates, the distance between multiple chips on the same chip substrate is increased without increasing the product structure, the product failure problem caused by collision between adjacent chips and between the chips and other chip substrates due to insufficient distance is avoided, and the overall processing yield and the product stability are improved; further, through the setting of pressing close to the breach of first portion of bending, avoid leading to second support area edge to produce because of first portion of bending and warp, and then lead to its upper chip slope, warpage or highly mismatch to arouse that chip and base plate connect or weld the not firm situation, guarantee the position accuracy of chip and the stability of connecting to improve holistic yield of product and quality.
2. According to the full-bridge semiconductor device, the areas, used for being connected with the chips, of the first chip substrate and the second chip substrate are respectively provided with the supporting parts, the areas of the supporting parts are smaller than the area of the lower surfaces of the chips, and each supporting part is positioned right below the central area of the corresponding chip, so that the position deviation and rotation of the chips in the high-temperature welding process can be reduced, the position accuracy of chip welding is improved, the connection strength between epoxy and the chips can be improved, and the stability of products is improved.
Drawings
FIG. 1 is a schematic structural diagram of a full-bridge semiconductor device according to the present invention;
FIG. 2 is a schematic view of a partial structure of a full bridge semiconductor device according to the present invention;
fig. 3 is a sectional view taken along line a-a in fig. 1.
In the above drawings: 1. an epoxy package; 2. a first chip substrate; 21. a first support region; 22. a first lead region; 3. a second chip substrate; 31. a second support region; 32. a second lead section; 4. a first pin; 5. a second pin; 6. a chip; 61. a first chip; 62. a second chip; 63. a third chip; 64. a fourth chip; 7. connecting sheets; 8. a first bending portion; 11. a support portion; 12. and (4) a notch.
Detailed Description
The utility model is further described with reference to the following figures and examples:
example 1: a full bridge semiconductor device comprising: the first chip substrate 2 and the second chip substrate 3 are wrapped in the epoxy package body 1, and the first pin 4 and the second pin 5 extend out of the epoxy package body 1 at one end, the first chip substrate 2 comprises a first support region 21 for connecting with at least two chips 6 and a first lead region 22 perpendicular to one end of the first support region 21, the second chip substrate 3 comprises a second support region 31 parallel to the first support region 21 and arranged at an interval, and a second lead region 32 perpendicular to one end of the second support region 31 and located at the outer side of one end of the first support region 21 far away from the first lead region 22, the joint of the second lead region 32 and the second support region 31 is provided with a first bending part 8, so that the upper surface of the second lead region 32 located at the outer side of the first support region 21 is lower than the lower surface of the first support region 21 in the vertical direction;
The side surface at the edge of the supporting part 11 is a slope; the ends of the first and second lead pads 22 and 32, which are far away from the first and second support pads 21 and 31, respectively, extend outward from the same side of the epoxy package 1.
Example 2: a full bridge semiconductor device comprising: the first chip substrate 2 and the second chip substrate 3 are wrapped in the epoxy package body 1, and the first pin 4 and the second pin 5 extend out of the epoxy package body 1 at one end, the first chip substrate 2 comprises a first support region 21 for connecting with at least two chips 6 and a first lead region 22 perpendicular to one end of the first support region 21, the second chip substrate 3 comprises a second support region 31 parallel to the first support region 21 and arranged at an interval, and a second lead region 32 perpendicular to one end of the second support region 31 and located at the outer side of one end of the first support region 21 far away from the first lead region 22, the joint of the second lead region 32 and the second support region 31 is provided with a first bending part 8, so that the upper surface of the second lead region 32 located at the outer side of the first support region 21 is lower than the lower surface of the first support region 21 in the vertical direction;
The notch 12 is a semicircular notch; the notch 12 is located below the chip 6 on the second support area 31; the first chip substrate 2 and the second chip substrate 3 are copper substrates.
When the full-bridge semiconductor device is adopted, the two chip substrates which are close to each other in the horizontal direction are spatially separated in the vertical direction through the arrangement of the first bending part on the second lead area, so that the chips can be arranged at the edge of the chip substrates and extend outwards from the edge of the chip substrates, the space between the multiple chips on the same chip substrate is increased while the product structure is not increased, the product failure problem caused by collision between the adjacent chips and between the chips and other chip substrates due to insufficient space is avoided, and the integral processing yield and the product stability are improved;
furthermore, through the arrangement of the notch close to the first bending part, the situation that the edge of the second supporting area is deformed due to the first bending part, so that the chip is inclined, warped or not matched in height to cause the virtual connection or the infirm welding of the chip and the substrate is avoided, the position precision and the connection stability of the chip are ensured, and the integral yield and quality of the product are improved;
in addition, the areas which are respectively used for being connected with the chip on the first chip substrate and the second chip substrate are provided with a supporting part, the area of each supporting part is smaller than that of the lower surface of the chip, and each supporting part is positioned under the central area of the corresponding chip, so that the position deviation and rotation of the chip in the high-temperature welding process can be reduced, the position accuracy of chip welding is improved, the connection strength between epoxy and the chip can be improved, and the stability of a product is improved.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (6)
1. A full bridge semiconductor device comprising: first chip base plate (2), second chip base plate (3) and one end of cladding in epoxy packaging body (1) are from first pin (4), second pin (5) that stretch out in epoxy packaging body (1), its characterized in that: the first chip substrate (2) comprises a first supporting area (21) used for being connected with at least two chips (6) and a first lead area (22) perpendicular to one end of the first supporting area (21), the second chip substrate (3) comprises a second supporting area (31) arranged in parallel with the first supporting area (21) at an interval and a second lead area (32) perpendicular to one end of the second supporting area (31) and located on the outer side of one end, far away from the first lead area (22), of the first supporting area (21), and a first bending part (8) is arranged at the connection position of the second lead area (32) and the second supporting area (31), so that the upper surface of the second lead area (32) located on the outer side of the first supporting area (21) is lower than the lower surface of the first supporting area (21) in the vertical direction;
second support region (31) and the junction of second lead wire district (32) and be located and have a breach (12) near first portion of bending (8) one side edge, setting is pressed close to with first portion of bending (8) in breach (12) on the horizontal plane, the region that is used for being connected with chip (6) on first chip base plate (2), second chip base plate (3) separately is provided with a supporting part (11), the area of supporting part (11) is less than the area and every of chip (6) lower surface supporting part (11) are located and correspond chip (6) central zone under.
2. The full bridge semiconductor device of claim 1, wherein: the side surface at the edge of the supporting part (11) is a slope surface.
3. The full bridge semiconductor device of claim 1, wherein: the notch (12) is a semicircular notch.
4. The full bridge semiconductor device of claim 1, wherein: the notch (12) is located below the chip (6) on the second support area (31).
5. The full bridge semiconductor device of claim 1, wherein: one ends of the first lead area (22) and the second lead area (32) far away from the first support area (21) and the second support area (31) respectively extend outwards from the same side of the epoxy packaging body (1).
6. The full bridge semiconductor device of claim 1, wherein: the first chip substrate (2) and the second chip substrate (3) are copper substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122302799.8U CN215933588U (en) | 2021-09-23 | 2021-09-23 | Full-bridge semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122302799.8U CN215933588U (en) | 2021-09-23 | 2021-09-23 | Full-bridge semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215933588U true CN215933588U (en) | 2022-03-01 |
Family
ID=80415520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122302799.8U Active CN215933588U (en) | 2021-09-23 | 2021-09-23 | Full-bridge semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215933588U (en) |
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2021
- 2021-09-23 CN CN202122302799.8U patent/CN215933588U/en active Active
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