CN215933592U - Semiconductor power device - Google Patents
Semiconductor power device Download PDFInfo
- Publication number
- CN215933592U CN215933592U CN202122304617.0U CN202122304617U CN215933592U CN 215933592 U CN215933592 U CN 215933592U CN 202122304617 U CN202122304617 U CN 202122304617U CN 215933592 U CN215933592 U CN 215933592U
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- Prior art keywords
- chip
- area
- supporting area
- lead
- packaging body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model discloses a semiconductor power device, comprising: cladding first chip base plate, second chip base plate and one end in the epoxy packaging body are from first pin, the second pin that stretches out in the epoxy packaging body, first chip base plate is including the first lead wire district that is arranged in the first supporting area and the first supporting area one end of perpendicular to be connected with at least two chips, second chip base plate includes the second supporting area and perpendicular to second supporting area one end that set up with first supporting area parallel interval and lies in first supporting area and keeps away from the second lead wire district in first lead wire district one end outside, the junction in second supporting area and second lead wire district is located and is close to first portion of bending side edge and has a breach, the breach is pressed close to the setting with first portion of bending on the horizontal plane. The utility model ensures the position precision and the connection stability of the chip, thereby improving the overall yield and quality of the product and further improving the overall processing yield.
Description
Technical Field
The utility model relates to the technical field of semiconductor packaging, in particular to a semiconductor power device.
Background
In recent years, the trend of miniaturization and light weight development of power supply products is more and more remarkable, and higher requirements are also put forward on the power density of patch type rectifier bridge products. The existing packaging structure is limited by the inner space of a product, a chip with a larger size is difficult to package, and the improvement of the power density of a rectifier bridge product is limited. The existing packaging structure mainly has the following defects: when packaging large-size chips, the chip spacing is not sufficient, and there is a risk that the chips collide together to cause product failure.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a semiconductor power device, which ensures the position precision and the connection stability of a chip, thereby improving the overall yield and quality of products and further improving the overall processing yield.
In order to achieve the purpose, the utility model adopts the technical scheme that: a semiconductor power device comprising: the first chip substrate, the second chip substrate and the first pin and the second pin are wrapped in the epoxy packaging body, one end of the first chip substrate extends out of the epoxy packaging body, the first chip substrate comprises a first supporting area and a first lead area, the first supporting area is used for being connected with at least two chips, the first lead area is perpendicular to one end of the first supporting area, the second chip substrate comprises a second supporting area and a second lead area, the second supporting area is parallel to the first supporting area and is arranged at an interval, one end of the second supporting area is perpendicular to one end of the second supporting area, the second lead area is located on the outer side, far away from one end of the first lead area, of the first supporting area, a first bending portion is arranged at the joint of the second lead area and the second supporting area, the upper surface of the second lead area, located on the outer side of the first supporting area, is lower than the lower surface of the first supporting area in the vertical direction, a gap is arranged at the joint of the second supporting area and the second lead area and located on the edge of the side close to the first bending portion, the notch and the first bending part are arranged on the horizontal plane in a close manner.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the notch is a semicircular notch.
2. In the above scheme, the notch is located below the chip on the second support area.
3. In the above solution, the first lead pad and the second lead pad have a second bending portion respectively near the edge region of the epoxy package, so that the lower surfaces of the first lead pad and the second lead pad extending out of the region of the epoxy package are flush with the lower surface of the epoxy package.
4. In the above scheme, interval is provided with first chip, second chip and this first chip, the respective positive pole of second chip and electrically conducts with first chip base plate on the upper surface of second chip base plate, interval is provided with third chip, fourth chip and this third chip, the respective negative pole of fourth chip and electrically conducts with second chip base plate on the upper surface of first chip base plate, the negative pole of first chip, the positive pole of third chip are connected through a connecting piece and the one end electricity that first pin is located the epoxy packaging body, the negative pole of second chip, the positive pole of fourth chip are connected through another connecting piece and the one end electricity that second pin is located the epoxy packaging body.
5. In the above scheme, the first chip substrate and the second chip substrate are copper substrates.
Due to the application of the technical scheme, compared with the prior art, the utility model has the following advantages and effects:
according to the semiconductor power device, the two chip substrates which are close to each other in the horizontal direction are separated in the vertical direction through the arrangement of the first bending part on the second lead area, so that the chips can be arranged at the edge of the chip substrates and extend outwards from the edge of the chip substrates, the distance between multiple chips on the same chip substrate is increased without increasing the product structure, the product failure problem caused by collision between adjacent chips and between the chips and other chip substrates due to insufficient distance is avoided, and the overall processing yield and the product stability are improved; further, through the setting of pressing close to the breach of first portion of bending, avoid leading to second support area edge to produce because of first portion of bending and warp, and then lead to its upper chip slope, warpage or highly mismatch to arouse that chip and base plate connect or weld the not firm situation, guarantee the position accuracy of chip and the stability of connecting to improve holistic yield of product and quality.
Drawings
FIG. 1 is a schematic structural diagram of a semiconductor power device according to the present invention;
fig. 2 is a sectional view taken along a-a in fig. 1 of the semiconductor power device of the present invention.
In the above drawings: 1. an epoxy package; 2. a first chip substrate; 21. a first support region; 22. a first lead region; 3. a second chip substrate; 31. a second support region; 32. a second lead section; 4. a first pin; 5. a second pin; 6. a chip; 61. a first chip; 62. a second chip; 63. a third chip; 64. a fourth chip; 7. connecting sheets; 8. a first bending portion; 10. A second bending portion; 12. and (4) a notch.
Detailed Description
The utility model is further described with reference to the following figures and examples:
example 1: a semiconductor power device comprising: a first chip substrate 2 and a second chip substrate 3 which are coated in the epoxy packaging body 1, and a first pin 4 and a second pin 5 which are extended from the epoxy packaging body 1 at one end, the first chip substrate 2 includes a first support region 21 for connecting at least two chips 6 and a first lead region 22 perpendicular to one end of the first support region 21, the second chip substrate 3 includes a second support region 31 spaced apart from and parallel to the first support region 21 and a second lead region 32 perpendicular to an end of the second support region 31 and located outside an end of the first support region 21 remote from the first lead region 22, the junction of the second lead pad 32 and the second support pad 31 has a first bend 8, so that the upper surface of the second lead region 32 located outside the first support region 21 is lower than the lower surface of the first support region 21 in the vertical direction, the difference in height between the upper and lower horizontal portions being 0.1 cm;
a notch 12 is arranged at the joint of the second support region 31 and the second lead region 32 and at the edge close to one side of the first bending part 8, the notch 12 and the first bending part 8 are arranged close to each other on the horizontal plane, and the notch 12 is a semicircular notch; the notch 12 is located below the chip 6 on the second support area 31;
the first chip 61 and the second chip 62 are disposed on the upper surface of the second chip substrate 3 at an interval, the positive electrodes of the first chip 61 and the second chip 62 are electrically conducted with the first chip substrate 2, the negative electrodes of the third chip 63 and the fourth chip 64 are disposed on the upper surface of the first chip substrate 2 at an interval, the negative electrodes of the first chip 61 and the positive electrodes of the third chip 63 are electrically conducted with the second chip substrate 3, the negative electrodes of the third chip 63 and the positive electrodes of the fourth chip 63 are electrically connected with one end of the first pins 4 in the epoxy package 1 through a connecting sheet 7, and the negative electrodes of the second chip 62 and the positive electrodes of the fourth chip 64 are electrically connected with one end of the second pins 5 in the epoxy package 1 through another connecting sheet 7.
Example 2: a semiconductor power device comprising: a first chip substrate 2 and a second chip substrate 3 which are coated in the epoxy packaging body 1, and a first pin 4 and a second pin 5 which are extended from the epoxy packaging body 1 at one end, the first chip substrate 2 includes a first support region 21 for connecting at least two chips 6 and a first lead region 22 perpendicular to one end of the first support region 21, the second chip substrate 3 includes a second support region 31 spaced apart from and parallel to the first support region 21 and a second lead region 32 perpendicular to an end of the second support region 31 and located outside an end of the first support region 21 remote from the first lead region 22, the junction of the second lead pad 32 and the second support pad 31 has a first bend 8, so that the upper surface of the second lead region 32 located outside the first support region 21 is lower than the lower surface of the first support region 21 in the vertical direction, the difference in height between the upper and lower horizontal portions being 0.1 cm;
the joint of the second support region 31 and the second lead region 32 and the edge near one side of the first bending portion 8 have a notch 12, and the notch 12 and the first bending portion 8 are arranged closely on the horizontal plane.
The first lead region 22 and the second lead region 32 have a downward second bending portion 10 near the edge region of the epoxy package 1, so that the lower surfaces of the first lead region 22 and the second lead region 32 extending out of the epoxy package 1 are flush with the lower surface of the epoxy package 1, and the height difference between the two sides of the second bending portion is 0.2 cm; the first chip substrate 2 and the second chip substrate 3 are copper substrates.
When the semiconductor power device is adopted, the two chip substrates which are close to each other in the horizontal direction are spatially separated in the vertical direction through the arrangement of the first bending part on the second lead area, so that the chips can be arranged at the edge of the chip substrates and extend outwards from the edge of the chip substrates, the distance between multiple chips on the same chip substrate is increased while the product structure is not increased, the product failure problem caused by collision between adjacent chips and between the chips and other chip substrates due to insufficient distance is avoided, and the integral processing yield and the product stability are improved;
further, through the setting of pressing close to the breach of first portion of bending, avoid leading to second support area edge to produce because of first portion of bending and warp, and then lead to its upper chip slope, warpage or highly mismatch to arouse that chip and base plate connect or weld the not firm situation, guarantee the position accuracy of chip and the stability of connecting to improve holistic yield of product and quality.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (6)
1. A semiconductor power device comprising: first chip base plate (2), second chip base plate (3) and one end of cladding in epoxy packaging body (1) are from first pin (4), second pin (5) that stretch out in epoxy packaging body (1), its characterized in that: the first chip substrate (2) comprises a first supporting area (21) used for being connected with at least two chips (6) and a first lead area (22) perpendicular to one end of the first supporting area (21), the second chip substrate (3) comprises a second supporting area (31) arranged in parallel with the first supporting area (21) at an interval and a second lead area (32) perpendicular to one end of the second supporting area (31) and located on the outer side of one end, far away from the first lead area (22), of the first supporting area (21), and a first bending part (8) is arranged at the connection position of the second lead area (32) and the second supporting area (31), so that the upper surface of the second lead area (32) located on the outer side of the first supporting area (21) is lower than the lower surface of the first supporting area (21) in the vertical direction;
the junction of second support region (31) and second lead wire district (32) is located and is close to first bending portion (8) one side edge and has a breach (12), breach (12) and first bending portion (8) are pressed close to the setting on the horizontal plane.
2. The semiconductor power device of claim 1, wherein: the notch (12) is a semicircular notch.
3. The semiconductor power device of claim 1, wherein: the notch (12) is located below the chip (6) on the second support area (31).
4. The semiconductor power device of claim 1, wherein: the first lead area (22) and the second lead area (32) are respectively provided with a downward second bending part (10) close to the edge area of the epoxy packaging body (1), so that the first lead area (22) and the second lead area (32) extend out of the lower surface of the area of the epoxy packaging body (1) and are flush with the lower surface of the epoxy packaging body (1).
5. The semiconductor power device of claim 1, wherein: a first chip (61) and a second chip (62) are arranged on the upper surface of the second chip substrate (3) at intervals, and the respective anodes of the first chip (61) and the second chip (62) are electrically conducted with the first chip substrate (2), a third chip (63) and a fourth chip (64) are arranged on the upper surface of the first chip substrate (2) at intervals, and the respective negative electrodes of the third chip (63) and the fourth chip (64) are electrically conducted with the second chip substrate (3), the negative electrode of the first chip (61) and the positive electrode of the third chip (63) are electrically connected with one end of the first pin (4) in the epoxy packaging body (1) through a connecting sheet (7), and the negative electrode of the second chip (62) and the positive electrode of the fourth chip (64) are electrically connected with one end, positioned in the epoxy packaging body (1), of the second pin (5) through another connecting sheet (7).
6. The semiconductor power device of claim 1, wherein: the first chip substrate (2) and the second chip substrate (3) are copper substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122304617.0U CN215933592U (en) | 2021-09-23 | 2021-09-23 | Semiconductor power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122304617.0U CN215933592U (en) | 2021-09-23 | 2021-09-23 | Semiconductor power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215933592U true CN215933592U (en) | 2022-03-01 |
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ID=80415628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122304617.0U Active CN215933592U (en) | 2021-09-23 | 2021-09-23 | Semiconductor power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215933592U (en) |
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2021
- 2021-09-23 CN CN202122304617.0U patent/CN215933592U/en active Active
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