CN215578518U - Power semiconductor paster packaging structure - Google Patents
Power semiconductor paster packaging structure Download PDFInfo
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- CN215578518U CN215578518U CN202121964372.8U CN202121964372U CN215578518U CN 215578518 U CN215578518 U CN 215578518U CN 202121964372 U CN202121964372 U CN 202121964372U CN 215578518 U CN215578518 U CN 215578518U
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Abstract
The utility model discloses a power semiconductor chip packaging structure which comprises an upper packaging shell, wherein an upper clamping cavity is formed in the upper packaging shell, a clamping strip is fixedly arranged at the position, close to the edge, of the lower surface of the upper packaging shell, a limiting groove is formed in the position, close to the edge, of the bottom surface of the upper clamping cavity, a heat dissipation plate is clamped and installed at the position, close to the bottom surface, of the inner part of the upper clamping cavity, a heat dissipation plate is fixedly installed on the upper surface of the heat dissipation plate, the heat dissipation plate is clamped and connected with the limiting groove, and a semiconductor main body is clamped and installed at the position, close to the inner part of the upper clamping cavity, of the lower surface of the heat dissipation plate. The power semiconductor chip packaging structure can solve the problems that the semiconductor chip packaging structure is generally formed by injection molding, the packaging mode is not easy to disassemble, and certain influence is caused on later-stage maintenance, and the power semiconductor chip packaging structure can also solve the problems that the heat dissipation effect is poor, and the service life of a semiconductor main body is easily shortened in the past.
Description
Technical Field
The utility model relates to the field of packaging structures, in particular to a power semiconductor patch packaging structure.
Background
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a function requirement to obtain an independent chip; the existing semiconductor chip packaging structure has certain defects when in use, if the existing semiconductor chip packaging structure is generally injection molded, the packaging mode is not easy to detach, certain influence is caused on later-stage maintenance, in addition, the heat dissipation effect of the existing semiconductor chip packaging structure is poor, and the service life of a chip is easily reduced for a long time.
SUMMERY OF THE UTILITY MODEL
The main objective of the present invention is to provide a power semiconductor chip package structure, which can effectively solve the problems in the background art.
In order to achieve the purpose, the utility model adopts the technical scheme that:
a power semiconductor chip packaging structure comprises an upper packaging shell, an upper clamping cavity is arranged in the upper packaging shell, the lower surface of the upper packaging shell is fixedly provided with a clamping strip near the edge, the bottom surface of the upper clamping cavity is provided with a limit groove near the edge, a heat dissipation plate is clamped and installed at the position close to the bottom surface inside the upper clamping cavity, a heat dissipation sheet is fixedly installed on the upper surface of the heat dissipation plate, the heat radiating fin is clamped and connected with the limiting groove, the lower surface of the heat radiating plate is positioned in the upper clamping cavity and is clamped and installed with a semiconductor body, the lower surface of the semiconductor main body is fixedly provided with a connecting contact, the lower surface of the semiconductor main body is welded with a bonding pad, the lower surface of the upper packaging shell is clamped with a lower packaging shell, a lower clamping cavity is formed in the lower packaging shell, and a clamping groove is formed in the position, close to the edge, of the upper surface of the lower packaging shell.
Preferably, the positions, close to the four corners, of the upper surface of the upper packaging shell are provided with a first screw hole, and the positions, close to the four corners, of the upper surface of the lower packaging shell are provided with a second screw hole.
Preferably, the upper surface of the bonding pad is provided with a limiting hole, and a welding leg is fixedly arranged at the position, far away from the upper port of the limiting hole, inside the limiting hole.
Preferably, the clamping strip is connected with the clamping groove in a clamping mode, and the heat dissipation plate, the semiconductor body and the bonding pad are limited by the upper clamping cavity and the lower clamping cavity.
Preferably, the connecting contact is inserted into the limiting hole, and the connecting contact is connected with the welding leg in a welding mode.
Preferably, a thin layer of heat dissipation silicone grease is coated on the contact position of the lower surface of the heat dissipation plate and the semiconductor body.
Compared with the prior art, the utility model has the following beneficial effects:
in the utility model, through the arrangement of the upper packaging shell and the lower packaging shell, when the lower packaging shell is bonded by glue, the lower packaging shell is clamped by the clamping groove and the clamping strip, and the glue is coated at the clamped position to complete the packaging of the equipment, and the clamping groove and the clamping strip are clamped to increase the clamping contact area of the glue with the clamping groove and the clamping strip, so that the upper packaging shell and the lower packaging shell are bonded more firmly, for a large-size semiconductor main body, the upper packaging shell and the lower packaging shell can be fixed by directly using a threaded connecting piece in a first screw hole and a second screw hole to complete the packaging of the semiconductor main body, thereby solving the problems that the packaging structure of a semiconductor paster is generally injection molded, the packaging mode is not easy to disassemble and has certain influence on later overhaul, put into in the last block chamber and the heating panel contact closely, with heat conduction to the heating panel on the semiconductor body to give off the external world by the fin, thereby it is poor to solve semiconductor paster packaging structure radiating effect, long this problem that reduces the life of semiconductor body easily in the past.
Drawings
Fig. 1 is a schematic overall structure diagram of a power semiconductor chip package structure according to the present invention;
fig. 2 is a schematic structural diagram of a power semiconductor chip package structure according to the present invention;
fig. 3 is a schematic diagram of a split structure of a power semiconductor chip package structure according to the present invention;
fig. 4 is an enlarged view of a portion a in fig. 3 of a power semiconductor chip package structure according to the present invention.
In the figure: 1. an upper package shell; 101. an upper clamping cavity; 102. a limiting groove; 103. a first screw hole; 104. clamping the strip; 2. a heat dissipation plate; 201. a heat sink; 3. a semiconductor body; 301. connecting the contacts; 4. a pad; 401. a limiting hole; 402. welding feet; 5. a lower package housing; 501. a lower clamping cavity; 502. a clamping groove; 503. and a second screw hole.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the utility model easy to understand, the utility model is further described with the specific embodiments.
As shown in fig. 1-4, a power semiconductor chip package structure comprises an upper package 1, an upper engaging cavity 101 is formed in the upper package 1, a engaging strip 104 is fixedly mounted on the lower surface of the upper package 1 near the edge, a limiting groove 102 is formed on the bottom surface of the upper engaging cavity 101 near the edge, a heat sink 2 is fixedly mounted in the upper engaging cavity 101 near the bottom, a heat sink 201 is fixedly mounted on the upper surface of the heat sink 2, the heat sink 201 is engaged with the limiting groove 102, a semiconductor body 3 is engaged with the lower surface of the heat sink 2 in the upper engaging cavity 101, a connecting contact 301 is fixedly mounted on the lower surface of the semiconductor body 3, a bonding pad 4 is welded on the lower surface of the semiconductor body 3, a lower package 5 is engaged with the lower package 1, a lower engaging cavity 501 is formed in the lower package 5, an engaging groove 502 is formed on the upper surface of the lower package 5 near the edge, clamping the heat dissipation plate 2 in the limiting groove 102 through the heat dissipation sheet 201, coating heat dissipation silicone grease on the upper surface of the semiconductor body 3, putting the semiconductor body into the upper clamping cavity 101 to be closely contacted with the heat dissipation plate 2, conducting heat on the semiconductor body 3 to the heat dissipation plate 2, and dissipating the heat to the outside through the heat dissipation sheet 201;
The positions, close to the four corners, of the upper surface of the upper packaging shell 1 are provided with a first screw hole 103, and the positions, close to the four corners, of the upper surface of the lower packaging shell 5 are provided with a second screw hole 503; the upper surface of the bonding pad 4 is provided with a limiting hole 401, and a welding leg 402 is fixedly arranged in the limiting hole 401 at a position far away from the upper port of the limiting hole 401; the clamping strip 104 is clamped and connected with the clamping groove 502, the heat dissipation plate 2, the semiconductor body 3 and the bonding pad 4 are limited by the upper clamping cavity 101 and the lower clamping cavity 501, the lower packaging shell 5 is clamped with the clamping strip 104 through the clamping groove 502, glue is coated at the clamped position to finish equipment packaging, the clamping groove 502 is clamped with the clamping strip 104, the clamping contact area of the glue with the clamping groove 502 and the clamping strip 104 is increased, the upper packaging shell 1 and the lower packaging shell 5 are bonded more firmly, the upper packaging shell 1 and the lower packaging shell 5 can be fixed directly in the first screw hole 103 and the second screw hole 503 by using a threaded connecting piece, and the semiconductor body 3 is packaged; applying tin to the limiting hole 401, inserting the connecting contact 301 into the limiting hole 401, heating the bonding pad 4 by using a hot air gun, melting the tin, and welding the semiconductor body 3 on the bonding pad 4, wherein the connecting contact 301 and the welding leg 402 are connected in a welding manner; the contact position of the lower surface of the heat dissipation plate 2 and the semiconductor body 3 is coated with a thin heat dissipation silicone grease.
It should be noted that, the utility model is a power semiconductor chip packaging structure, during packaging, different packaging modes can be selected, during bonding by glue, tin is coated in the limiting hole 401, then the connecting contact 301 is inserted into the limiting hole 401, the soldering pad 4 is heated by a hot air gun, the tin is melted to weld the semiconductor body 3 on the soldering pad 4, then the heat dissipation plate 2 is clamped in the limiting groove 102 by the heat dissipation plate 201, after the upper surface of the semiconductor body 3 is coated with heat dissipation silicone grease, the semiconductor body is placed in the upper clamping cavity 101 to be closely contacted with the heat dissipation plate 2, finally the lower packaging shell 5 is clamped with the clamping strip 104 by the clamping groove 502, and glue is coated at the clamping position to complete the packaging of the device, and the clamping groove 502 is clamped with the clamping strip 104, the clamping contact area of the glue with the packaging groove 502 and the clamping strip 104 is increased, so that the upper packaging shell 1 and the lower packaging shell 5 are bonded more firmly, for a large-size semiconductor body 3, the upper packaging shell 1 and the lower packaging shell 5 can be fixed by directly using a threaded connecting piece in the first screw hole 103 and the second screw hole 503 to complete the packaging of the semiconductor body 3, and in addition, the heat dissipation plate 2 is contacted with the semiconductor body 3 through heat dissipation silicone grease, so that the heat on the semiconductor body 3 is conducted to the heat dissipation plate 2 and is dissipated to the outside through the heat dissipation plate 201.
The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the utility model as claimed. The scope of the utility model is defined by the appended claims and equivalents thereof.
Claims (6)
1. A power semiconductor paster packaging structure which is characterized in that: the packaging structure comprises an upper packaging shell (1), an upper clamping cavity (101) is formed in the upper packaging shell (1), a clamping strip (104) is fixedly mounted on the lower surface of the upper packaging shell (1) close to the edge position, a limiting groove (102) is formed in the bottom surface of the upper clamping cavity (101) close to the edge position, a radiating plate (2) is mounted in the upper clamping cavity (101) close to the bottom position in a clamping manner, a radiating fin (201) is fixedly mounted on the upper surface of the radiating plate (2), the radiating fin (201) is connected with the limiting groove (102) in a clamping manner, a semiconductor body (3) is mounted on the lower surface of the radiating plate (2) in the upper clamping cavity (101) in a clamping manner, a connecting contact (301) is fixedly mounted on the lower surface of the semiconductor body (3), a welding pad (4) is mounted on the lower surface of the semiconductor body (3), and a lower packaging shell (5) is mounted on the lower surface of the upper packaging shell (1) in a clamping manner, the lower packaging shell (5) is internally provided with a lower clamping cavity (501), and the upper surface of the lower packaging shell (5) close to the edge is provided with a clamping groove (502).
2. The power semiconductor chip package structure according to claim 1, wherein: the upper surface of the upper packaging shell (1) is provided with a first screw hole (103) at a position close to four corners, and the upper surface of the lower packaging shell (5) is provided with a second screw hole (503) at a position close to four corners.
3. The power semiconductor chip package structure of claim 2, wherein: spacing hole (401) have been seted up to pad (4) upper surface, spacing hole (401) inside is kept away from spacing hole (401) upper port position fixed mounting has leg (402).
4. The power semiconductor chip package structure of claim 3, wherein: the clamping strip (104) is connected with the clamping groove (502) in a clamping mode, and the heat dissipation plate (2), the semiconductor body (3) and the bonding pad (4) are limited by the upper clamping cavity (101) and the lower clamping cavity (501).
5. The power semiconductor chip package structure according to claim 4, wherein: the connecting contact (301) is inserted into the limiting hole (401), and the connecting contact (301) is connected with the welding foot (402) in a welding mode.
6. The power semiconductor chip package structure according to claim 5, wherein: and a thin layer of heat dissipation silicone grease is coated on the contact position of the lower surface of the heat dissipation plate (2) and the semiconductor body (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121964372.8U CN215578518U (en) | 2021-08-20 | 2021-08-20 | Power semiconductor paster packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121964372.8U CN215578518U (en) | 2021-08-20 | 2021-08-20 | Power semiconductor paster packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215578518U true CN215578518U (en) | 2022-01-18 |
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ID=79839816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121964372.8U Active CN215578518U (en) | 2021-08-20 | 2021-08-20 | Power semiconductor paster packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215578518U (en) |
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2021
- 2021-08-20 CN CN202121964372.8U patent/CN215578518U/en active Active
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