CN215527723U - 封装结构 - Google Patents

封装结构 Download PDF

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CN215527723U
CN215527723U CN202121213625.8U CN202121213625U CN215527723U CN 215527723 U CN215527723 U CN 215527723U CN 202121213625 U CN202121213625 U CN 202121213625U CN 215527723 U CN215527723 U CN 215527723U
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insulating film
lead frame
chip
film
package structure
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王雄星
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Jiangsu Xingzhou Microelectronics Co ltd
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Jiangsu Xingzhou Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型提供一种封装结构，所述封装结构包括：引线框架；绝缘膜，所述绝缘膜放置在所述引线框架上；芯片，所述芯片放置在所述绝缘膜上；硅胶层，所述硅胶层包裹住所述芯片。本实用新型使用半导体封装工艺在引线框架与芯片之间设置绝缘膜，提高产品隔离耐压能力，提高了芯片与引线框架之间绝缘隔离电压。

Description

封装结构
技术领域
本实用新型涉及半导体领域，尤其涉及一种封装结构。
背景技术
现有技术中，多数类型的霍尔电流传感器是开环式和闭环式两种，其结构均存在中间穿孔的部分。
无论开环式或者闭环式的霍尔电流传感器，基本结构都是通过原边电流导线穿过环形磁芯中间孔这种结构，在环形磁芯中产生磁场，或者初级电流线绕圆形磁环产生磁场的方式来实现。
现有技术中霍尔电流传感器结构缺陷是：整个霍尔传感器模块三维尺寸大，原因是受限于圆形磁环的体积，加之初级电流线的直径以及外围辅助测试电路印制电路板的尺寸限制，无法将霍尔传感器模块做小。
霍尔电流传感器做成半导体集成电路，常规的SOP16封装通过普通绝缘胶来达到芯片与引线框架之间绝缘隔离电压无法承受3kV、50HZ电流通过1分钟。
常规的SOP16封装内部铜框架导线阻抗大、功耗大，无法解决过大电流工作时散热问题。由于封装内部塑封材料和芯片的膨胀率相差巨大，在通过大电流工作时，产生高温的造成内部应力会影响产品的稳定性和可靠性。
实用新型内容
本实用新型所要解决的技术问题是提高芯片与引线框架之间绝缘隔离电压，提供一种封装结构。
为了解决上述问题，本实用新型提供了一种封装结构，包括：引线框架；绝缘膜，所述绝缘膜放置在所述引线框架上；芯片，所述芯片放置在所述绝缘膜上；硅胶层，所述硅胶层包裹住所述芯片。
本实用新型使用半导体封装工艺在引线框架与芯片之间设置绝缘膜，提高产品隔离耐压能力，提高了芯片与引线框架之间绝缘隔离电压。
附图说明
附图1所示为本实用新型一具体实施方式步骤示意图。
附图2A-2G所示为本实用新型一具体实施方式工艺示意图。
附图3所示为本实用新型一具体实施方式所述将绝缘膜放置在所述引线框架上步骤示意图。
具体实施方式
下面结合附图对本实用新型提供的的具体实施方式做详细说明。
附图1所示为本实用新型一具体实施方式步骤示意图，包括：步骤S11，提供一引线框架；步骤S12，将绝缘膜放置在所述引线框架上；步骤S13，将芯片放置在所述绝缘膜上；步骤S14，采用硅胶层包裹住所述芯片。
附图2A所示，参考步骤S11，提供一引线框架201。在本具体实施方式中，所述引线框架采用金属Cu材料。
步骤S12，将绝缘膜203放置在所述引线框架201上。在本具体实施方式中，所述绝缘膜采用DAF膜。
在本实用新型的一个具体实施方式中，上述结构的形成步骤进一步采用如下方法，参考附图3所示，为本实用新型一具体实施方式所述将绝缘膜放置在所述引线框架上步骤示意图，包括：步骤S31，将第一装片膜放置在所述引线框架上；步骤S32，将绝缘膜放置在所述第一装片膜上，使所述绝缘膜和所述第一装片膜充分粘合；步骤S33，将第二装片膜放置在所述绝缘膜上。
附图2B所示，参考步骤S31，将第一装片膜202放置在所述引线框架201上。在本具体实施方式中，所述第一装片膜202起到黏合所述引线框架201与所述绝缘膜203的作用。
附图2C所示，参考步骤S32，将绝缘膜203放置在所述第一装片膜202上，使所述绝缘膜203和所述第一装片膜202充分粘合。在本具体实施方式中，所述绝缘膜203采用DAF膜。绝缘膜203与第一装片膜202膜充分粘合后，对绝缘膜203做切割，切割后的绝缘膜203可以使用半导体工艺装片机器做黏贴，放置在引线框架201上面。
附图2D所示，参考步骤S31，将第二装片膜204放置在所述绝缘膜203上。在本具体实施方式中，所述第二装片膜204起到黏合所述绝缘膜203与下述芯片205的作用。
上述步骤实施完毕后，继续实施如下步骤。
附图2E所示，参考步骤S13，将芯片205放置在所述绝缘膜203上。
在一具体实施方式中，如附图2F所示，连接引线206，使芯片205与引线框架201电学连接。
附图2G所示，参考步骤S14，采用硅胶层207包裹住所述芯片205。在本具体实施方式中，所述硅胶层207采用电子级硅胶，利用电子级硅胶起到隔离芯片205与后续塑封料的作用。这种封装工艺保证了产品在不同温度的使用环境中几乎不受塑封料膨胀变形的影响，也减低框架外部的应力对芯片性能的影响，从而提高产品的稳定性和可靠性。
上述步骤完成后，即得到附图2G所示的一种封装结构，包括：引线框架201；绝缘膜203，所述绝缘膜203放置在所述引线框架201上；芯片205，所述芯片205放置在所述绝缘膜203上；硅胶层207，所述硅胶层207包裹住所述芯片205。在本实用新型的一种具体实施方式中，所述绝缘膜203的下方存在第一装片膜202；所述第一装片膜202黏合所述引线框架201与所述绝缘膜203，所述绝缘膜203的上方存在第二装片膜204，所述第二装片膜204黏合所述绝缘膜203与所述芯片205。所述引线框架201采用金属Cu材料；所述绝缘膜203采用DAF膜；所述硅胶层207采用电子级硅胶。
上述技术方案通过在引线框架和芯片之间，利用新的封装工艺，在引线框架与芯片之间设置绝缘膜，提高产品隔离耐压能力，提高了芯片与引线框架之间绝缘隔离电压，使得封装后产品的隔离电压达到5KV/50HZ/1分钟。
以上所述仅是本实用新型的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本实用新型原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本实用新型的保护范围。

Claims (8)

1.一种封装结构，其特征在于，包括：
引线框架；
绝缘膜，所述绝缘膜放置在所述引线框架上；
芯片，所述芯片放置在所述绝缘膜上；
硅胶层，所述硅胶层包裹住所述芯片。
2.根据权利要求1所述的封装结构，其特征在于，所述绝缘膜的下方存在第一装片膜。
3.根据权利要求1所述的封装结构，其特征在于，所述绝缘膜的上方存在第二装片膜。
4.根据权利要求2所述的封装结构，其特征在于，所述第一装片膜黏合所述引线框架与所述绝缘膜。
5.根据权利要求3所述的封装结构，其特征在于，所述第二装片膜黏合所述绝缘膜与所述芯片。
6.根据权利要求1所述的封装结构，其特征在于，所述引线框架采用金属Cu材料。
7.根据权利要求1所述的封装结构，其特征在于，所述绝缘膜采用DAF膜。
8.根据权利要求1所述的封装结构，其特征在于，所述硅胶层采用电子级硅胶。
CN202121213625.8U 2021-06-01 2021-06-01 封装结构 Active CN215527723U (zh)

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