CN110223924A - 一种晶圆级封装方法和晶圆 - Google Patents
一种晶圆级封装方法和晶圆 Download PDFInfo
- Publication number
- CN110223924A CN110223924A CN201910636287.XA CN201910636287A CN110223924A CN 110223924 A CN110223924 A CN 110223924A CN 201910636287 A CN201910636287 A CN 201910636287A CN 110223924 A CN110223924 A CN 110223924A
- Authority
- CN
- China
- Prior art keywords
- wafer
- resin
- level packaging
- packaging method
- leading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 61
- 239000011347 resin Substances 0.000 claims abstract description 61
- 235000012431 wafers Nutrition 0.000 claims description 120
- 238000005520 cutting process Methods 0.000 claims description 40
- 238000005538 encapsulation Methods 0.000 claims description 17
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 14
- 239000006071 cream Substances 0.000 claims description 14
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 238000005476 soldering Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000007711 solidification Methods 0.000 claims description 3
- 230000008023 solidification Effects 0.000 claims description 3
- 239000010426 asphalt Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000009998 heat setting Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本发明提供一种晶圆级封装方法、晶圆级芯片封装单元和晶圆,本发明在对晶圆进行加工前直接在具有切割道的晶圆的表面覆盖树脂使树脂与切割道接触并高温硬化,在后续对晶圆进行加工过程中,晶圆受到其表面固化的树脂的保护,能够防止晶圆在加工过程中易破裂的问题。通过上述方法能够一次完成晶圆表面所有树脂的覆盖并高温硬化,缩短了生产周期和降低成本。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种晶圆级封装方法、晶圆级芯片封装单元和晶圆。
背景技术
晶圆级芯片封装技术是对整片晶圆进行封装后再切割得到单个成品芯片的技术,封装后的芯片尺寸与裸片基本一致。晶圆级芯片尺寸封装技术改变传统封装如陶瓷无引线芯片载具、有机无引线芯片载具和数码相机模块式的模式,顺应了市场对微电子产品日益轻、薄、短、小和低价化要求。经晶圆级芯片尺寸封装技术后的芯片尺寸达到了高度微型化,芯片成本随着芯片尺寸的减小和晶圆尺寸的增大而显着降低。晶圆级芯片尺寸封装技术是可以将IC设计、晶圆制造、封装测试、基本板制造整合为一体的技术,是当前封装领域的热点和未来发展的趋势。
现有晶圆级芯片封装技术在封装前段(晶圆切割,上芯,焊线制程)过程易导致晶圆破裂,且生产周期和成本较高;另外,晶圆级芯片到PCB之间采用焊线,如图1、图2所示,现有技术中,芯片3上的引出端子2通过焊线4连接引线框架5再连接到PCB等其它外接的元器件,芯片3和引出端子2被封装在环氧树脂1内。现有技术中通过焊线4连接的形式使得传输路径长电感较大,传输不稳定,难以满足电子产品薄、小的要求。
发明内容
为解决现有技术中在封装前段过程中的晶圆破裂的技术问题,本发明提供一种日程提醒的方法、终端设备和存储介质,具体方案如下:
一种晶圆级封装方法,包括以下步骤:
S1:在晶圆的表面覆盖树脂使所述树脂与所述晶圆的切割道接触;
S2:加热所述树脂以使所述树脂固化到预设硬度;
S3:切割所述树脂和所述切割道以得到晶圆级芯片封装单元。
进一步的,步骤S1中,布置在晶圆上的引出端子被覆盖所述树脂内。
进一步的,所述方法还包括在步骤S2和步骤S3之间的电极构造步骤,所述电极构造步骤包括:
S401:在所述树脂上蚀刻出电极槽以使所述引出端子从所述树脂中露出;
S402:在所述电极槽内添加焊料,所述焊料与所述引出端子接触;
S403:形成与所述引出端子电连接的电极。
进一步的,步骤S402中,所述焊料的端面沿背离所述引出端子的方向超过所述树脂的表面。
进一步的,在步骤S403中,所述焊料为锡膏,采用锡膏回流焊形成所述电极。
进一步的,所述晶圆的表面包括晶圆上引出端子所在的第一表面、晶圆上与所述第一表面相对布置的第二表面。
进一步的,所述树脂为透明树脂。
进一步的,所述树脂为环氧树脂胶膜。
一种应用于如上所述的晶圆级封装方法的晶圆,其特征在于,包括晶圆级芯片和位于相邻晶圆级芯片之间的切割道,所述切割道能够被切割为环绕在所述晶圆级芯片周围并用于保护所述晶圆级芯片的子切割道。
与现有技术相比,本发明在对晶圆进行加工前直接在具有切割道的晶圆的表面覆盖树脂使树脂与切割道接触并高温硬化,在后续对晶圆进行加工(如切割或其它机械加工等)过程中,晶圆受到其表面固化的树脂的保护,能够防止晶圆在加工过程中易破裂的问题。通过上述方法能够一次完成晶圆表面所有树脂的覆盖并高温硬化,缩短了生产周期和降低成本。
本发明进一步通过蚀刻和点锡膏的方法使与引出端子接触的锡膏形成电极,通过电极实现晶圆级芯片上的引出端子与外部电路连接,不需要再使用焊线,缩短了传输距离,减小了电感,传输更为稳定,操作简单,与传统焊线相比,能够很好地满足电子产品薄、小的要求并缩短生产周期。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中:
图1、图2为现有技术的晶圆级芯片封装单元结构图;
图3为本发明实施例的晶圆级芯片封装单元的俯视图;
图4为本发明实施例的晶圆级芯片封装单元的内部结构剖视图;
图5为本发明实施例的晶圆及设置在晶圆上的引出端子的结构图;
图6为图5的俯视图;
图7为本发明实施例的在晶圆的第一表面和第二表面覆盖树脂的示意图;
图8为本发明实施例的高温固化树脂的示意图;
图9为本发明实施例的蚀刻树脂的示意图;
图10为本发明实施例的在电极槽内点饮锡膏的示意图;
图11为本发明实施例的锡膏回流焊的示意图;
图12为本发明实施例的切割树脂和晶圆的切割道以将晶圆切割成晶圆级芯片封装单元的示意图。
在附图中,相同的标识对象采用相同的附图标记,附图并未按实际比例绘制。
具体实施方式
下面将结合附图对本发明作进一步的说明。
如图7-图12所示,本实施例提供一种晶圆级封装方法,该方法包括以下步骤:
S1:在晶圆的表面覆盖树脂使所述树脂与所述晶圆的切割道接触;
S2:加热所述树脂以使所述树脂固化到预设硬度;
S3:切割所述树脂和所述切割道以得到晶圆级芯片封装单元。
该方法通过在对晶圆18进行加工前直接在具有切割道11的晶圆18的表面覆盖树脂15使树脂15与切割道11接触并高温硬化,在后续对晶圆18进行加工(如切割或其它机械加工等)过程中,晶圆18受到其表面固化的树脂15的保护,能够防止晶圆18在加工过程中易破裂的问题。通过上述方法能够一次完成晶圆18表面所有树脂15的覆盖并高温硬化,缩短了生产周期和降低成本,不需要反复覆盖再高温硬化,树脂覆盖过程中不需要中断覆盖树脂的步骤并执行其它步骤后再恢复树脂的覆盖。
图5、图6示出了晶圆18和布置在晶圆18上的引出端子9的结构,如图5、图6所示,本实施例还提供一种应用于晶圆级封装方法的晶圆18,晶圆18包括晶圆级芯片8和位于相邻晶圆级芯片8之间的切割道11,晶圆18的俯视图如图6所示,切割道11能够被切割为环绕在晶圆级芯片8周围并用于保护晶圆级芯片8的子切割道10。本实施例的切割道11和子切割道10均能够保护晶圆级芯片8。引出端子9设置在晶圆级芯片8上以将晶圆级芯片8的内部电路引出。
由于晶圆18中构造有切割道11,故将晶圆18的表面覆盖树脂15并将树脂15与切割道11接触后,就已经实现了各个晶圆级芯片8的塑封,树脂15能够一次性覆盖在晶圆18上需要覆盖的表面,在树脂15覆盖的过程中,不需要中断树脂15的覆盖步骤并执行其它步骤后再继续覆盖树脂15,缩短生产周期和降低成本;由于晶圆18中构造有切割道11,能够在对晶圆18进行加工前完成树脂15的覆盖并固化到预设硬度,从而在前段加工过程中通过固化的树脂15保护晶圆18避免晶圆18破裂。
如图7-图12所示,本实施例的晶圆级封装方法的具体步骤如下。
晶圆18的表面包括第一表面19和第二表面20,第一表面19为晶圆18上引出端子9所在的表面,第二表面20与第一表面19相对布置。在第一表面19和第二表面20上覆盖树脂15,优选的,引出端子9被覆盖在树脂15内,如图7所示。将树脂15在高温环境12中加热,使树脂15固化到预设硬度,如图8所示。将树脂15固化到预设硬度后,执行电极构造步骤,电极构造步骤包括:
S401:在树脂15上蚀刻出电极槽16以使引出端子9从树脂15中露出,如图9所示;
S402:在电极槽16内添加焊料,优选为锡膏17,锡膏17与引出端子9接触,如图10所示,优选的,锡膏17的端面沿背离引出端子9的方向超过树脂15的表面,锡膏17可以为低温免洗锡膏;
S403:形成与引出端子9电连接的电极6,如图11所示,优选地,采用锡膏回流焊形成电极6。
引出端子9通过电极6直接与PCB板等外接元器件连接,不再需要通过焊线引出,缩短了传输距离从而减小了电感,传输更为稳定,与传统焊线相比,能够很好地满足电子产品薄、小的要求并缩短生产周期。
电极构造步骤完成后,对树脂15和切割道11进行切割从而得到晶圆级芯片封装单元13,如图12所示,由于晶圆18受到固化后的树脂15的保护,切割操作或其它对晶圆进行加工的操作不会引起晶圆18破裂。如图3、图4所示,晶圆级芯片封装单元13包括晶圆级芯片8,环绕在晶圆级芯片8周围的子切割道10,子树脂7覆盖在晶圆级芯片表面并与子切割道10,晶圆级芯片表面包括晶圆级芯片8上布置有引出端子9的表面和与晶圆级芯片8上布置有引出端子9的表面相对的表面,晶圆级芯片8位于子树脂7和子切割道10构成的封闭空间内。
电极构造步骤完成后,切割所述树脂15和所述切割道11以得到晶圆级芯片封装单元13。将切割道11切割为环绕在晶圆级芯片8周围的子切割道10,将树脂15切割为与子切割道11接触并覆盖在晶圆级芯片表面的子树脂7,晶圆级芯片8位于子树脂7和子切割道10构成的封闭空间内,子切割道10用于保护所述晶圆级芯片。
切割出的不合格品14包括晶圆级芯片8,子切割道10只位于晶圆级芯片8的部分侧面并没有环绕晶圆级芯片8。
本实施例中的树脂可以为透明的环氧树脂胶膜,环氧树脂胶膜常温下具备胶膜的柔韧性和可贴附性,在高温固化状态可改变环氧树脂胶膜特性,具备一定抗压强度、绝缘性,提供物理和电气保护,防止外部环境冲击芯片。
虽然已经参考优选实施例对本发明进行了描述,但在不脱离本发明的范围的情况下,可以对其进行各种改进并且可以对其中部分或者全部技术特征进行等同替换。尤其是,只要不存在逻辑或结构冲突,各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例,而是包括落入权利要求的范围内的所有技术方案。
Claims (9)
1.一种晶圆级封装方法,其特征在于,包括以下步骤:
S1:在晶圆的表面覆盖树脂使所述树脂与所述晶圆的切割道接触;
S2:加热所述树脂以使所述树脂固化到预设硬度;
S3:切割所述树脂和所述切割道以得到晶圆级芯片封装单元。
2.根据权利要求1所述的晶圆级封装方法,其特征在于,步骤S1中,布置在晶圆上的引出端子被覆盖所述树脂内。
3.根据权利要求2所述的晶圆级封装方法,其特征在于,所述方法还包括在步骤S2和步骤S3之间的电极构造步骤,所述电极构造步骤包括:
S401:在所述树脂上蚀刻出电极槽以使所述引出端子从所述树脂中露出;
S402:在所述电极槽内添加焊料,所述焊料与所述引出端子接触;
S403:形成与所述引出端子电连接的电极。
4.根据权利要求3所述的晶圆级封装方法,其特征在于,步骤S402中,所述焊料的端面沿背离所述引出端子的方向超过所述树脂的表面。
5.根据权利要求3所述的晶圆级封装方法,其特征在于,在步骤S403中,所述焊料为锡膏,采用锡膏回流焊形成所述电极。
6.根据权利要求1-5中任一项所述的晶圆级封装方法,其特征在于,所述晶圆的表面包括晶圆上引出端子所在的第一表面、晶圆上与所述第一表面相对布置的第二表面。
7.根据权利要求1-5中任一项所述的晶圆级封装方法,其特征在于,所述树脂为透明树脂。
8.根据权利要求1-5中任一项所述的晶圆级封装方法,其特征在于,所述树脂为环氧树脂胶膜。
9.一种应用于如权利要求1-7中任一项所述的晶圆级封装方法的晶圆,其特征在于,包括晶圆级芯片和位于相邻晶圆级芯片之间的切割道,所述切割道能够被切割为环绕在所述晶圆级芯片周围并用于保护所述晶圆级芯片的子切割道。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910636287.XA CN110223924A (zh) | 2019-07-15 | 2019-07-15 | 一种晶圆级封装方法和晶圆 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910636287.XA CN110223924A (zh) | 2019-07-15 | 2019-07-15 | 一种晶圆级封装方法和晶圆 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN110223924A true CN110223924A (zh) | 2019-09-10 |
Family
ID=67813385
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910636287.XA Pending CN110223924A (zh) | 2019-07-15 | 2019-07-15 | 一种晶圆级封装方法和晶圆 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN110223924A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111211096A (zh) * | 2020-01-10 | 2020-05-29 | 珠海格力电器股份有限公司 | 一种芯片模块封装结构和封装方法 |
CN112242359A (zh) * | 2019-07-16 | 2021-01-19 | 珠海零边界集成电路有限公司 | 一种芯片封装结构及芯片封装方法 |
CN112992836A (zh) * | 2019-12-12 | 2021-06-18 | 珠海格力电器股份有限公司 | 一种铜桥双面散热的芯片及其制备方法 |
CN113035793A (zh) * | 2019-12-25 | 2021-06-25 | 珠海格力电器股份有限公司 | 芯片的制作方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6482730B1 (en) * | 1999-02-24 | 2002-11-19 | Texas Instruments Incorporated | Method for manufacturing a semiconductor device |
US20030143819A1 (en) * | 2002-01-25 | 2003-07-31 | Infineon Technologies Ag | Method of producing semiconductor chips with a chip edge guard, in particular for wafer level packaging chips |
CN102931094A (zh) * | 2011-08-09 | 2013-02-13 | 万国半导体股份有限公司 | 具有增大焊接接触面的晶圆级封装结构及制备方法 |
CN104299950A (zh) * | 2014-09-28 | 2015-01-21 | 南通富士通微电子股份有限公司 | 晶圆级芯片封装结构 |
CN104347542A (zh) * | 2014-09-26 | 2015-02-11 | 上海朕芯微电子科技有限公司 | 五面包封的csp结构及制造工艺 |
CN109411368A (zh) * | 2017-08-17 | 2019-03-01 | 半导体组件工业公司 | 多面模塑半导体封装和相关方法 |
-
2019
- 2019-07-15 CN CN201910636287.XA patent/CN110223924A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6482730B1 (en) * | 1999-02-24 | 2002-11-19 | Texas Instruments Incorporated | Method for manufacturing a semiconductor device |
US20030143819A1 (en) * | 2002-01-25 | 2003-07-31 | Infineon Technologies Ag | Method of producing semiconductor chips with a chip edge guard, in particular for wafer level packaging chips |
CN102931094A (zh) * | 2011-08-09 | 2013-02-13 | 万国半导体股份有限公司 | 具有增大焊接接触面的晶圆级封装结构及制备方法 |
CN104347542A (zh) * | 2014-09-26 | 2015-02-11 | 上海朕芯微电子科技有限公司 | 五面包封的csp结构及制造工艺 |
CN104299950A (zh) * | 2014-09-28 | 2015-01-21 | 南通富士通微电子股份有限公司 | 晶圆级芯片封装结构 |
CN109411368A (zh) * | 2017-08-17 | 2019-03-01 | 半导体组件工业公司 | 多面模塑半导体封装和相关方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112242359A (zh) * | 2019-07-16 | 2021-01-19 | 珠海零边界集成电路有限公司 | 一种芯片封装结构及芯片封装方法 |
CN112992836A (zh) * | 2019-12-12 | 2021-06-18 | 珠海格力电器股份有限公司 | 一种铜桥双面散热的芯片及其制备方法 |
CN112992836B (zh) * | 2019-12-12 | 2023-01-17 | 珠海格力电器股份有限公司 | 一种铜桥双面散热的芯片及其制备方法 |
CN113035793A (zh) * | 2019-12-25 | 2021-06-25 | 珠海格力电器股份有限公司 | 芯片的制作方法 |
CN111211096A (zh) * | 2020-01-10 | 2020-05-29 | 珠海格力电器股份有限公司 | 一种芯片模块封装结构和封装方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110223924A (zh) | 一种晶圆级封装方法和晶圆 | |
US8183092B2 (en) | Method of fabricating stacked semiconductor structure | |
US7714453B2 (en) | Interconnect structure and formation for package stacking of molded plastic area array package | |
US6492726B1 (en) | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection | |
US20090127682A1 (en) | Chip package structure and method of fabricating the same | |
US9147600B2 (en) | Packages for multiple semiconductor chips | |
TWI486105B (zh) | 封裝結構及其製造方法 | |
JP2004158753A (ja) | リードフレーム材及びその製造方法、並びに半導体装置及びその製造方法 | |
US20210202337A1 (en) | Semiconductor device | |
CN112447534A (zh) | 封装体及其制备方法 | |
US20060214308A1 (en) | Flip-chip semiconductor package and method for fabricating the same | |
CN110176439B (zh) | 一种模块SiP结构及其制造方法 | |
JP2000329632A (ja) | 圧力センサーモジュール及び圧力センサーモジュールの製造方法 | |
CN105374763A (zh) | 用于封装应力敏感器件的硅保护物 | |
US9117807B2 (en) | Integrated passives package, semiconductor module and method of manufacturing | |
KR20080074468A (ko) | 초음파를 이용한 반도체 칩의 표면실장방법 | |
US20080067641A1 (en) | Package semiconductor and fabrication method thereof | |
US8481369B2 (en) | Method of making semiconductor package with improved standoff | |
CN220821555U (zh) | 传感器芯片qfn封装过渡结构 | |
US20240128185A1 (en) | Semiconductor device and pre-forming adaptor thereof | |
KR20090118438A (ko) | 반도체 패키지 및 그 제조 방법 | |
JP2004165525A (ja) | 半導体装置及びその製造方法 | |
CN213401182U (zh) | 一种系统级封装的无线通讯芯片 | |
JP2004063680A (ja) | チップ上基板のチップアレイ式ボールグリッドアレイパッケージの製造方法 | |
US11715644B2 (en) | Method for packaging integrated circuit chip |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20200917 Address after: 519015 Room 1001, Lianshan Lane, Jida Jingshan Road, Xiangzhou District, Zhuhai City, Guangdong Province Applicant after: Zhuhai Zero Boundary Integrated Circuit Co.,Ltd. Applicant after: GREE ELECTRIC APPLIANCES,Inc.OF ZHUHAI Address before: 519000 Guangdong city of Zhuhai Province Qianshan Applicant before: GREE ELECTRIC APPLIANCES,Inc.OF ZHUHAI |
|
TA01 | Transfer of patent application right | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190910 |
|
RJ01 | Rejection of invention patent application after publication |