CN109411368A - 多面模塑半导体封装和相关方法 - Google Patents
多面模塑半导体封装和相关方法 Download PDFInfo
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- CN109411368A CN109411368A CN201810750840.8A CN201810750840A CN109411368A CN 109411368 A CN109411368 A CN 109411368A CN 201810750840 A CN201810750840 A CN 201810750840A CN 109411368 A CN109411368 A CN 109411368A
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Classifications
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本发明涉及多面模塑半导体封装和相关方法。形成半导体封装的方法的实施方式可包括在晶圆的第一侧上形成电触点,将光刻胶层施加到晶圆的第一侧,对光刻胶层进行图案化,以及使用光刻胶层在晶圆的第一侧中蚀刻凹槽。所述方法可包括将第一模塑料施加到凹槽中及晶圆的第一侧上方,将与晶圆的第一侧相对的晶圆的第二侧磨削到所述晶圆的第一侧中形成的凹槽,将第二模塑料和层压树脂中的一者施加到晶圆的第二侧,以及将晶圆切割成半导体封装。可由第一模塑料、所述第二模塑料和所述层压树脂中的一者覆盖每个半导体封装的六个侧面。
Description
技术领域
本文件的各方面整体涉及半导体封装,诸如芯片尺寸封装和倒装芯片封装。更具体的实施方式涉及由模塑料覆盖的半导体封装。
背景技术
减小半导体封装尺寸长期以来一直是业内期望的,因为这总体上带来了经济效益以及技术效益。半导体封装尺寸的减小通常会导致制造期间半导体管芯和封装发生损坏的风险增加。保护性覆盖件或模塑件大致覆盖半导体封装的部分以保护半导体免受环境、静电放电和电涌等的影响。
发明内容
形成半导体封装的方法的实施方式可包括在晶圆的第一侧上形成多个电触点,将光刻胶层施加到晶圆的第一侧,对光刻胶层进行图案化,以及使用光刻胶层在晶圆的第一侧中蚀刻多个凹槽。该方法可包括将第一模塑料施加到所述多个凹槽中及晶圆的第一侧上方,将与晶圆的第一侧相对的晶圆的第二侧磨削到晶圆的第一侧中形成的所述多个凹槽,将第二模塑料和层压树脂中的一者施加到晶圆的第二侧,以及将晶圆切割成多个半导体封装。可由第一模塑料、第二模塑料和层压树脂中的一者覆盖每个半导体封装的六个侧面。
形成半导体封装的方法的实施方式可包括以下各项中的一项、全部或任一项:
可使用印刷机模塑技术和压塑技术中的一者施加第一模塑料。
封装内的管芯的第一侧的周边可基本上为八边形和具有倒圆拐角的矩形中的一者。
可使用光刻胶层及聚酰亚胺、聚苯并恶唑和酚醛树脂中的一者在晶圆的第一侧中蚀刻所述多个凹槽。
可使用光刻胶层和钝化掩模在晶圆的第一侧中蚀刻所述多个凹槽。
阻焊层、钝化层、中间层及阻焊层、钝化层和中间层的组合中的一者可耦接到晶圆的第一侧并且可由第一模塑料覆盖。
可使用蚀刻工艺对所述多个封装进行切割。
形成半导体封装的方法的实施方式可包括在晶圆的第一侧上形成金属层,将第一光刻胶层施加在金属层上,对第一光刻胶层进行图案化,使用第一光刻胶层形成耦接到金属层的电触点,移除第一光刻胶层,蚀刻金属层,以及在晶圆的第一侧中蚀刻多个凹槽。该方法可包括将第一模塑料施加到所述多个凹槽中、电触点上方及晶圆的第一侧上方,通过磨削第一模塑料而透过第一模塑料暴露电触点,将与晶圆的第一侧相对的晶圆的第二侧磨削到晶圆的第一侧中形成的所述多个凹槽,将第二模塑料和层压树脂中的一者施加到晶圆的第二侧,以及将晶圆切割成多个半导体封装。每个半导体封装可由第一模塑料、第二模塑料和层压树脂中的一者覆盖在每个半导体封装的第一侧、第二侧、第三侧、第四侧、第五侧和第六侧上。
形成半导体封装的方法的实施方式可包括以下各项中的一项、全部或任一项:
每个半导体封装内的管芯的第一侧可包括周边,该周边是八边形和具有倒圆边缘的矩形中的一者。
第一模塑料可通过所述多个凹槽的侧壁中形成的多个脊锚定到所述多个凹槽的侧壁。
可在所述多个凹槽的蚀刻期间使用深反应离子蚀刻技术形成所述多个凹槽。
可使用聚酰亚胺、聚苯并恶唑和酚醛树脂中的一者在晶圆的第一侧中蚀刻所述多个凹槽。
可使用钝化掩模在晶圆的第一侧中蚀刻所述多个凹槽。
阻焊层、钝化层、中间层及阻焊层、钝化层和中间层的组合中的一者可耦接到晶圆的第一侧并且可由第一模塑料覆盖。
半导体封装的实施方式可包括具有第一侧、第二侧、第三侧、第四侧、第五侧和第六侧的管芯,该管芯的第一侧包括多个电触点。该封装可包括覆盖管芯的第一侧、管芯的第二侧、管芯的第三侧、管芯的第四侧和管芯的第五侧的第一模塑料,其中所述多个电触点延伸穿过第一模塑料中的多个开口。该封装可包括覆盖管芯的第六侧的第二模塑料和层压树脂中的一者,其中在管芯的切割之后不存在管芯的第一侧的管芯碎裂。
形成半导体封装的方法的实施方式可包括以下各项中的一项、全部或任一项:
第六侧可与第一侧相对。
管芯的第一侧的周边可包括八边形和倒圆矩形中的一者。
第一模塑料可通过管芯的第二侧、管芯的第三侧、管芯的第四侧和管芯的第五侧中形成的多个脊锚定到管芯的第二侧、管芯的第三侧、管芯的第四侧和管芯的第五侧。
所述多个电触点可包含镍、金和铝的组合及锡、银和铜的组合中的一者。
该封装可包括耦接到晶圆的第一侧并且由第一模塑料覆盖的阻焊层、钝化层、中间层及阻焊层、钝化层和中间层的组合中的一者。
对于本领域的普通技术人员而言,通过具体实施方式以及附图并通过权利要求书,上述以及其他方面、特征和优点将会显而易见。
附图说明
将在下文中结合附图来描述各实施方式,其中类似标号表示类似元件,并且:
图1是半导体封装的剖面侧视图;
图2是半导体封装的顶视图;
图3是示出半导体封装的形成的第一工艺流程;
图4是其中切出有多个凹槽的半导体晶圆的顶视图;
图5是其中蚀刻有多个凹槽的半导体晶圆的顶视图;
图6是其中蚀刻有多个凹槽的半导体晶圆的第二实施方式的顶视图;
图7是其中蚀刻有多个凹槽的半导体晶圆的第三实施方式的顶视图;
图8是其上施加有模塑件的晶圆的一部分的剖视图;
图8A是模塑件与管芯中形成的凹槽的侧壁之间的接合的放大剖视图;
图9是示出半导体封装的形成的第二工艺流程;
图10是示出半导体封装的形成的一部分的第三工艺流程。
图11示出了用于在第三工艺流程中形成凹槽的第一替代方案。
图12示出了用于在第三工艺流程中形成凹槽的第二替代方案;
图13示出了用于在第三工艺流程中形成凹槽的第三替代方案;
图14示出了用于在第三工艺流程中形成凹槽的第四替代方案;并且
图15是示出半导体封装的形成的第四工艺流程。
具体实施方式
本公开、其各方面以及实施方式并不限于本文所公开的具体部件、组装工序或方法元素。本领域已知的与预期半导体封装件符合的许多另外的部件、组装工序和/或方法元件将显而易见地能与本公开的特定实施方式一起使用。因此,例如,尽管本发明公开了具体实施方式,但是此类实施方式和实施部件可包括符合预期操作和方法的本领域已知用于此类半导体封装以及实施部件和方法的任何形状、尺寸、样式、类型、模型、版本、量度、浓度、材料、数量、方法元素、步骤等。
参见图1,示出了半导体封装的剖面侧视图。半导体封装包括管芯2,该管芯包括第一侧4、第二侧6、与第二侧6相对的第三侧8、第四侧、与第四侧相对的第五侧(第四侧和第五侧两者在该视图中位于绘图表面之内和之外)以及与第一侧4相对的第六侧10。在各种实施方式中,管芯2的第二侧6、管芯的第三侧8、管芯的第四侧和/或管芯的第五侧可包括其中的凹槽。
在各种实施方式中,一个或多个电触点12耦接到管芯2的第一侧4。在各种实施方式中,电触点是金属,并且以非限制性示例的方式,可为铜、银、金、镍、钛、铝、它们的任何组合或合金、或另一种金属。在再其他实施方式中,电触点12可不为金属的,而是可为另一种导电材料。
在各种实施方式中,第一模塑料14覆盖管芯的第一侧、第二侧、第三侧、第四侧和第五侧。在各种实施方式中,以非限制性示例的方式,模塑料可为环氧树脂模塑料、丙烯酸模塑料或另一种类型的能够物理地支撑管芯并且对污染物的进入提供防护的材料。在各种实施方式中,层压树脂或第二模塑料覆盖管芯的第六侧10。
电触点12各自延伸穿过第一模塑料14中的对应多个开口。在各种实施方式中,如图1所示,电触点12延伸超过模塑件14的表面,而在其他实施方式中,电触点与模塑料14的表面处于同一水平或齐平。
在各种实施方式中,管芯的侧面将没有缺口或裂纹,特别是在管芯的半导体器件侧面上。这通过使用蚀刻技术(而不是常规的锯切技术)形成每个管芯的第二侧、第三侧、第四侧和第五侧来完成。本文将结合图3的讨论更完全公开这种方法。
此外,第一模塑料可锚定到管芯的第二侧、第三侧、第四侧和第五侧。在各种实施方式中,锚定效应是模塑料与沿着管芯的第二侧、第三侧、第四侧和第五侧形成的多个脊相互作用的结果。本文将结合图3的讨论更完全公开该锚定效应。
参见图2,示出了半导体封装的顶视图。在图2中可清楚看出,模塑料14环绕每个电触点12(图2中的阴影区域)的周边,使得管芯的整个第一侧(以及每隔一侧)不暴露。
参见图3,示出了第一工艺流程,该第一工艺流程示出了半导体封装的形成。在各种实施方式中,用于制备半导体封装的方法包括提供晶圆16,该晶圆可包含任何特定类型的衬底材料,以非限制性示例的方式包括硅、蓝宝石、红宝石、砷化镓、玻璃或任何其他半导体晶圆衬底类型。在各种实施方式中,金属层18形成在晶圆16的第一侧28上,并且可使用溅射技术形成。在其他实施方式中,金属层18使用其他技术形成,以非限制性示例的方式,所述其他技术诸如为电镀、化学镀、化学气相沉积以及其他沉积金属层的方法。在特定实施方式中,金属层是钛/铜晶种层,而在其他实施方式中,以非限制性示例的方式,金属层可包含铜、钛、金、镍、铝、银、或它们的任何组合或合金。
在各种实施方式中,第一光刻胶层20在金属层18上方形成并图案化。一个或多个电触点22可在金属层18之上及光刻胶层20之内形成。在各种实施方式中,这可使用各种电镀或化学镀技术进行,但可在各种实施方式中采用沉积和蚀刻技术。电触点22可为此前在本文公开的任何类型的电触点(凸块、螺栓等)。在各种实施方式中,通过灰化或溶剂溶解工艺移除第一光刻胶层20,并且可在形成电触点之后蚀刻掉金属层18。
在各种实施方式中,第二光刻胶层24在晶圆16上方形成并图案化。在各种实施方式中,如图3所示,第二图案化的光刻胶层24不覆盖电触点22。在其他实施方式中,第二光刻胶层连同晶圆一起共形地形成在电触点上方。参见图9,示出了第二工艺流程,该第二工艺流程示出了半导体封装的形成。在该工艺流程中,第二光刻胶层68作为共形层形成在电触点70上方。除该差异以外,图9所示的工艺包括与图3所示的工艺相同的工艺步骤。
返回参见图3,在各种实施方式中,该方法包括使用第二图案化的光刻胶层在晶圆16的第一侧28中蚀刻多个凹槽26。在各种实施方式中,凹槽的宽度可介于约50与约150微米宽之间,而在其他实施方式中,凹槽的宽度可小于约50微米或大于约150微米。在各种实施方式中,所述多个凹槽26的深度可延伸到晶圆中约25与200微米之间,而在其他实施方式中,所述多个凹槽26的深度可小于约25微米或大于约200微米。
在各种实施方式中,以非限制性示例的方式,可使用等离子蚀刻、深反应离子蚀刻或湿法化学蚀刻来形成所述多个凹槽。在各种实施方式中,由德国斯图加特的罗伯特·博世公司(Robert Bosch GmbH,Stuttgart Germany)以商品名出售的工艺(“博世工艺”)可用于在晶圆16的第一侧28中形成多个凹槽26。
现在参见图4,示出了常规半导体晶圆的顶视图,其中多个锯切口围绕所述多个管芯。使用锯在半导体晶圆中切出凹槽总是会在管芯的器件侧面上及凹槽30的侧壁34中产生缺口和裂纹。如果裂纹和缺口传播到半导体管芯的器件部分中,则裂纹和缺口的存在有可能影响半导体封装的可靠性。由于锯切工艺涉及旋转刀片对管芯表面的摩擦,因此碎裂和破裂只可通过锯切加工变量(晶圆进给速度、刀片切缝宽度、切割深度、多个锯切口、刀片材料等)加以管理,但无法消除。此外,由于锯切工艺依赖于使晶圆在刀片下方经过,因此使用常规锯切技术时通常仅产生正方形和矩形尺寸的管芯。
参见图5,示出了其中蚀刻有多个凹槽的半导体晶圆的顶视图。与使用图4所示的常规锯切方法加工的管芯的外观不同,使用蚀刻技术形成的晶圆38中的所述多个凹槽36具有其中未表现出裂纹或缺口的边缘和侧壁40。由于不存在裂纹和缺口,使用蚀刻技术在半导体晶圆中形成多个凹槽有可能提高所得半导体封装的可靠性。
此外,使用蚀刻技术在晶圆中形成多个凹槽允许产生管芯的周边的不同形状。在各种实施方式中,相对于图3所述的第二光刻胶层可以以一定方式图案化,使得所形成的多个凹槽不会使管芯形成有矩形周边。例如,参见图6,示出了其中蚀刻有多个凹槽的半导体晶圆的第二实施方式的顶视图。在各种实施方式中,可在晶圆44中形成多个凹槽42。所述多个凹槽42可使最终管芯46形成有八边形的周边。参见图7,示出了其中蚀刻有多个凹槽的半导体晶圆的第三实施方式的顶视图。在各种实施方式中,可在晶圆50中形成多个凹槽48。所述多个凹槽48可使最终管芯52形成有倒圆矩形的周边。在其他实施方式中,可在晶圆中形成多个凹槽,所述多个凹槽使最终管芯形成有任何其他封闭几何形状的周边。
返回参见图3,在各种实施方式中,所形成的所述多个凹槽26具有两个基本上平行的侧壁,这两个侧壁基本上笔直地延伸到晶圆16的第一侧28中。在其他实施方式中,在晶圆16的第一侧28中形成两个或更多个阶梯式凹槽。可通过以下方式形成每个阶梯式凹槽:在晶圆中产生第一凹槽,然后在每个第一凹槽内形成第二更窄凹槽。
参见图3,用于形成半导体封装的方法的实施方式包括将第一模塑料54施加到所述多个凹槽26中及晶圆的第一侧上方。在各种实施方式中,如图3所示,第一模塑料54可覆盖电触点22。在其他实施方式中,第一模塑料54可不完全覆盖电触点22。以非限制性示例的方式,使用液体分配技术、传递模塑技术、印刷机模塑技术或压塑技术来施加第一模塑料。模塑料可为环氧树脂模塑料、丙烯酸模塑料或本文所公开的另一种类型的模塑料。
在各种实施方式中,第一模塑料54可锚定到多个凹槽26的多个侧壁56。现在参见图8,示出了其上施加有模塑件的晶圆的一部分的剖视图。现在参见图8A,示出了模塑件与管芯中形成的凹槽的侧壁之间的接合的放大剖视图。在各种实施方式中,可在所述多个凹槽内的每个凹槽的侧壁56中形成多个脊58。在特定实施方式中,从侧壁延伸的每个脊的高度为基本上0.2微米高,且间距为基本上一微米。因此,在凹槽为150微米深的实施方式中,凹槽的每个侧壁可有基本上150微米。在其他实施方式中,凹槽可高于或低于0.2微米,并且可具有大于或小于一微米的间距。脊可将第一模塑料54锚定到所述多个凹槽的侧壁56。在使用博世工艺蚀刻所述多个凹槽的各种实施方式中,该蚀刻工艺在经由深反应离子蚀刻的沉积/蚀刻循环来蚀刻所述多个凹槽的同时可在所述多个凹槽中形成脊,从而增加第一模塑料与每个凹槽的侧壁之间的粘附力。
返回参见图3,在第一模塑料54覆盖电触点22的各种实施方式中,可通过磨削第一模塑料来暴露电触点22。在各种实施方式中,可将晶圆16的第二侧60磨削到晶圆16的第一侧28中形成的所述多个凹槽26。这样,半导体晶圆的各个管芯被彼此切割。在各种实施方式中,以非限制性示例的方式,可使用机械抛光技术、化学蚀刻技术、机械抛光与化学蚀刻技术的组合或任何其他磨削技术来磨削晶圆16的第二侧60。
在各种实施方式中,可将第二模塑料62或层压树脂施加到晶圆16的第二侧60。在施加第二模塑料的实施方式中,模塑料可为本文所公开的任何类型的模塑料,并且可使用本文所公开的任何技术施加。
在各种实施方式中,如图3所示的工艺流程中示出,在磨削晶圆16的第二侧60并且施加第二模塑料之前磨削第一模塑料54以暴露电触点22。在其他实施方式中,可在磨削晶圆16的第二侧60并且施加第二模塑料之后磨削第一模塑料54以暴露电触点22。
用于制备半导体封装的方法包括将晶圆16切割成多个半导体封装64。可通过在初始形成所述多个凹槽26的地方切割或蚀刻穿过晶圆16,从而对该晶圆进行切割。以非限制性示例的方式,可通过使用锯、激光、水射流、等离子蚀刻、深反应离子蚀刻或化学蚀刻对该晶圆进行切割。在各种实施方式中,可使用博世工艺对晶圆16进行切割。用于对晶圆进行切割的方法可包括使用比用于形成所述多个凹槽26更薄的切口或蚀刻对晶圆进行切割。这样,第一模塑料将覆盖每个半导体封装64内的每个切割的管芯66的各侧面。具体地讲,在特定实施方式中,用于对每个半导体封装进行切割的锯宽度可介于20与40微米厚之间。半导体封装内的半导体管芯可由模塑料或层压树脂覆盖在半导体管芯的所有六个侧面上。
在各种实施方式中,每个半导体封装内的管芯的第一侧可包括周边,以非限制性示例的方式,该周边是矩形、八边形、具有倒圆边缘的矩形或任何其他封闭几何形状。
现在参见图10,示出了第三工艺流程,该第三工艺流程示出了半导体封装的形成的一部分。在各种实施方式中,用于形成半导体封装的方法包括提供晶圆72,该晶圆可为本文所公开的任何类型的晶圆衬底。在各种实施方式中,一个或多个金属垫74可耦接到晶圆72的第一侧76。以非限制性示例的方式,金属垫可包含铝、铜、镍、银、金、钛、或它们的任何组合或合金。
在各种实施方式中,第一钝化层78可耦接到晶圆72的第一侧76的一部分。第一钝化层78在各种实施方式中可为二氧化硅钝化层,但其可为多种多样其他类型的层中的任何一种,以非限制性示例的方式包括氮化硅、聚酰亚胺或另一种聚合物或沉积材料。在各种实施方式中,第二钝化层80可耦接到晶圆72的第一侧76的一部分。第二钝化层80可为氮化硅钝化层。第二钝化层可包含与第一钝化层相同的材料或不同的材料。
在各种实施方式中,第三层82可耦接到晶圆72的第一侧76的一部分。第三层可为聚酰亚胺、聚苯并恶唑、酚醛树脂、或聚酰亚胺、聚苯并恶唑和酚醛树脂的组合。在各种实施方式中,可在第三层上方及晶圆72的第一侧76上方形成金属晶种层84。金属晶种层84可为本文所公开的任何类型的金属层。在各种实施方式中,金属晶种层84可直接接触晶圆72的第一侧76的部分。在各种实施方式中,该方法包括在金属晶种层84上方形成第一光刻胶层86并使第一光刻胶层图案化。
在各种实施方式中,该方法包括形成耦接到金属晶种层84且在第一光刻胶层86内的电触点88。电触点88可为本文所公开的任何类型的电触点。在各种实施方式中,电触点88可包括第一层90和第二层92。在各种实施方式中,第一层90可包含铜,并且第二层92可包含锡、银、或锡与银的组合。在各种实施方式中,形成半导体封装的方法包括在形成电触点之后移除第一光刻胶层86并且蚀刻掉未由电触点覆盖的金属晶种层84的部分。
在各种实施方式中,形成半导体封装的方法包括在晶圆72的第一侧76上方形成第二光刻胶层94并使第二光刻胶层图案化。在各种实施方式中,第二光刻胶层覆盖电触点88,而在其他实施方式中,第二光刻胶层94不覆盖电触点88。第二光刻胶层94可用于在晶圆72中蚀刻多个凹槽96。该方法包括在晶圆中蚀刻所述多个凹槽之后移除第二光刻胶层94。
可以以施加图3中的第一模塑料的相同方式将第一模塑料施加到所述多个凹槽中及晶圆72的第一侧76上方。如图10所示的用于形成半导体封装的方法的其余部分可包括通过磨削来暴露电触点,将晶圆的背面磨削到所述多个凹槽,将第二模塑料或层压树脂施加到晶圆的背面,以及将晶圆切割成多个半导体封装。形成半导体封装的这些部分可与图3所示及本文此前所公开的用于形成半导体封装的相应部分相同或类似。
在各种实施方式中,由图10所示的方法制备的半导体封装可在半导体管芯与第一模塑料之间包括一个或多个金属垫、一个或多个钝化层、聚酰亚胺、酚醛树脂、聚苯并恶唑以及它们的任何组合。
参见图11至图14,示出了在图10所示的工艺中用于形成多个凹槽的替代方法。参见图11,示出了使用图案化的光刻胶层及聚酰亚胺、聚苯并恶唑和酚醛树脂中的一者并结合蚀刻工艺来形成多个凹槽的方法。在各种实施方式中,图案化的光刻胶层98可在掩模100上方,包括图案化的聚酰亚胺层、图案化的聚苯并恶唑层或图案化的酚醛树脂层。掩模100可在晶圆102上方。可使用本文所公开的任何蚀刻工艺,利用图案化的光刻胶层和掩模在晶圆102中形成凹槽104。
参见图12,示出了使用聚酰亚胺、聚苯并恶唑和酚醛树脂中的一者并结合本文所公开的任何蚀刻工艺来形成多个凹槽的方法。该方法可与图11所示的方法相同,不同之处在于图12所示的方法不包括用于在晶圆108中形成凹槽106的图案化的光刻胶层。
参见图13,示出了使用图案化的光刻胶层和钝化掩模来形成多个凹槽的方法。在各种实施方式中,图案化的光刻胶层110可在钝化掩模112上方。钝化掩模112可包括本文所公开的任何钝化层。钝化掩模112可在晶圆114上方。可使用图案化的光刻胶层110和钝化掩模112及本文所公开的任何蚀刻工艺在晶圆114中形成凹槽116。
参见图14,示出了使用钝化掩模并结合本文所公开的任何蚀刻方法来形成多个凹槽的方法。该方法可与图13所示的方法相同,不同之处在于图14所示的方法不包括用于在晶圆118中形成凹槽116的图案化的光刻胶层。
参见图15,示出了第四工艺流程,该第四工艺流程示出了半导体封装的形成。图15所示的用于形成半导体封装的方法包括提供晶圆120。在各种实施方式中,中间层122可耦接到晶圆120的第一侧124。在各种实施方式中,钝化层128可耦接到晶圆120。钝化层可为本文所公开的任何类型的钝化层。
在各种实施方式中,一个或多个电触点126可耦接到晶圆120。在各种实施方式中,这些电触点包括凸块130。这些电触点可包括耦接到凸块130的第一金属层132。第一金属层可包含本文所公开的任何金属。在特定实施方式中,第一金属层包含镍和金。电触点128可包括耦接到第一金属层132的第二金属层134。第二金属层134可包含本文所公开的任何金属。在特定实施方式中,第二金属层134包含铝。在各种实施方式中,阻焊层136可耦接在晶圆120上方。在其他实施方式中,不包括阻焊层。
在各种实施方式中,钝化层128可被图案化并且可直接接触晶圆120的部分。在此类实施方式中,图案化的钝化层或掩模可用于使用本文所公开的任何蚀刻工艺在晶圆120的第一侧124中蚀刻多个凹槽138。所述多个凹槽可使用本文所公开的任何方法蚀刻,并且可为本文此前公开的任何类型的凹槽。
在各种实施方式中,将第一模塑料140施加到所述多个凹槽138中及第一晶圆120上方。第一模塑料140可为本文所公开的任何模塑料,并且可使用本文所公开的任何技术施加。在各种实施方式中,第一模塑料140不完全覆盖电触点126,如图15所示。在其他实施方式中,第一模塑料不完全覆盖电触点126。在第一模塑料140不完全覆盖电触点126的实施方式中,可磨削第一模塑料以暴露电触点126。
在各种实施方式中,可使用本文所公开的任何磨削方法将与晶圆120的第一侧124相对的第二侧142磨削到所述多个凹槽。然后可将第二模塑料144或层压树脂施加到晶圆120的第二侧142。
随后可将晶圆120切割成多个半导体封装146。可使用本文所公开的任何技术对晶圆进行切割。具有半导体封装146的半导体管芯148可使所有六个侧面被模塑料覆盖。在其他实施方式中,管芯150的第六侧可由层压树脂覆盖。
在各种实施方式中,由图15所示的方法形成的半导体封装可包括耦接到晶圆的第一侧并且由第一模塑料覆盖的阻焊层、钝化层、中间层、或阻焊层、钝化层和中间层的组合。
形成半导体封装的方法的实施方式可包括将第一模塑料施加到所述多个凹槽之中及晶圆的第一侧上方。可使用印刷机模塑技术和压塑技术中的一者施加第一模塑料。
封装内的管芯的第一侧的周边可基本上为八边形或具有倒圆拐角的矩形。
形成半导体封装的方法的实施方式可包括在晶圆的第一侧上形成金属层,将第一光刻胶层施加在金属层上,对第一光刻胶层进行图案化,使用第一光刻胶层形成耦接到金属层的电触点,移除第一光刻胶层,蚀刻金属层,以及在晶圆的第一侧中蚀刻多个凹槽。
可在所述多个凹槽的蚀刻期间使用深反应离子蚀刻技术形成所述多个凹槽。
可使用聚酰亚胺、聚苯并恶唑和酚醛树脂中的一者在晶圆的第一侧中蚀刻所述多个凹槽。
可使用钝化掩模在晶圆的第一侧中蚀刻所述多个凹槽。
阻焊层、钝化层、中间层、或阻焊层、钝化层和中间层的组合可耦接到晶圆的第一侧并且可由第一模塑料覆盖。
半导体封装的实施方式可包括具有第一侧、第二侧、第三侧、第四侧、第五侧和第六侧的管芯,该管芯的第一侧包括多个电触点。第六侧可与第一侧相对。
管芯的第一侧的周边可包括八边形和倒圆矩形中的一者。
所述多个电触点可包含镍、金和铝的组合及锡、银和铜的组合之一。
在以上描述中提到半导体封装的具体实施方式以及实施部件、子部件、方法和子方法的地方,应当显而易见的是,可在不脱离其实质的情况下作出多种修改,并且这些实施方式、实施部件、子部件、方法和子方法可应用于其他半导体封装。
Claims (10)
1.一种形成半导体封装的方法,包括:
在晶圆的第一侧上形成多个电触点;
将光刻胶层施加到所述晶圆的所述第一侧;
对所述光刻胶层进行图案化;
使用所述光刻胶层在所述晶圆的所述第一侧中蚀刻多个凹槽;
将第一模制化合物施加到所述多个凹槽中及所述晶圆的所述第一侧上方;
将与所述晶圆的所述第一侧相对的所述晶圆的第二侧磨削到在所述晶圆的所述第一侧中形成的所述多个凹槽;
将第二模制化合物和层压树脂中的一者施加到所述晶圆的第二侧;以及
将所述晶圆切割成多个半导体封装,其中由所述第一模制化合物、所述第二模制化合物和所述层压树脂中的一者覆盖每个半导体封装的六个侧面。
2.根据权利要求1所述的方法,其中使用所述光刻胶层及聚酰亚胺、聚苯并恶唑和酚醛树脂中的一者在所述晶圆的所述第一侧中蚀刻所述多个凹槽。
3.根据权利要求1所述的方法,其中使用所述光刻胶层和钝化掩模在所述晶圆的所述第一侧中蚀刻所述多个凹槽。
4.根据权利要求1所述的方法,其中阻焊层、钝化层、中间层及阻焊层、钝化层和中间层的组合中的一者耦接到所述晶圆的所述第一侧并且由所述第一模制化合物覆盖。
5.一种形成半导体封装的方法,包括:
在晶圆的第一侧上形成金属层;
将第一光刻胶层施加在所述金属层上;
对所述第一光刻胶层进行图案化;
使用所述第一光刻胶层形成耦接到所述金属层的电触点;
移除所述第一光刻胶层;
蚀刻所述金属层;
在所述晶圆的所述第一侧中蚀刻多个凹槽;
将第一模制化合物施加到所述多个凹槽中、所述电触点上方及所述晶圆的所述第一侧上方;
通过磨削所述第一模制化合物而透过所述第一模塑料暴露所述电触点;
将与所述晶圆的所述第一侧相对的所述晶圆的第二侧磨削到在所述晶圆的所述第一侧中形成的所述多个凹槽;
将第二模制化合物和层压树脂中的一者施加到所述晶圆的所述第二侧;
将所述晶圆切割成多个半导体封装,其中每个半导体封装由第一模制化合物、所述第二模制化合物和层压树脂中的一者覆盖在每个半导体封装的所述第一侧、所述第二侧、第三侧、第四侧、第五侧和第六侧上。
6.根据权利要求5所述的方法,其中每个半导体封装内的管芯的第一侧包括周边,所述周边是八边形和具有倒圆边缘的矩形中的一者。
7.根据权利要求5所述的方法,其中所述第一模制化合物通过在所述多个凹槽的侧壁中形成的多个脊锚定到所述多个凹槽的侧壁。
8.一种半导体封装,包括:
管芯,所述管芯包括第一侧、第二侧、第三侧、第四侧、第五侧和第六侧,所述管芯的所述第一侧包括多个电触点;
第一模制化合物,所述第一模制化合物覆盖所述管芯的所述第一侧、所述管芯的所述第二侧、所述管芯的所述第三侧、所述管芯的所述第四侧和所述管芯的所述第五侧,其中所述多个电触点延伸穿过所述第一模制化合物中的多个开口;以及
覆盖所述管芯的所述第六侧的第二模制化合物和层压树脂中的一者,
其中在所述管芯的切割之后不存在所述管芯的所述第一侧的管芯碎裂。
9.根据权利要求8所述的半导体封装,其中所述第一模制化合物通过在所述管芯的所述第二侧、所述管芯的所述第三侧、所述管芯的所述第四侧和所述管芯的所述第五侧中形成的多个脊锚定到所述管芯的所述第二侧、所述管芯的所述第三侧、所述管芯的所述第四侧和所述管芯的所述第五侧。
10.根据权利要求8所述的半导体封装,还包括耦接到所述晶圆的所述第一侧并且由所述第一模制化合物覆盖的阻焊层、钝化层、中间层及阻焊层、钝化层和中间层的组合中的一者。
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