CN215069959U - Lead frame for arranging chip and packaging body - Google Patents
Lead frame for arranging chip and packaging body Download PDFInfo
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- CN215069959U CN215069959U CN202120849044.7U CN202120849044U CN215069959U CN 215069959 U CN215069959 U CN 215069959U CN 202120849044 U CN202120849044 U CN 202120849044U CN 215069959 U CN215069959 U CN 215069959U
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Abstract
The utility model provides a lead frame and a packaging body for arranging chips, which comprises a first substrate, a second substrate arranged in the middle of the upper part of the first substrate and a plurality of base islands arranged on the second substrate and used for attaching chips; a plurality of low-voltage pins and a plurality of high-voltage pins are respectively arranged at two side parts of the first substrate; the width of the high-voltage pin is larger than that of the low-voltage pin; a plurality of strip-shaped through holes are formed above the high-voltage pins in a matrix manner; a plurality of strip-shaped heat dissipation grooves are formed in one side, close to the low-voltage pins and one side, close to the high-voltage pins, of the first substrate; the low-voltage pins and the high-voltage pins are arranged across the heat dissipation grooves, and in the practical application process, due to the fact that the low-voltage pins and the high-voltage pins with different sizes are arranged and matched with the heat dissipation grooves, the safety degree of product operation can be well guaranteed.
Description
[ technical field ]
The utility model relates to a semiconductor product technical field especially relates to a structural design is reasonable, and the outstanding lead frame and the packaging body that are used for arranging the chip of application effect.
[ background art ]
With the strong growth of the semiconductor industry in China, the IC manufacturing industry is rapidly developing. The package is an important part of the whole integrated circuit manufacturing process, has the functions of heat dissipation and protection, and seals the chip to isolate external pollution and damage of external force to the chip.
The chip type package has many advantages of small package volume, low cost, high production efficiency and the like, and is popular with terminal customers, and therefore, a large number of chip type package structures, such as SOP, SOT, DFN, QFN, CPC and the like, are independently developed by various packaging factories.
One of the problems of the existing chip lead frame is that the heat dissipation performance is poor, and the better popularization and application of the product are restricted.
[ contents of utility model ]
For overcoming the problem that prior art exists, the utility model provides a structural design is reasonable, uses the outstanding lead frame and the packaging body that are used for arranging the chip of effect.
The utility model provides a lead frame for arranging chips, which comprises a first substrate, a second substrate arranged in the middle of the upper part of the first substrate and a plurality of base islands arranged on the second substrate and used for attaching chips; a plurality of low-voltage pins and a plurality of high-voltage pins are respectively arranged at two side parts of the first substrate; the width of the high-voltage pin is larger than that of the low-voltage pin; a plurality of strip-shaped through holes are formed above the high-voltage pins in a matrix manner; a plurality of strip-shaped heat dissipation grooves are formed in one side, close to the low-voltage pins and one side, close to the high-voltage pins, of the first substrate; the low-voltage pin and the high-voltage pin are arranged across the heat dissipation groove.
Preferably, the plurality of low-voltage pins and the plurality of high-voltage pins are symmetrically arranged at two side parts of the first substrate; the chip on the second substrate is electrically connected with the low-voltage pin and the high-voltage pin through metal wires.
Preferably, the chip attached to the base island is an integrated circuit chip; and a discrete device is also arranged on the base island and comprises a diode, a triode, an MOS (metal oxide semiconductor) tube or a thyristor.
Preferably, the first substrate is of a square structure as a whole; and the length of the heat dissipation groove is longer than the whole width of the low-voltage pin and the high-voltage pin.
Preferably, the low-voltage pins and the high-voltage pins are in corner structures at the side parts of the first substrate.
A packaging body comprises a plastic packaging body and the lead frame.
Compared with the prior art, the lead frame and the packaging body for arranging the chips are characterized in that a first substrate 11, a second substrate 12 arranged in the middle of the upper part of the first substrate 11 and a plurality of base islands (121/122/123) for attaching the chips, which are arranged on the second substrate 12, are arranged at the same time; a plurality of low-voltage pins 14 and a plurality of high-voltage pins 13 are respectively arranged at two side parts of the first substrate 11; the width of the high-voltage pin 13 is larger than that of the low-voltage pin 14; a plurality of strip-shaped through holes are formed above the high-voltage pins 13 in a matrix manner; a plurality of strip-shaped heat dissipation grooves 15 are further formed in one side, close to the low-voltage pins 14 and the high-voltage pins 13, of the first substrate 11; the low-voltage pins 14 and the high-voltage pins 13 are arranged across the heat dissipation groove 15, and in the practical application process, because the low-voltage pins 14 and the high-voltage pins 13 with different sizes are arranged and matched with the heat dissipation groove 15, the safety degree of product operation can be better ensured.
[ description of the drawings ]
Fig. 1 is a schematic perspective view of a lead frame for arranging chips according to the present invention.
[ detailed description of the invention ]
To make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, a lead frame 1 for chip arrangement according to the present invention includes a first substrate 11, a second substrate 12 disposed at a middle position of an upper portion of the first substrate 11, and a plurality of base islands (121/122/123) disposed on the second substrate 12 for attaching chips; a plurality of low-voltage pins 14 and a plurality of high-voltage pins 13 are respectively arranged at two side parts of the first substrate 11; the width of the high-voltage pin 13 is larger than that of the low-voltage pin 14; a plurality of strip-shaped through holes are formed above the high-voltage pins 13 in a matrix manner; a plurality of strip-shaped heat dissipation grooves 15 are further formed in one side, close to the low-voltage pins 14 and the high-voltage pins 13, of the first substrate 11; the low-voltage pin 14 and the high-voltage pin 13 are arranged across the heat dissipation groove 15.
The method comprises the steps of simultaneously arranging a first substrate 11, a second substrate 12 arranged in the middle of the upper part of the first substrate 11 and a plurality of base islands (121/122/123) for attaching chips, which are arranged on the second substrate 12; a plurality of low-voltage pins 14 and a plurality of high-voltage pins 13 are respectively arranged at two side parts of the first substrate 11; the width of the high-voltage pin 13 is larger than that of the low-voltage pin 14; a plurality of strip-shaped through holes are formed above the high-voltage pins 13 in a matrix manner; a plurality of strip-shaped heat dissipation grooves 15 are further formed in one side, close to the low-voltage pins 14 and the high-voltage pins 13, of the first substrate 11; the low-voltage pins 14 and the high-voltage pins 13 are arranged across the heat dissipation groove 15, and in the practical application process, because the low-voltage pins 14 and the high-voltage pins 13 with different sizes are arranged and matched with the heat dissipation groove 15, the safety degree of product operation can be better ensured.
Preferably, the low voltage pins 14 and the high voltage pins 13 are symmetrically disposed on two side portions of the first substrate 11; the chip on the second substrate 12 is electrically connected to the low voltage pin 14 and the high voltage pin 13 through metal wires.
Preferably, the chip attached to the base island (121/122/123) is an integrated circuit chip; and discrete devices are also arranged on the base island (121/122/123), and the discrete devices comprise diodes, triodes, MOS (metal oxide semiconductor) tubes or thyristors.
Preferably, the first substrate 11 is a square structure as a whole; and the length of the heat dissipation groove 15 is longer than the whole width of the low voltage pin 14 and the high voltage pin 13.
Preferably, the low voltage pins 14 and the high voltage pins 13 are in a corner structure at the side of the first substrate 11.
A package body comprises a plastic package body and the lead frame 1.
The press pins and the high-voltage pins are respectively arranged on two sides of the base island (121/122/123), so that the situation that the pins are mutually broken down due to large high-low voltage difference is avoided, and the requirements of packaging or reliability are further met.
Compared with the prior art, the lead frame and the package 1 for arranging the chips of the present invention are formed by simultaneously providing a first substrate 11, a second substrate 12 disposed at a middle position of an upper portion of the first substrate 11, and a plurality of base islands (121/122/123) for attaching the chips disposed on the second substrate 12; a plurality of low-voltage pins 14 and a plurality of high-voltage pins 13 are respectively arranged at two side parts of the first substrate 11; the width of the high-voltage pin 13 is larger than that of the low-voltage pin 14; a plurality of strip-shaped through holes are formed above the high-voltage pins 13 in a matrix manner; a plurality of strip-shaped heat dissipation grooves 15 are further formed in one side, close to the low-voltage pins 14 and the high-voltage pins 13, of the first substrate 11; the low-voltage pins 14 and the high-voltage pins 13 are arranged across the heat dissipation groove 15, and in the practical application process, because the low-voltage pins 14 and the high-voltage pins 13 with different sizes are arranged and matched with the heat dissipation groove 15, the safety degree of product operation can be better ensured.
The above-mentioned embodiments of the present invention do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (6)
1. A lead frame for arranging chips, characterized in that: the chip-attaching structure comprises a first substrate, a second substrate arranged in the middle of the upper part of the first substrate and a plurality of base islands arranged on the second substrate and used for attaching chips; a plurality of low-voltage pins and a plurality of high-voltage pins are respectively arranged at two side parts of the first substrate; the width of the high-voltage pin is larger than that of the low-voltage pin; a plurality of strip-shaped through holes are formed above the high-voltage pins in a matrix manner; a plurality of strip-shaped heat dissipation grooves are formed in one side, close to the low-voltage pins and one side, close to the high-voltage pins, of the first substrate; the low-voltage pin and the high-voltage pin are arranged across the heat dissipation groove.
2. A lead frame for arranging chips according to claim 1, wherein: the plurality of low-voltage pins and the plurality of high-voltage pins are symmetrically arranged at two side parts of the first substrate; the chip on the second substrate is electrically connected with the low-voltage pin and the high-voltage pin through metal wires.
3. A lead frame for arranging chips according to claim 1, wherein: the chip attached to the base island is an integrated circuit chip; and a discrete device is also arranged on the base island and comprises a diode, a triode, an MOS (metal oxide semiconductor) tube or a thyristor.
4. A lead frame for arranging chips according to claim 1, wherein: the first substrate is integrally in a square structure; and the length of the heat dissipation groove is longer than the whole width of the low-voltage pin and the high-voltage pin.
5. A lead frame for arranging chips according to claim 4, wherein: the low-voltage pin and the high-voltage pin are in corner structures at the side edge parts of the first substrate.
6. A package, characterized in that: comprising a plastic package body and a lead frame according to any of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120849044.7U CN215069959U (en) | 2021-04-23 | 2021-04-23 | Lead frame for arranging chip and packaging body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120849044.7U CN215069959U (en) | 2021-04-23 | 2021-04-23 | Lead frame for arranging chip and packaging body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215069959U true CN215069959U (en) | 2021-12-07 |
Family
ID=79112826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120849044.7U Active CN215069959U (en) | 2021-04-23 | 2021-04-23 | Lead frame for arranging chip and packaging body |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215069959U (en) |
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2021
- 2021-04-23 CN CN202120849044.7U patent/CN215069959U/en active Active
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