CN220106521U

CN220106521U - Integrated package IPM (intelligent power module) packaging structure for driving multiple MOS (metal oxide semiconductor) chips by IC (integrated circuit) chips

Info

Publication number: CN220106521U
Application number: CN202321589411.XU
Authority: CN
Inventors: 蔡择贤; 曹周; 陈勇; 饶锡林; 孙少林; 张怡; 雷楚宜; 曾文杰
Original assignee: Guangdong Chippacking Technology Co ltd
Current assignee: Guangdong Chippacking Technology Co ltd
Priority date: 2023-06-21
Filing date: 2023-06-21
Publication date: 2023-11-28
Anticipated expiration: 2033-06-21

Abstract

The utility model relates to an Integrated Circuit (IC) chip driving multi-MOS chip sealing IPM packaging structure, which comprises an IC chip, a plurality of first MOS chips, a plurality of second MOS chips, a first base island, a second base island, a plurality of third base islands, a plurality of pins and a plurality of bridge jumper wires, wherein the IC chip is arranged on the first base island, the plurality of first MOS chips are jointly arranged on the second base island, the plurality of second MOS chips are respectively and independently arranged on the plurality of third base islands, and the source electrodes of the plurality of first MOS chips are electrically connected with the bridge jumper wires through metal wires, and the bridge jumper wires are electrically connected with the IC chip through the metal wires. Through addding a plurality of jumper wires that cross the bridge, the length of the single metal wire that corresponds of the farther first MOS chip of distance IC chip shortens by a wide margin, and the shape of metal wire is easier to control, and the overall arrangement design of metal wire is also easier, is difficult for scattering, is difficult for the mutual influence between the metal wire.

Description

Integrated package IPM (intelligent power module) packaging structure for driving multiple MOS (metal oxide semiconductor) chips by IC (integrated circuit) chips

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a sealing IPM packaging structure for driving a plurality of MOS chips by an IC chip.

Background

The intelligent power module (IntelligentPowerModule, IPM) is a novel control module integrating an insulated gate bipolar transistor chip and a driving circuit thereof, has the advantages of low cost, miniaturization, high reliability, easy use and the like, and is widely applied to the fields of variable frequency home appliances, inverter power supplies, industrial control and the like. In the prior art, the IPM package structure comprises an IC chip and a plurality of MOS chips, the IC chip is located at one corner of the package structure, the MOS chips are arranged around the IC chip, and the MOS chips are directly and electrically connected with the IC chip through metal wires.

Disclosure of Invention

The utility model aims to provide a sealed IPM (intelligent power module) packaging structure for driving a plurality of MOS (metal oxide semiconductor) chips by an IC (integrated circuit) chip, which solves the technical problems that wires are scattered and are easy to influence each other.

The utility model is realized in the following way: the utility model provides a compound encapsulation IPM packaging structure of IC chip drive a plurality of MOS chips, includes IC chip, a plurality of first MOS chip, a plurality of second MOS chip, first base island, second base island, a plurality of third base island and a plurality of pin, the IC chip sets up on first base island, a plurality of first MOS chip set up jointly on the second base island, a plurality of second MOS chip set up respectively on a plurality of third base island independently, the grid of first MOS chip passes through the metal wire and is directly connected with the IC chip electricity, the grid of second MOS chip passes through the metal wire and is directly connected with the IC chip electricity, the source of second MOS chip passes through the metal wire and is directly connected with the pin electricity, compound encapsulation IPM packaging structure still includes a plurality of bridge jumper, the source of a plurality of first MOS chips passes through the metal wire and is connected with bridge jumper electricity first, bridge jumper wire and IC chip electricity connection.

The source electrode of the first MOS chip is electrically connected with the bridge jumper wire through a plurality of metal wires.

And the bridge jumper wire is electrically connected with the IC chip through a plurality of metal wires.

The number of the first MOS chips, the second MOS chips and the bridge jumper wires is three, the three first MOS chips are arranged side by side, and the three second MOS chips are also arranged side by side.

The bridge-crossing jumpers are integrally connected with the third base islands respectively, the other ends of the bridge-crossing jumpers are led out outwards to form pins, and the bridge-crossing jumpers are located between the IC chip and the first MOS chip.

And a plurality of independent pins are further arranged on the outer side of the third base island, and are respectively and electrically connected with the source electrode of the second MOS chip through metal wires.

The beneficial effects of the utility model are as follows: the sealed IPM packaging structure is characterized in that the sources of the first MOS chips are electrically connected with the bridge jumper wires through metal wires, and the bridge jumper wires are electrically connected with the IC chips through the metal wires, so that the length of a single metal wire corresponding to the first MOS chips far away from the IC chips is greatly shortened, the shape of the metal wire is easier to control, the layout design of the metal wire is easier, the metal wires are not easy to scatter, and the metal wires are not easy to influence each other.

Drawings

FIG. 1 is a top view of a encapsulated IPM package according to the present utility model;

fig. 2 is a schematic layout diagram of an IC chip, a first MOS chip, and a second MOS chip according to the present utility model;

fig. 3 is a schematic diagram of a layout of a first base island, a second base island, a third base island, pins and a jumper bridge according to the present utility model.

Wherein, 1, IC chip; 2. a first MOS chip; 3. a second MOS chip; 4. a first island; 5. a second island; 6. a third island; 7. pins; 8. a metal wire; 9. and (5) a bridge jumper wire.

Detailed Description

The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

As an embodiment of the integrated and sealed IPM package structure for driving multiple MOS chips by using an IC chip according to the present utility model, as shown in fig. 1 to 3, the integrated and sealed IPM package structure includes an IC chip 1, multiple first MOS chips 2, multiple second MOS chips 3, a first base island 4, a second base island 5, multiple third base islands 6, and multiple pins 7, where the IC chip 1 is disposed on the first base island 4, the multiple first MOS chips 2 are disposed on the second base island 5 together, the multiple second MOS chips 3 are separately disposed on the multiple third base islands 6, respectively, the gates of the first MOS chips 2 are directly electrically connected to the IC chip 1 through metal wires 8, the gates of the second MOS chips 3 are directly electrically connected to the IC chip 1 through metal wires 8, the sources of the second MOS chips 3 are directly electrically connected to pins 7 through metal wires 8, and the integrated and sealed IPM package structure further includes multiple bridge jumpers 9, and the sources of the multiple first MOS chips 2 are electrically connected to the IC chip 1 through jumper wires 9 through metal wires 8.

The sealed IPM packaging structure is characterized in that the sources of the first MOS chips 2 are electrically connected with the bridge jumper 9 through the metal wires 8, and the bridge jumper 9 is electrically connected with the IC chip 1 through the metal wires 8, so that the length of a single metal wire 8 corresponding to the first MOS chip 2 far away from the IC chip 1 is greatly shortened, the shape of the metal wire 8 is easier to control, the layout design of the metal wires 8 is easier, the metal wires 8 are not easy to scatter, and the metal wires 8 are not easy to influence each other.

In this embodiment, the source of the first MOS chip 2 is electrically connected to the bridge jumper 9 through a plurality of metal wires 8. By increasing the number of bond wires of the metal lines 8, the internal resistance and parasitic inductance of the packaged product can be reduced.

In the present utility model, the jumper wire 9 may be electrically connected to the IC chip 1 through a plurality of metal wires 8, so as to reduce the internal resistance and parasitic inductance of the packaged product. If the pad area on the IC chip 1 is not large enough, a single metal line 8 is used to make the electrical connection.

In this embodiment, the number of the first MOS chips 2, the second MOS chips 3 and the bridge jumper 9 is three, the three first MOS chips 2 are arranged side by side, and the three second MOS chips 3 are also arranged side by side, so that the first MOS chips 2 and the second MOS chips 3 are regularly arranged, the gaps are reasonable, and the gap requirements between the chips are met.

In this embodiment, the plurality of bridge-crossing jumpers 9 are integrally connected with the plurality of third islands 6, and the other ends of the bridge-crossing jumpers 9 are led out to form pins 7, and the bridge-crossing jumpers 9 are located between the IC chip 1 and the first MOS chip 2, so that the lengths of the two metal wires 8 are relatively short, and the sum of the lengths of the two metal wires 8 is the shortest; the W, V, U ends on the packaged product can be respectively led out from the pins 7 at the jumper 9 of the bridge, so that the design of the PCB ends is facilitated.

In this embodiment, a plurality of independent pins 7 are further disposed on the outer side of the third base island 6, and the plurality of independent pins 7 are electrically connected to the source of the second MOS chip 3 through metal wires 8, respectively. Under the pressure-resistant requirement of guaranteeing the high-voltage area, through LF arrangement, the output space of VR2 and VR3 is vacated on the right side of the third base island 6, so that the IO ends of the original uniform electrical property can be electrically separated.

The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.

Claims

1. The utility model provides a compound encapsulation IPM packaging structure of IC chip drive a plurality of MOS chips, includes IC chip, a plurality of first MOS chip, a plurality of second MOS chip, first base island, second base island, a plurality of third base island and a plurality of pin, the IC chip sets up on first base island, a plurality of first MOS chip set up jointly on the second base island, a plurality of second MOS chip set up respectively on a plurality of third base island independently, the grid of first MOS chip passes through the metal wire and is directly connected with the IC chip electricity, the grid of second MOS chip passes through the metal wire and is directly connected with the IC chip electricity, the source of second MOS chip passes through the metal wire and is directly connected with the pin electricity, its characterized in that still includes a plurality of bridge jumper, the source of a plurality of first MOS chips passes through the metal wire and is connected with bridge jumper electricity first, bridge jumper wire and then pass through the metal wire and IC chip electricity connection.

2. The IPM package structure of claim 1, wherein the source of the first MOS chip is electrically connected to the bridge jumper via a plurality of wires.

3. The IPM package structure of claim 2, wherein the jumper wire is electrically connected to the IC chip via a plurality of wires.

4. The IPM package structure of claim 1, wherein the number of the first MOS chips, the second MOS chips and the bridge jumper is three, the three first MOS chips are arranged side by side, and the three second MOS chips are also arranged side by side.

5. The IPM package structure of claim 4, wherein the bridge jumpers are integrally connected with the third islands, and the other ends of the bridge jumpers are led out to form pins, and the bridge jumpers are located between the IC chip and the first MOS chip.

6. The IPM package structure of claim 5, wherein a plurality of independent pins are further disposed on an outer side of the third base island, and the plurality of independent pins are electrically connected to the source of the second MOS chip through metal wires, respectively.