CN212967703U - Chip packaging structure and digital isolator - Google Patents
Chip packaging structure and digital isolator Download PDFInfo
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- CN212967703U CN212967703U CN202022403234.4U CN202022403234U CN212967703U CN 212967703 U CN212967703 U CN 212967703U CN 202022403234 U CN202022403234 U CN 202022403234U CN 212967703 U CN212967703 U CN 212967703U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a chip package structure and digital isolator, chip package structure includes packaging frame and encapsulates the chip that closes on packaging frame, packaging frame is including the first base island and the second base island that the separation set up, and the side correspondence of first base island and second base island is equipped with a plurality of mutual separations's first pin and second pin, closes and seals the chip and include first chip and second chip as an organic whole, and rewiring layer including the encapsulation, first chip and second chip are located first base island and second base island top respectively, and first chip and second chip pass through rewiring layer electric connection, pass through rewiring layer and first connecting wire electric connection between first chip and the first pin, pass through rewiring layer and second connecting wire electric connection between second chip and the second pin. The utility model provides the high stability of packaging structure and device performance has reduced the risk that conventional routing welding process brought, is applicable to in devices such as two chip digital isolation wares.
Description
Technical Field
The utility model belongs to the technical field of the chip package, concretely relates to chip packaging structure and digital isolator.
Background
In a semiconductor circuit packaging structure, particularly a digital isolator, two chips of a logic high level and a logic low level need to be sealed, the two chips need to be connected through a wire, and when the digital isolator works, the two chips are respectively in different voltage domains.
Referring to fig. 1, a chip package structure in the prior art is shown, which includes a package frame and two chips, where the package frame includes a first base island 11 ' and a second base island 12 ' that are separately arranged, a plurality of first leads 21 ' and second leads 22 ' that are separated from each other are correspondingly disposed at sides of the first base island 11 ' and the second base island 12 ', a first chip 31 ' is packaged on the first base island 11 ', a second chip 32 ' is packaged on the second base island 12 ', the first chip 31 ' and the second chip 32 ' are electrically connected by a first connection line 41 ' (a middle bridge line), the first chip 31 ' and the first leads 21 ' are electrically connected by a second connection line 42 ', and the second chip 32 ' and the second leads 22 ' are electrically connected by a third connection line 43 '. Further, the package frame further includes a first supporting leg 111 'connected to the first base island 11' and a second supporting leg 121 'connected to the second base island 12'.
In the chip packaging structure in the prior art, a supporting leg is used for supporting the chip to connect the base island, and in the process implementation, the problems of insufficient soldering and even deformation caused by unstable structure generally exist, so that the packaging process and the stability of product performance are influenced.
Therefore, it is desirable to provide a chip package structure and a digital isolator.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a chip package structure and digital isolator to promote chip package structure's stability.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a chip packaging structure comprises a packaging frame and a sealing chip packaged on the packaging frame, wherein the packaging frame comprises a first base island and a second base island which are separately arranged, a plurality of first pins and second pins which are mutually separated are correspondingly arranged at the sides of the first base island and the second base island, the sealing chip comprises a first chip, a second chip and a rewiring layer which are packaged into a whole, the first chip and the second chip are respectively positioned above the first base island and the second base island, the first chip and the second chip are electrically connected through the rewiring layer, the first chip and the first pin are electrically connected with a first connecting wire through the rewiring layer, and the second chip and the second pin are electrically connected with a second connecting wire through the rewiring layer.
In one embodiment, the encapsulated chip includes:
a first chip and a second chip;
the packaging body is used for packaging the first chip and the second chip, and the upper surface of the first chip and the upper surface of the second chip are exposed to the outside of the packaging body;
the first insulating layer is positioned on the upper surfaces of the packaging body, the first chip and the second chip, and a plurality of first windows penetrating through the upper surface of the first chip and a plurality of second windows penetrating through the upper surface of the second chip are formed on the first insulating layer;
the rewiring layer is positioned on the first insulating layer and in the first window and the second window, and is electrically connected with the first chip and the second chip respectively;
and a second insulating layer on the rewiring layer.
In an embodiment, a plurality of third windows penetrating through the first chip-side redistribution layer and a plurality of fourth windows penetrating through the second chip-side redistribution layer are formed on the second insulating layer.
In one embodiment, the first chip is electrically connected to the first lead through a first connection line penetrating through the third window, and the second chip is electrically connected to the second lead through a third connection line penetrating through the fourth window.
In an embodiment, the upper surface of the first chip and the upper surface of the second chip are disposed flush with the upper surface of the package, or the upper surface of the first chip and the upper surface of the second chip protrude from the upper surface of the package.
In one embodiment, the package frame further includes a first supporting leg connected to the first base island and a second supporting leg connected to the second base island.
In an embodiment, the first chip is electrically connected to the first supporting legs through first connecting lines penetrating through the third window, and the second chip is electrically connected to the second supporting legs through third connecting lines penetrating through the fourth window.
The utility model discloses still another embodiment provides the technical scheme as follows:
a digital isolator comprises the chip packaging structure.
Compared with the prior art, the utility model has the advantages of it is following:
the utility model discloses a restructure chip structure, close first chip and second chip and seal into an entirety and encapsulate with the encapsulation frame, with two base islands fixed connection in the encapsulation frame, improved the stability of packaging structure and device performance, be applicable to in devices such as two-chip digital isolator;
the rewiring layer in the sealing chip is used for electrically connecting the first chip and the second chip, an intermediate bridging line is not needed, the structure of the device is optimized, and the risk caused by the conventional wire bonding process is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a chip package structure in the prior art;
fig. 2 is a schematic structural diagram of a chip package structure according to an embodiment of the present invention;
fig. 3 is a schematic plan view of a package frame according to an embodiment of the present invention;
fig. 4a and 4b are a schematic plan view and a schematic cross-sectional view of a sealed chip according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of a chip packaging method according to an embodiment of the present invention;
fig. 6a to 6g are process flow diagrams of sealing the first chip and the second chip to form a sealed chip according to an embodiment of the present invention;
fig. 7 is a schematic view of a connection structure between a connection line and a chip according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. However, the present invention is not limited to the embodiments, and the structural, method, or functional changes made by those skilled in the art according to the embodiments are all included in the scope of the present invention.
In the various illustrations of the present application, certain dimensions of structures or portions are exaggerated relative to other structures or portions for ease of illustration and, thus, are provided only to illustrate the basic structure of the subject matter of the present application.
Terms such as "upper," "lower," "above," "over," and the like, used herein to denote relative spatial positions, are used for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative positional terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" other elements or features would then be oriented "below" the other elements or features.
The utility model discloses a chip package structure, including encapsulation frame and the closed chip of encapsulation on encapsulation frame, encapsulation frame is including first base island and the second base island that the separation set up, the side correspondence of first base island and second base island is equipped with a plurality of mutual separations's first pin and second pin, closed chip is including encapsulating first chip and second chip as an organic whole, and rewiring layer, first chip and second chip are located first base island and second base island top respectively, first chip passes through rewiring layer electric connection with the second chip, through rewiring layer and first connecting wire electric connection between first chip and the first pin, through rewiring layer and second connecting wire electric connection between second chip and the second pin.
The utility model also discloses a digital isolator, it includes foretell chip package structure.
The present invention will be further described with reference to specific embodiments.
Referring to fig. 2 in combination with fig. 3, fig. 4a and fig. 4b, a chip package structure according to an embodiment of the present invention includes a package frame 10 and a sealing chip 20 packaged on the package frame.
Referring to fig. 3, the package frame 10 in this embodiment includes a first base island 111 and a second base island 112 separately arranged, and a plurality of first pins 121 and second pins 122 separated from each other are correspondingly arranged beside the first base island 111 and the second base island 112. Preferably, the package frame 10 further includes a first supporting leg 131 connected to the first base island 111, and a second supporting leg 132 connected to the second base island 112.
Referring to fig. 4a and 4b in combination with fig. 6a to 6g, the sealed chip 20 includes:
the chip package comprises a first chip 21 and a second chip 22, wherein the first chip 21 and the second chip 22 are packaged into a whole;
a package 201 for packaging the first chip 21 and the second chip 22, wherein an upper surface of the first chip 21 and an upper surface of the second chip 22 are exposed to the outside of the package 201;
a first insulating layer 202 disposed on the upper surfaces of the package body 201, the first chip 21 and the second chip 22, wherein a plurality of first windows 2021 penetrating the upper surface of the first chip and a plurality of second windows 2022 penetrating the upper surface of the second chip are formed on the first insulating layer 202;
the rewiring layer 203 is positioned on the first insulating layer 202 and in the first window 2021 and the second window 2022, and the rewiring layer 203 is electrically connected with the upper surfaces of the first chip 21 and the second chip 22 respectively;
the second insulating layer 204 is located on the redistribution layer 203, and preferably, a plurality of third windows 2041 penetrating through the first chip-side redistribution layer and a plurality of fourth windows 2042 penetrating through the second chip-side redistribution layer are formed on the second insulating layer 204 in this embodiment.
Of course, in other embodiments, the upper surface of the first chip 21 and the upper surface of the second chip 22 may protrude from the upper surface of the package 201, and the technical solution that the redistribution layer electrically connects the first chip and the second chip is within the protection scope.
In this embodiment, the upper surface of the first chip 21 and the upper surface of the second chip 22 are electrically connected through the redistribution layer 203, and the lower surface of the package body 201 is packaged on the first base island 111 and the second base island 112.
The chip is characterized in that the external pins are connected in a wire bonding welding mode, one end of the connecting wire is connected with the external pins, and the other end of the connecting wire is connected with the rewiring layer beside the chip through the third window/the fourth window. Specifically, the upper surface of the first chip 21 is electrically connected to the first leads 121 through first connection lines 31 penetrating through the third window, and the upper surface of the second chip 22 is electrically connected to the second leads 122 through second connection lines 32 penetrating through the fourth window. Further, the upper surface of the first chip 21 is electrically connected to the first supporting leg 131 through a first connecting line 31 penetrating through the third window, and the upper surface of the second chip 22 is electrically connected to the second supporting leg 132 through a second connecting line 32 penetrating through the fourth window.
It should be understood that 3 first pins, 1 first supporting leg, 3 second pins, and 1 second supporting leg are taken as an example for description in this embodiment, and the number of the pins, the supporting legs, and the corresponding connecting lines may be adjusted as required in other embodiments.
In addition, the package frame and the sealing chip in this embodiment are described by taking 2 sets of corresponding islands and chips as an example, the number of the islands and the chips in other embodiments can be set to 3 or more than 3, all or part of the chips are sealed, and then the sealing chip is packaged on the package frame, which belongs to the protection scope of the present invention.
Referring to fig. 5, a chip packaging method according to an embodiment of the present invention specifically includes the following steps:
1. a first chip 21 and a second chip 22 are prepared.
Firstly, a first chip and a second chip are respectively prepared through the processes of chip wafer processing, wafer thinning, wafer scribing and the like.
2. And sealing the first chip 21 and the second chip 22 to form a sealed chip, and forming a rewiring layer electrically connecting the first chip and the second chip in the sealed chip.
Referring to fig. 6a to 6g, the specific steps of the chip sealing and redistribution layer preparation in this embodiment are as follows:
referring to fig. 6a, a carrier 40 is provided, the carrier is a rigid package carrier, the material of the carrier is not limited, and the lower surface of the carrier 40 is a plane;
referring to fig. 6b, the upper surface of the first chip 21 and the upper surface of the second chip 22 are attached to the lower surface of the carrier 40, and the first chip 21 and the second chip 22 are separately disposed. Specifically, the attaching positions of the first chip 21 and the second chip 22 are set according to the relative positions of the first base island and the second base island in the specific packaging frame, so as to ensure that the first chip 21 and the second chip 22 are respectively located above the first base island and the second base island after the encapsulated chip 20 is packaged with the packaging frame 10;
referring to fig. 6c, the first chip 21 and the second chip 22 are molded by plastic using a packaging material, and a package 201 is formed below the carrier 40. Wherein, the packaging material can be epoxy resin and the like;
peeling the carrier plate 40 to obtain the package structure shown in fig. 6d, wherein the upper surfaces of the first chip and the second chip are flush with the upper surface of the package body;
referring to fig. 6e, a first insulating layer 202 is formed on the upper surfaces of the package 201, the first chip 21 and the second chip 22, and a plurality of first windows 2021 penetrating the upper surface of the first chip 21 and a plurality of second windows 2022 penetrating the upper surface of the second chip 22 are formed by etching;
referring to fig. 6f, a redistribution layer 203 is formed on the first insulating layer 202 and in the first window 2021 and the second window 2022, and the redistribution layer 203 is electrically connected to the first chip 21 and the second chip 22 respectively;
referring to fig. 6g, a second insulating layer 204 is formed on the redistribution layer 203, and a plurality of third windows 2041 penetrating through the first chip-side redistribution layer and a plurality of fourth windows 2042 penetrating through the second chip-side redistribution layer are formed by etching.
In this embodiment, by the arrangement of the redistribution layer, the electrical connection between the first chip 21 and the second chip 22 can be directly realized in the package structure through the redistribution layer 203 without an additional wire bonding process.
In addition, a third window and a fourth window are formed in the second insulating layer 204 on the redistribution layer on the side of the first chip and the second chip, so that the redistribution layer below the windows can be used as an electric connection part of the first chip and the second chip, and the chips are electrically connected with external pins.
3. The encapsulated chip 20 shown in fig. 6g is encapsulated on the encapsulation frame 10 shown in fig. 3, so that the first chip 21 and the second chip 22 are respectively located above the first base island 111 and the second base island 112, and the plastic-encapsulated body 201 is directly encapsulated with the first base island 111 and the second base island 112.
4. Referring to fig. 2, the first chip, the first pins and the first supporting pins are connected by wire bonding, and the first chip 21 and the first pins 121, and the first chip 21 and the first supporting pins 131 are electrically connected by the first connecting wires 31; the second chip, the second pins and the second supporting legs are connected by wire bonding, and the second chip 22, the second pins 122, the second chip 22 and the second supporting legs 132 are electrically connected by the second connecting wires 32.
Referring to fig. 2 and fig. 7, in the present embodiment, the connection between the first connection line 31 and the first chip 21 is an electrical connection between the first connection line 31 and the redistribution layer 203 under the third window beside the first chip 21, and the connection between the second connection line 321 and the second chip 22 is an electrical connection between the second connection line 32 and the redistribution layer 203 under the fourth window beside the second chip 22.
Further, after the combined chip and the packaging frame are packaged and wire-bonded, the whole packaging structure is subjected to plastic molding, and the ribs are cut and separated.
The utility model provides a chip package structure and chip package method can be applied to in the digital isolator, and wherein, first chip and second chip are logic high level chip and logic low level chip respectively. Of course, the present invention can also be applied to other semiconductor package structures and methods, in which the first chip and the second chip are chips of other types.
It should be understood that, in the above embodiment, two chips are sealed, and two base islands are correspondingly disposed in the package frame, in other embodiments, the positions and the numbers of the chips in the sealed chips may also be correspondingly set according to the specific structure of the package frame, the number of the chips may also be set to be three or more, and a plurality of first chips or second chips may also be packaged on each base island, which is not described in detail herein. All adopt and encapsulate the technical scheme to the encapsulation frame on with the chip closure back and all belong to the utility model discloses the scope of protecting.
According to the technical scheme provided by the utility model, the utility model discloses following beneficial effect has:
the utility model discloses a restructure chip structure, close first chip and second chip and seal into an entirety and encapsulate with the encapsulation frame, with two base islands fixed connection in the encapsulation frame, improved the stability of packaging structure and device performance, be applicable to in devices such as two-chip digital isolator;
the rewiring layer in the sealing chip is used for electrically connecting the first chip and the second chip, an intermediate bridging line is not needed, the structure of the device is optimized, and the risk caused by the conventional wire bonding process is reduced.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (8)
1. A chip packaging structure is characterized by comprising a packaging frame and a packaging chip packaged on the packaging frame, wherein the packaging frame comprises a first base island and a second base island which are separately arranged, a plurality of first pins and second pins which are mutually separated are correspondingly arranged at the sides of the first base island and the second base island, the packaging chip comprises a first chip and a second chip which are packaged into a whole and a rewiring layer, the first chip and the second chip are respectively positioned above the first base island and the second base island, the first chip and the second chip are electrically connected through the rewiring layer, the first chip and the first pin are electrically connected with a first connecting wire through the rewiring layer, and the second chip and the second pin are electrically connected with a second connecting wire through the rewiring layer.
2. The chip package structure according to claim 1, wherein the encapsulated chip comprises:
a first chip and a second chip;
the packaging body is used for packaging the first chip and the second chip, and the upper surface of the first chip and the upper surface of the second chip are exposed to the outside of the packaging body;
the first insulating layer is positioned on the upper surfaces of the packaging body, the first chip and the second chip, and a plurality of first windows penetrating through the upper surface of the first chip and a plurality of second windows penetrating through the upper surface of the second chip are formed on the first insulating layer;
the rewiring layer is positioned on the first insulating layer and in the first window and the second window, and is electrically connected with the first chip and the second chip respectively;
and a second insulating layer on the rewiring layer.
3. The chip package structure according to claim 2, wherein the second insulating layer has a plurality of third windows formed therethrough to the first chip-side redistribution layer and a plurality of fourth windows formed therethrough to the second chip-side redistribution layer.
4. The chip package structure according to claim 3, wherein the first chip is electrically connected to the first lead via a first connection line penetrating the third window, and the second chip is electrically connected to the second lead via a third connection line penetrating the fourth window.
5. The chip package structure according to claim 2, wherein the upper surface of the first chip and the upper surface of the second chip are disposed flush with the upper surface of the package body, or the upper surface of the first chip and the upper surface of the second chip are disposed to protrude from the upper surface of the package body.
6. The chip package structure according to claim 3, wherein the package frame further comprises a first supporting leg connected to the first base island and a second supporting leg connected to the second base island.
7. The chip package structure according to claim 6, wherein the first chip is electrically connected to the first supporting leg through a first connecting line penetrating the third window, and the second chip is electrically connected to the second supporting leg through a third connecting line penetrating the fourth window.
8. A digital isolator, characterized in that it comprises a chip package according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022403234.4U CN212967703U (en) | 2020-10-26 | 2020-10-26 | Chip packaging structure and digital isolator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022403234.4U CN212967703U (en) | 2020-10-26 | 2020-10-26 | Chip packaging structure and digital isolator |
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| Publication Number | Publication Date |
|---|---|
| CN212967703U true CN212967703U (en) | 2021-04-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202022403234.4U Active CN212967703U (en) | 2020-10-26 | 2020-10-26 | Chip packaging structure and digital isolator |
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| CN (1) | CN212967703U (en) |
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- 2020-10-26 CN CN202022403234.4U patent/CN212967703U/en active Active
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