CN213071137U - Chip packaging structure and digital isolator - Google Patents

Chip packaging structure and digital isolator Download PDF

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Publication number
CN213071137U
CN213071137U CN202022419222.0U CN202022419222U CN213071137U CN 213071137 U CN213071137 U CN 213071137U CN 202022419222 U CN202022419222 U CN 202022419222U CN 213071137 U CN213071137 U CN 213071137U
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China
Prior art keywords
chip
package
welding part
windows
electrically connected
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CN202022419222.0U
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Chinese (zh)
Inventor
解燕旗
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Sripu Microelectronics Technology Suzhou Co ltd
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Sripu Microelectronics Technology Suzhou Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model discloses a chip package structure and digital isolator, chip package structure includes that encapsulation frame and flip-chip encapsulate the chip of sealing on encapsulation frame, encapsulation frame includes a plurality of first pins and second pin, seals the chip including first chip and second chip, rewiring layer and a plurality of welding part that the encapsulation is as an organic whole, and first chip passes through rewiring layer electric connection with the second chip, and the welding part includes the first welding part through rewiring layer and first chip electric connection and the second welding part through rewiring layer and second chip electric connection, first welding part encapsulates the electric connection in order to realize first chip and first pin on first pin, and the second welding part encapsulates the electric connection in order to realize second chip and second pin on the second pin. The utility model discloses optimize the device structure, improved the stability of packaging structure and device performance, simplified packaging technology, reduced the risk that conventional routing welding process brought.

Description

Chip packaging structure and digital isolator
Technical Field
The utility model belongs to the technical field of the chip package, concretely relates to chip packaging structure and digital isolator.
Background
In a semiconductor circuit packaging structure, particularly a digital isolator, two chips of a logic high level and a logic low level need to be sealed, the two chips need to be connected through a wire, and when the digital isolator works, the two chips are respectively in different voltage domains.
Referring to fig. 1, a chip package structure in the prior art is shown, which includes a package frame and two chips, where the package frame includes a first base island 11 ' and a second base island 12 ' that are separately arranged, and a plurality of first leads 21 ' and second leads 22 ' that are separated from each other are correspondingly disposed at sides of the first base island 11 ' and the second base island 12 ', a first chip 31 ' is packaged on the first base island 11 ', a second chip 32 ' is packaged on the second base island 12 ', the first chip 31 ' and the second chip 32 ' are electrically connected by a first connection line 41 ', the first chip 31 ' and the first lead 21 ' are electrically connected by a second connection line 42 ', and the second chip 32 ' and the second lead 22 ' are electrically connected by a third connection line 43 '. Further, the package frame further includes a first supporting leg 111 'connected to the first base island 11' and a second supporting leg 121 'connected to the second base island 12'.
In the chip packaging structure in the prior art, the support for the chip is connected with the base island through a support leg, and the connection between the chips and the I/O output are connected in a wire bonding mode, so that the problems of insufficient soldering and even deformation caused by unstable structure can exist, and the stability of the packaging process and the product performance is further influenced.
Therefore, it is desirable to provide a chip package structure and a digital isolator.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a chip package structure and digital isolator to promote chip package structure's stability.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a chip packaging structure comprises a packaging frame and a sealing chip which is packaged on the packaging frame in an inverted mode, wherein the packaging frame comprises a plurality of first pins and second pins, the sealing chip comprises a first chip and a second chip which are packaged into a whole, a rewiring layer and a plurality of welding parts, the first chip is electrically connected with the second chip through the rewiring layer, the welding parts comprise a first welding part which is electrically connected with the first chip through the rewiring layer and a second welding part which is electrically connected with the second chip through the rewiring layer, the first welding part is packaged on the first pins to achieve the electrical connection of the first chip and the first pins, and the second welding part is packaged on the second pins to achieve the electrical connection of the second chip and the second pins.
In one embodiment, the sealed chip further includes: the packaging body is used for packaging the first chip and the second chip, and the upper surface of the first chip and the upper surface of the second chip are exposed to the outside of the packaging body.
In an embodiment, the upper surface of the first chip and the upper surface of the second chip are disposed flush with the upper surface of the package, or the upper surface of the first chip and the upper surface of the second chip protrude from the upper surface of the package.
In one embodiment, the package chip further includes a first insulating layer located on the upper surfaces of the package body, the first chip and the second chip, the first insulating layer is formed with a plurality of first windows penetrating the upper surface of the first chip and a plurality of second windows penetrating the upper surface of the second chip, the redistribution layer is located on the first insulating layer and in the first windows and the second windows, and the redistribution layer is electrically connected to the first chip and the second chip respectively.
In an embodiment, the sealed chip further includes a second insulating layer on the redistribution layer.
In one embodiment, a plurality of third windows penetrating through the redistribution layer electrically connected with the first chip and a plurality of fourth windows penetrating through the redistribution layer electrically connected with the second chip are formed on the second insulating layer, the first welding part is formed in the third windows and protrudes out of the second insulating layer, and the second welding part is formed in the fourth windows and protrudes out of the second insulating layer.
The utility model discloses still another embodiment provides the technical scheme as follows:
a digital isolator comprises the chip packaging structure.
Compared with the prior art, the utility model has the advantages of it is following:
the utility model discloses a restructure chip and encapsulation frame's structure, close first chip and second chip and seal into a whole after and carry out flip-chip packaging with the encapsulation frame, optimized the device structure, improved the stability of packaging structure and device performance, be applicable to in devices such as double-chip digital isolator;
the electrical connection of the first chip and the second chip is carried out through the rewiring layer in the combined sealing chip, and the welding part is directly sealed on the pin in an inverted mode, so that the packaging process is simplified, and the risk brought by the conventional wire bonding welding process is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a chip package structure in the prior art;
fig. 2 is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention;
fig. 3 is a schematic plan view of a package frame according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a first chip and a second chip in a combined package chip according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of a chip packaging method according to an embodiment of the present invention;
fig. 6a to 6j are process flow diagrams of a chip packaging method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. However, the present invention is not limited to the embodiments, and the structural, method, or functional changes made by those skilled in the art according to the embodiments are all included in the scope of the present invention.
In the various illustrations of the present application, certain dimensions of structures or portions are exaggerated relative to other structures or portions for ease of illustration and, thus, are provided only to illustrate the basic structure of the subject matter of the present application.
Terms such as "upper," "lower," "above," "over," and the like, used herein to denote relative spatial positions, are used for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative positional terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" other elements or features would then be oriented "below" the other elements or features.
The utility model discloses a chip package structure, encapsulate the chip of sealing up including encapsulation frame and flip-chip on encapsulation frame, encapsulation frame includes a plurality of first pins and second pin, seal up the chip including encapsulation first chip and second chip as an organic whole, rewiring layer and a plurality of welding part, first chip passes through rewiring layer electric connection with the second chip, the welding part includes the first welding part through rewiring layer and first chip electric connection and the second welding part through rewiring layer and second chip electric connection, first welding part encapsulates the electric connection in order to realize first chip and first pin on first pin, the second welding part encapsulates the electric connection in order to realize second chip and second pin on the second pin.
The utility model also discloses a digital isolator, it includes foretell chip package structure.
The present invention will be further described with reference to specific embodiments.
Referring to fig. 2 in combination with fig. 3 and 4, a chip package structure according to an embodiment of the present invention includes a package frame 10 and a sealing chip 20 flip-chip packaged on the package frame.
Referring to fig. 3, the package frame 10 in the embodiment includes a plurality of first leads 11 and second leads 12, and the first leads 11 and the second leads 12 are distributed on the frame in an array.
Referring to fig. 2 and 4 in combination with fig. 6a to 6j, the sealed chip 20 includes:
the chip package comprises a first chip 21 and a second chip 22, wherein the first chip 21 and the second chip 22 are packaged into a whole;
a package 201 for packaging the first chip 21 and the second chip 22, wherein an upper surface of the first chip 21 and an upper surface of the second chip 22 are exposed to the outside of the package 201;
a first insulating layer 202 disposed on the upper surfaces of the package body 201, the first chip 21 and the second chip 22, wherein a plurality of first windows 2021 penetrating the upper surface of the first chip and a plurality of second windows 2022 penetrating the upper surface of the second chip are formed on the first insulating layer 202;
the redistribution layer 203 is positioned on the first insulating layer 202 and in the first window 2021 and the second window 2022, and the redistribution layer 203 is electrically connected with the upper surfaces of the first chip 21 and the second chip 22 respectively, so that the first chip 21 is electrically connected with the second chip 22;
a second insulating layer 204 located on the redistribution layer 203, and a plurality of third windows 2041 penetrating through the redistribution layer electrically connected to the first chip and a plurality of fourth windows 2042 penetrating through the redistribution layer electrically connected to the second chip are formed on the second insulating layer 204;
the bonding portion includes a first bonding portion 2051 electrically connected to the first chip 21 through the redistribution layer 203 and a second bonding portion 2052 electrically connected to the second chip 22 through the redistribution layer 203, the first bonding portion 2051 is formed in the third window 2041 and protrudes from the second insulating layer 204, and the second bonding portion 2052 is formed in the fourth window 2042 and protrudes from the second insulating layer 204.
The first welding portions 2051 and the second welding portions 2052 in this embodiment may be solder balls, and preferably, the first welding portions 2051 and the second welding portions 2052 are distributed on the second insulating layer in an array.
The first soldering portions 2051 are distributed corresponding to the first leads 11 on the package frame 10, the second soldering portions 2052 are distributed corresponding to the second leads 12 on the package frame 10, and after the encapsulated chip 20 is flip-chip packaged on the package frame 10, the first soldering portions 2051 can be packaged on the first leads 11 to electrically connect the first chip 21 with the first leads 11, and the second soldering portions 2052 can be packaged on the second leads 12 to electrically connect the second chip 22 with the second leads 12
Of course, in other embodiments, the upper surface of the first chip 21 and the upper surface of the second chip 22 may also protrude from the upper surface of the package 201, and the technical solutions that the redistribution layer electrically connects the first chip and the second chip, and the first bonding portion and the second bonding portion are electrically connected to the first chip and the second chip respectively belong to the protection scope.
In addition, the package frame and the sealing chip in this embodiment are described by taking 2 chips as an example, the number of chips in other embodiments can also be set to 3 or more than 3, all the chips are sealed by sealing all or part of the chips, and the technical scheme of flip-chip packaging the sealing chip on the package frame is adopted in the present invention.
Referring to fig. 5 and fig. 6a to 6j, a chip packaging method according to an embodiment of the present invention specifically includes the following steps:
1. a first chip 21 and a second chip 22 are prepared.
Firstly, a first chip and a second chip are respectively prepared through the processes of chip wafer processing, wafer thinning, wafer scribing and the like.
2. The first chip 21 and the second chip 22 are sealed to form a sealed chip, and a redistribution layer electrically connecting the first chip and the second chip, a first welding part electrically connected with the first chip, and a second welding part electrically connected with the second chip are formed in the sealed chip.
The method comprises the following steps:
referring to fig. 6a, a carrier 40 is provided, the carrier is a rigid package carrier, the material of the carrier is not limited, and the lower surface of the carrier 40 is a plane;
referring to fig. 6b, the upper surface of the first chip 21 and the upper surface of the second chip 22 are attached to the lower surface of the carrier 40, and the first chip 21 and the second chip 22 are separately disposed. Specifically, the attachment positions of the first chip 21 and the second chip 22 are set according to the structure of a specific package frame;
referring to fig. 6c, the first chip 21 and the second chip 22 are molded by plastic using a packaging material, and a package 201 is formed below the carrier 40. Wherein, the packaging material can be epoxy resin and the like;
peeling the carrier plate 40 to obtain the package structure shown in fig. 6d, wherein the upper surfaces of the first chip and the second chip are flush with the upper surface of the package body;
referring to fig. 6e, a first insulating layer 202 is formed on the upper surfaces of the package 201, the first chip 21 and the second chip 22, and a plurality of first windows 2021 penetrating the upper surface of the first chip 21 and a plurality of second windows 2022 penetrating the upper surface of the second chip 22 are formed by etching;
referring to fig. 6f, a redistribution layer 203 is formed on the first insulating layer 202 and in the first window 2021 and the second window 2022, and the redistribution layer 203 is electrically connected to the first chip 21 and the second chip 22 respectively;
referring to fig. 6g, a second insulating layer 204 is formed on the redistribution layer 203, and a plurality of third windows 2041 penetrating through the redistribution layer 203 electrically connected to the first chip 21 and a plurality of fourth windows 2042 penetrating through the redistribution layer 203 electrically connected to the first chip 22 are formed by etching, that is, the redistribution layer 203 under the third windows 2041 is electrically connected to the first chip 21 only, and the redistribution layer 203 under the fourth windows 2042 is electrically connected to the second chip 22 only;
referring to fig. 6h, a first bonding portion 2051 electrically connected to the first chip through the redistribution layer is formed in the third window 2041, and a second bonding portion 2052 electrically connected to the second chip through the redistribution layer is formed in the fourth window 2042, where the first bonding portion 2051 and the second bonding portion 2052 in this embodiment are both solder ball structures.
3. Referring to fig. 6i, the encapsulated chip 20 is flip-chip packaged on the package frame 10, so that the first bonding portion 2051 and the second bonding portion 2052 are electrically connected to the first lead 11 and the second lead 12 on the package frame 10, respectively, and the package structure shown in fig. 6j is finally obtained.
Further, after the sealed chip and the packaging frame are packaged in an inverted mode, the whole packaging structure is subjected to plastic package forming, and ribs are cut for separation.
In this embodiment, the upper surfaces of the first chip, the second chip, and the package are described with respect to the packaged chip before flip-chip mounting, and after flip-chip mounting, the upper surfaces of the first chip, the second chip, and the package are located at relatively lower positions.
In this embodiment, by the arrangement of the redistribution layer, the electrical connection between the first chip 21 and the second chip 22 can be directly realized in the package structure through the redistribution layer 203, and the connection between the two chips is not required to be performed through an additional wire bonding process.
In addition, the welding parts which are separately and electrically connected with the first chip 21 and the second chip 22 are prepared on the second insulating layer, and the welding parts are directly packaged on the pins in a flip-chip mode without extra wire bonding process for connection between the chips and the pins.
And simultaneously, the utility model discloses also reconstitute to the encapsulation frame in the well, need not to set up the base island, simplified the encapsulation frame construction.
The utility model provides an in the chip package structure can be applied to digital isolator, wherein, first chip and second chip are logic high level chip and logic low level chip respectively. Of course, the present invention can also be applied to other semiconductor package structures and methods, in which the first chip and the second chip are chips of other types.
It should be understood that, in the above embodiment, two chips are sealed as an example for description, in other embodiments, the positions and the number of the chips in the sealed chips may be correspondingly set according to the specific structure of the package frame, and the number of the chips may also be set to three or more, which will not be described in detail herein. All adopt and close the flip-chip package with the chip and all belong to the technical scheme on the encapsulation frame the utility model discloses the scope of protecting.
According to the technical scheme provided by the utility model, the utility model discloses following beneficial effect has:
the utility model discloses a restructure chip and encapsulation frame's structure, close first chip and second chip and seal into a whole after and carry out flip-chip packaging with the encapsulation frame, optimized the device structure, improved the stability of packaging structure and device performance, be applicable to in devices such as double-chip digital isolator;
the electrical connection of the first chip and the second chip is carried out through the rewiring layer in the combined sealing chip, and the welding part is directly sealed on the pin in an inverted mode, so that the packaging process is simplified, and the risk brought by the conventional wire bonding welding process is reduced.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (7)

1. A chip packaging structure is characterized by comprising a packaging frame and a sealing chip which is packaged on the packaging frame in an inverted mode, wherein the packaging frame comprises a plurality of first pins and second pins, the sealing chip comprises a first chip and a second chip which are packaged into a whole, a rewiring layer and a plurality of welding parts, the first chip is electrically connected with the second chip through the rewiring layer, the welding parts comprise a first welding part which is electrically connected with the first chip through the rewiring layer and a second welding part which is electrically connected with the second chip through the rewiring layer, the first welding part is packaged on the first pins to achieve the electrical connection of the first chip and the first pins, and the second welding part is packaged on the second pins to achieve the electrical connection of the second chip and the second pins.
2. The chip package structure according to claim 1, wherein the encapsulated chip further comprises: the packaging body is used for packaging the first chip and the second chip, and the upper surface of the first chip and the upper surface of the second chip are exposed to the outside of the packaging body.
3. The chip package structure according to claim 2, wherein the upper surface of the first chip and the upper surface of the second chip are disposed flush with the upper surface of the package body, or the upper surface of the first chip and the upper surface of the second chip are disposed to protrude from the upper surface of the package body.
4. The chip package structure according to claim 2, wherein the encapsulated chip further comprises a first insulating layer disposed on the upper surfaces of the package body, the first chip and the second chip, the first insulating layer is formed with a plurality of first windows penetrating the upper surface of the first chip and a plurality of second windows penetrating the upper surface of the second chip, the redistribution layer is disposed on the first insulating layer and in the first windows and the second windows, and the redistribution layer is electrically connected to the first chip and the second chip, respectively.
5. The chip package structure of claim 4, wherein the encapsulated chip further comprises a second insulating layer on the redistribution layer.
6. The chip package structure according to claim 5, wherein the second insulating layer has a plurality of third windows formed therethrough to the redistribution layer electrically connected to the first chip and a plurality of fourth windows formed therethrough to the redistribution layer electrically connected to the second chip, the first bonding portions are formed in the third windows and protrude from the second insulating layer, and the second bonding portions are formed in the fourth windows and protrude from the second insulating layer.
7. A digital isolator, characterized in that it comprises a chip package according to any one of claims 1 to 6.
CN202022419222.0U 2020-10-27 2020-10-27 Chip packaging structure and digital isolator Active CN213071137U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202022419222.0U CN213071137U (en) 2020-10-27 2020-10-27 Chip packaging structure and digital isolator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202022419222.0U CN213071137U (en) 2020-10-27 2020-10-27 Chip packaging structure and digital isolator

Publications (1)

Publication Number Publication Date
CN213071137U true CN213071137U (en) 2021-04-27

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Country Status (1)

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CN (1) CN213071137U (en)

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