CN211238250U - Chip packaging structure adopting multi-base-island lead frame - Google Patents
Chip packaging structure adopting multi-base-island lead frame Download PDFInfo
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- CN211238250U CN211238250U CN202020339596.9U CN202020339596U CN211238250U CN 211238250 U CN211238250 U CN 211238250U CN 202020339596 U CN202020339596 U CN 202020339596U CN 211238250 U CN211238250 U CN 211238250U
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- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model discloses a chip packaging structure adopting a multi-base island lead frame, which is characterized in that a diode with double N substrates and a diode with double P substrates are respectively arranged on two different base islands to form a diode rectifier bridge stack; compared with the traditional four independent diode rectifier bridge stacks, the scheme is simpler to realize, easier to operate and lower in cost.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to an adopt chip packaging structure of many base island lead frame.
Background
With the rapid development of the IC design and manufacture industries, the packaging technology is greatly improved. Packaging is an important part of the whole integrated circuit manufacturing process, and has heat dissipation and protection functions. The packaging process can seal the chip and isolate the damage of external pollution and external force to the chip.
With the progress of technology, packaging a single chip in one package has not been satisfactory. Packaging multiple chips in one package is becoming the direction of technology development. The chip area is smaller and smaller, the power is larger and larger, the use environment is more and more limited, the heat dissipation requirement is higher and higher, the market competition is more and more intense, and the cost competition is particularly prominent.
At present, an input rectifier bridge, a freewheeling diode and a drive IC in a drive circuit are separated, and belong to different packaged components, and multiple times of board mounting is needed in actual production in a factory, so that the cost of the components is high, and the size of a circuit board is large.
Fig. 1A and 1B are also shown, in which fig. 1A is a schematic circuit diagram of a conventional input rectifier bridge, and fig. 1B is a schematic diagram of a diode package.
As shown in fig. 1A, a conventional input rectifier bridge generally includes four independent diodes (D1-D4) to rectify an input AC and output a DC.
As shown in fig. 1B, in the case of the N-substrate diode 11, when it is packaged, the bottom of the diode is electrically connected to the base island of the lead frame and the top is an anode (i.e., N-substrate), and it can be electrically connected to other components through metal leads, as shown in part a in fig. 1B; for the P-substrate diode 12, when packaged, the bottom is electrically connected to the base island of the lead frame and the top is the cathode (i.e., P-substrate), and can be electrically connected to other components through metal leads, as shown in part B of fig. 1B.
When four independent diodes are packaged, a plurality of independent base islands, multiple times of glue dispensing and core loading are needed, the scheme is complicated, the production capacity (UPH) is low, and the cost is high.
Disclosure of Invention
An object of the utility model is to provide an adopt chip packaging structure of polybase island lead frame to the technical problem who exists among the prior art, can reduce components and parts in the factory production, realize material cost reduction, packaging structure's circuit board volume advantage such as littleer.
In order to achieve the above object, the utility model provides an adopt chip packaging structure of polybase island lead frame, include: the multi-base-island lead frame comprises a first type of pins, and a first base island and a second base island which are electrically isolated from each other, wherein the first base island is connected with at least one connecting rib; the first type of pins comprise a first alternating current input pin, a second alternating current input pin, a bus pin and a grounding pin, the distance between every two adjacent pins is larger than a preset distance value, and the bus pin is directly connected with the second base island; the double-P substrate diode is arranged on the first base island and comprises a first cathode, a second cathode and a shared anode, wherein the anode of the double-P substrate diode is electrically connected with the first base island and the grounding pin through the first base island, the first cathode of the double-P substrate diode is electrically connected with the first alternating current input pin through a metal lead, and the second cathode of the double-P substrate diode is electrically connected with the second alternating current input pin through a metal lead; two opposite side edges of the double-P substrate diode are parallel to a central axis of the chip packaging structure or form an included angle; the double-N substrate diode is arranged on the second base island and comprises a first anode, a second anode and a shared cathode; the cathode of the diode is electrically connected with the second base island and is electrically connected with the bus pin through the second base island, the first anode of the diode is electrically connected with the first alternating current input pin through a metal lead, and the second anode of the diode is electrically connected with the second cathode of the double-P substrate diode through a metal lead and is electrically connected with the second alternating current input pin through the second cathode; two opposite side edges of the double-N substrate diode are parallel to a central axis of the chip packaging structure or form an included angle with the central axis.
The utility model has the advantages that: the utility model discloses a put a two N substrate diodes and a two P substrate diodes respectively on two different base islands, constitute diode rectifier bridge piles, compare four traditional independent diode rectifier bridge piles, this scheme realizes simpler, the operation is easier, the cost is lower. By further sealing the diode rectifier bridge stack and one or more of the drive IC, the fly-wheel diode, the MOS tube and the like in a packaging structure, the integration level of the chip is improved, and the cost of the whole circuit is reduced; the base islands in the packaging structure are electrically isolated, and the distance between the pins is large enough, so that high-voltage breakdown can be effectively prevented, and the requirements of packaging or reliability are met.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1A is a schematic circuit diagram of a conventional input rectifier bridge;
fig. 1B is a schematic diagram of a diode package.
Fig. 2 is a schematic plan view of a first embodiment of a chip package structure using a multi-base island lead frame according to the present invention;
fig. 3 is a schematic plan view of a second embodiment of a chip package structure using a multi-base island lead frame according to the present invention;
fig. 4 is a schematic plan view of a chip package structure of a third embodiment of the present invention using a multi-base island lead frame;
fig. 5 is a schematic plane structure diagram of a fourth embodiment of the chip packaging structure using the multi-base island lead frame according to the present invention;
fig. 6 is a schematic view of a plane structure of a fifth embodiment of the chip packaging structure of the multi-base island lead frame according to the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without any creative work belong to the protection scope of the present invention. The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The utility model is characterized in that a diode with double N substrates and a diode with double P substrates are respectively arranged on two different base islands to form a diode rectifier bridge stack; compared with the traditional four independent diode rectifier bridge stacks, the scheme is simpler to realize, easier to operate and lower in cost. The diode rectifier bridge stack and one or more of a drive IC, a freewheeling diode, an MOS tube and the like are sealed in a packaging structure, so that a sealed chip with high integration level is formed. The double-P substrate diode is formed on two diodes on the same P substrate and comprises a first cathode, a second cathode and a shared anode; a double N-substrate diode is two diodes formed on the same N-substrate and includes a first anode, a second anode, and a common cathode.
The utility model discloses can adopt any suitable encapsulation standard to form packaging structure. In the package structure in the following embodiments, the SOP-6 or ESOP-6 package specifications were selected for demonstration in relation to a 6-pin package. Wherein, the length of the SOP-6 and ESOP-6 packages is 4.84-4.96mm, the width is 3.84-3.96mm, the number of pins is 6, and the width of the pins is 0.35-0.47 mm. By adopting the packaging specification, the packaging body can keep smaller size and bear higher power density on the premise of keeping high integration level. Those skilled in the art will appreciate that the application of the present invention is not limited to the above package format, for example, in the following embodiments, the package structure involving 8 pins is demonstrated using the SOP-8 package specification. In the case of a 7-pin package structure, a mixture of SOP-6 and SOP-8 package specifications is used (i.e., SOP-6 package specifications are used for a 3-pin portion on one side and SOP-8 package specifications are used for a 4-pin portion on one side). In other embodiments, other package specifications, such as QFN, DFN, etc., may also be used to implement the present invention.
Referring to fig. 2, the present invention is a schematic plan view of a chip package structure with multiple base islands according to a first embodiment.
In this embodiment, the package structure includes a multi-base-island lead frame, a dual P-substrate diode 31, and a dual N-substrate diode 32.
Specifically, the multi-base-island lead frame is a double-base-island lead frame, and the packaging line of the double-base-island lead frame is schematically marked by a graphic frame 308. In this embodiment, the multi-base-island lead frame includes a plurality of first-type pins and two base islands electrically isolated from each other, which are a first base island 301 and a second base island 302, respectively. The first class of pins includes at least a first alternating current (AC1) input pin, a second alternating current (AC2) input pin, a BUS (BUS) pin, and a Ground (GND) pin. For example, the 4 pins (pin1 to pin4) of the double-island lead frame are: pin1 is a first alternating current (AC1) input pin1, pin2 is a Ground (GND) pin2, pin3 is a second alternating current (AC2) input pin3, and pin4 is a BUS (BUS) pin 4. The distance between every two adjacent pins is large enough (the distance between every two adjacent pins is larger than a preset distance value), so that the high-voltage breakdown risk is effectively reduced. Wherein the first alternating current (AC1) input pin1 and the second alternating current (AC2) input pin3 are located on the same side of the first base island 301 away from the second base island 302. Preferably, the Ground (GND) pin2 is directly connected to the first base island 301, and the BUS (BUS) pin4 is directly connected to the second base island 302.
In other embodiments, a first alternating current (AC1) input pin and a second alternating current (AC2) input pin may be located on both sides of the first base island 301, and one of the alternating current input pins (e.g., the first alternating current input pin) is located near the side of the pin to which the second base island 302 is electrically connected. That is, the first alternating current (AC1) input pin is disposed opposite to the second alternating current (AC2) input pin, and one of them is located at the side of the pin to which the second base island 302 is electrically connected.
The double-P substrate diode 31 is attached to the first base island 301 by an adhesive such as a conductive adhesive. The dual P-substrate diode 31 comprises a first cathode, a second cathode and a common anode; an anode thereof is electrically connected to the first base island 301 and to the Ground (GND) pin2 through the first base island 301; the first cathode (pbase) is electrically connected to the first alternating current (AC1) input pin1 through the metal lead 39, and the second cathode is electrically connected to the second alternating current (AC2) input pin3 through the metal lead 39. The anode of the double P-substrate diode 31 may also be electrically connected to the Ground (GND) pin2 through a metal lead. In other embodiments, the first base island 301 may be a recessed structure, and the first base island 301 is recessed to serve as a Ground (GND) pin. The foundation island is grounded after being dented, so that heat dissipation is facilitated, and the arrangement of grounding pins on the lead frame is saved.
The double-N substrate diode 32 is attached to the second base island 302 by an adhesive such as a conductive adhesive. The double N-substrate diode 32 includes a first anode, a second anode, and a common cathode; its cathode is electrically connected to the second base island 302 and to the BUS (BUS) pin4 through the second base island 302; a first anode (N-substrate) thereof is electrically connected to a first alternating current (AC1) input pin1 through a metal lead 39, and a second anode is electrically connected to a second cathode of the double P-substrate diode 31 through the metal lead 39, thereby being electrically connected to a second alternating current (AC2) input pin3 through the second cathode of the double P-substrate diode 31. In this embodiment, the cathode of the double N-substrate diode 32 is directly electrically connected to the BUS (BUS) pin 4; in other embodiments, the cathode of the double N-substrate diode 32 may also be electrically connected to the BUS (BUS) pin4 by a metal wire.
In this embodiment, the first cathode of the double P-substrate diode 31 is disposed opposite to the first anode of the double N-substrate diode 32, and is disposed on a side of the corresponding base island near the first alternating current (AC1) input pin 1. The arrangement mode enables the routing length of the metal lead between the component and the corresponding pin to be shorter, routing to be more convenient, and chip packaging layout to be facilitated.
Optionally, the area of the first base island 301 is larger than that of the second base island 302, which facilitates the layout of the dual P-substrate diode 31 and facilitates the subsequent layout of other components on the first base island 301. Two sides of the first base island 301 are respectively connected with a Tie bar 309, so that the stability of the base island is improved. In other embodiments, the area of the first base island 301 may be the same as the area of the second base island 302, and the first base island 301 may be connected to only one connecting rib, and the second base island 302 is connected to another connecting rib.
Optionally, two opposite sides of the double P-substrate diode 31 have an included angle with a central axis of the chip package structure, and/or two opposite sides of the double N-substrate diode 32 have an included angle with a central axis of the chip package structure. Namely, at least one of the dual P-substrate diode 31 and the dual N-substrate diode 32 can adopt an inclined layout, so that the wire bonding operation in the wire bonding area is more convenient, and the close wire bonding contact or close distance breakdown can be prevented. The included angle can be set according to actual requirements, and for example, the included angle can be larger than 0 degree and smaller than 90 degrees relative to the central longitudinal axis.
In the embodiment, a diode rectifier bridge stack is formed by respectively placing a double-N substrate diode and a double-P substrate diode on two different base islands, so that fewer dispensing and core loading times are realized, the production efficiency is improved, and the production cost is reduced.
Referring to fig. 3, the present invention is a schematic plan view of a chip package structure with multiple base islands according to a second embodiment.
In this embodiment, the package structure includes a multi-base island lead frame, a dual P-substrate diode 31, a dual N-substrate diode 32, and a main control chip 33.
In this embodiment, the multi-base-island lead frame includes two base islands electrically isolated from each other, namely a first base island 301a and a second base island 302. Wherein the area of the first base island 301a is larger than the area of the second base island 302. Two sides of the first base island 301 are respectively connected with a Tie bar 309, so that the stability of the base island is improved. The packaging line of the multi-base island lead frame is schematically marked by a graphic wire frame 308. The multi-base-island lead frame comprises a first type of pin and a second type of pin; the first class of pins includes a first alternating current (AC1) input pin, a second alternating current (AC2) input pin, a BUS (BUS) pin, and a Ground (GND) pin, and the second class of pins includes a feedback (CS) pin and a Drain (Drain) pin. Specifically, the Drain (Drain) pin may include a first Drain (Drain1) pin and a second Drain (Drain2) pin.
Specifically, in this embodiment, the multi-base-island lead frame includes at least 8 pins (pin1 to pin8), where pin1 is a first alternating current (AC1) input pin1, pin4 is a second alternating current (AC2) input pin4, pin5 is a feedback (CS) pin5, pin6 is a first Drain terminal (Drain1) pin6, and pin8 is a BUS (BUS) pin 8. Wherein the BUS (BUS) pin8 is directly connected to the corresponding base island (second base island 302). The pins 2, 3, and 7 are undefined because no component is connected, and the optional pin7 may be a Null (NC) pin 7. The distance between the pins is large enough (larger than a preset distance value), so that the high-voltage breakdown risk is effectively reduced. Wherein a first alternating current (AC1) input pin1 and a second alternating current (AC2) input pin4 are located on the same side of the first base island 301a away from the second base island 302.
Preferably, fig. 3 shows a recessing product for facilitating heat dissipation, wherein the first base island 301a is Grounded (GND) after being recessed. The BUS (BUS) pin3 is directly connected to the second base island 302.
The double-P substrate diode 31 is adhered to the first base island 301a by an adhesive such as a conductive adhesive; the anode thereof is electrically connected to the first base island 301 a; the anode of the first base island 301a is electrically connected (thereby achieving grounding), and the double cathode of the first base island is electrically connected with a part of the multiple pins of the multiple-base island lead frame through the metal lead 39. For example, the first cathode (pbase) of the diode 31 is electrically connected to the first alternating current (AC1) input pin1 through the metal wire 39, and the second cathode thereof is electrically connected to the second alternating current (AC2) input pin4 through the metal wire 39.
The diode 32 with double N substrates is adhered to the second base island 302 by an adhesive such as a conductive adhesive, the cathode of the diode is electrically connected to the pins of the second base island 302 (i.e., electrically connected to the BUS (BUS) pins 8), and the anode of the diode is electrically connected to some of the pins of the multi-base-island lead frame through a metal lead 39. For example, the cathode of the double N-substrate diode 32 is electrically connected to the BUS (BUS) pin8, the first anode of the double N-substrate diode 32 is electrically connected to the first alternating current (AC1) input pin1 through the metal wire 39, and the second anode thereof is electrically connected to the second cathode of the double P-substrate diode 31 through the metal wire 39, so as to be electrically connected to the second alternating current (AC2) input pin4 through the second cathode of the double P-substrate diode 31.
In this embodiment, the second base island 302 is formed at an end close to the dual P-substrate diode 31, so that the wire bonding length between the dual N-substrate diode 32 and the corresponding pin and the metal lead between the dual N-substrate diode 32 and the dual P-substrate diode 31 is short, and the chip packaging layout is facilitated.
The main control chip 33 is attached to the first base island 301a by using an adhesive such as a conductive adhesive, and the main control chip 33 is electrically connected to the first base island 301a and some of the plurality of pins of the multi-base-island lead frame through metal leads 39. For example, the main control chip 33 is electrically connected to a feedback (CS) pin5 and a first Drain (Drain1) pin6 through metal leads 39, respectively; the main control chip 33 is electrically connected to the first base island 301a (for GND connection) through a metal wire 39. The main control chip 21 is an integrated circuit chip (IC), such as a driver IC, for controlling other devices.
Optionally, an included angle is formed between two opposite sides of the main control chip 33 and a central axis of the chip package structure, and/or an included angle is formed between two opposite sides of the dual P-substrate diode 31 and a central axis of the chip package structure, and/or an included angle is formed between two opposite sides of the dual N-substrate diode 32 and a central axis of the chip package structure. Namely, at least one of the double P-substrate diode 31, the double N-substrate diode 32 and the main control chip 33 can adopt an inclined layout, so that the wire bonding operation in the wire bonding area is more convenient, and the contact or close-range breakdown of the adjacent wire bonding can be prevented. The included angle can be set according to actual requirements, and for example, the included angle can be larger than 0 degree and smaller than 90 degrees relative to the central longitudinal axis.
In the embodiment, a diode rectifier bridge stack is formed by respectively placing a double-N substrate diode and a double-P substrate diode on two different base islands, so that fewer dispensing and core loading times are realized, the production efficiency is improved, and the production cost is reduced. The driver IC and the double-P substrate diode are placed on the same base island, and the diode rectifier bridge stack and the driver IC are sealed in a packaging structure, so that a high-integration-level sealed chip is formed.
Referring to fig. 4, the present invention is a schematic plan view of a chip package structure with multiple base islands according to a third embodiment.
The difference from the embodiment shown in fig. 3 is that, in the present embodiment, a first alternating current (AC1) input pin and a second alternating current (AC2) input pin are located at two sides of the first base island 301b, and one of the alternating current input pins (e.g., the first alternating current input pin) is located close to the side of the pin electrically connected to the second base island 302. That is, the first alternating current (AC1) input pin is disposed opposite to the second alternating current (AC2) input pin, and one of them is located at the side of the pin to which the second base island 302 is electrically connected.
Correspondingly, the electrical characteristics of the pins of the multi-base island lead frame are adjusted, specifically, pin1 is a first alternating current (AC1) input pin1, pin3 is a BUS (BUS) pin3, pin4 is a first Drain (Drain1) pin4, pin5 is a feedback (CS) pin5, pin6 is a second Drain (Drain2) pin6, and pin8 is a second alternating current (AC2) input pin 8. Wherein the BUS (BUS) pin3 is directly connected to the corresponding base island (second base island 302).
The electrical connection of the double P-substrate diode 31 and the double N-substrate diode 32 can be referred to fig. 3.
The main control chip 33 is electrically connected to the first base island 301b and some of the plurality of leads (second-type leads) of the multi-base-island lead frame through metal leads 39. For example, the main control chip 33 is electrically connected to the first base island 301b (for grounding), the first Drain (Drain1) pin4, the feedback (CS) pin5, and the second Drain (Drain2) pin6 through metal wires 39, respectively.
Compared with the embodiment shown in fig. 3, in the embodiment, the wire bonding length of the metal lead between the component and the corresponding pin is shorter, and the wire bonding is more convenient.
In other embodiments, the main control chip 33 may not be disposed in the package structure, and the connection relationship between the components in the package structure and the pins of the package structure may be adaptively adjusted.
Referring to fig. 5, the present invention is a schematic plan view of a fourth embodiment of a chip packaging structure with a multi-base island lead frame.
The difference from the embodiment shown in fig. 4 is that, in this embodiment, a double N-substrate diode 32 and an N-substrate freewheeling device 34 are disposed on the second base island 302 a.
Correspondingly, the electrical characteristics of the pins of the multi-base-island lead frame are adjusted, specifically, pin1 is a first alternating current (AC1) input pin1, pin3 is a BUS (BUS) pin3, pin4 is a Drain (Drain) pin4, pin5 is a Null (NC) pin, pin6 is a feedback (CS) pin6, and pin8 is a second alternating current (AC2) input pin 8.
The main control chip 33 is electrically connected to the first base island 301b, the N-substrate freewheeling device 34, and some pins (second-type pins) of the multiple pins of the multi-base-island lead frame through metal leads 39. For example, the main control chip 33 is electrically connected to the first base island 301b (for grounding), the N-substrate freewheeling component 34, and the feedback (CS) pin6 through metal leads 39, respectively; the main control chip 33 is further connected to the second base island 302a through a metal wire 39, so as to electrically connect to a BUS (BUS) pin 3.
The N-substrate freewheeling device 34 is attached to the second base island 302a by using an adhesive such as a conductive adhesive, and is located at a side close to the main control chip 33. The N-substrate freewheeling component 34 is electrically connected to the second base island 302a (to implement BUS (BUS) pin 3), and is electrically connected to the Drain (Drain) pin4 and the main control chip 33 through metal wires 39, respectively. The N-substrate freewheeling device 34 is an N-substrate freewheeling diode that may be used as a freewheeling diode for a switching power supply when the package structure is actually applied to a circuit structure.
In the embodiment, a diode bridge rectifier stack is formed by respectively placing a diode with double N substrates and a diode with double P substrates on two different base islands, and the diode bridge rectifier stack, the drive IC and the freewheeling diode are sealed in a packaging structure, so that the chip integration level is further improved.
In other embodiments, the main control chip 33 may not be disposed in the package structure, and the connection relationship between the components in the package structure and the pins of the package structure may be adaptively adjusted.
Referring to fig. 6, the present invention is a schematic plan view of a chip package structure with multiple base islands according to a fifth embodiment.
The difference from the embodiment shown in fig. 5 is that, in this embodiment, the multi-base-island lead frame further includes a third base island 303, and the third base island 303 is substantially placed side by side with the second base island 302 and is located on the same side of the first base island 301 b. The third base island 303 is close to the side of the main control chip 33. A direct connection pin, such as a Drain terminal (Drain) pin4, directly connected to the third base island 303 is further disposed on the multi-base-island lead frame. That is, the Drain (Drain) pin4 is directly connected to the third base island 303. A P-substrate freewheeling component 35 is disposed on the third base island 303.
Accordingly, the main control chip 33 is connected to the third base island 303 through a metal wire 39, thereby electrically connecting a Drain (Drain) pin 4.
The P-substrate follow current component 35 is attached to the third base island 303 with an adhesive such as a conductive adhesive. The P-substrate freewheeling component 35 is electrically connected to the Drain (Drain) pin4 on the third base island 303 and to the second base island 302 via a metal lead 39, thereby electrically connecting to the BUS (BUS) pin 3. The P-substrate freewheeling component 35 is a P-substrate diode that can be used as a freewheeling diode for a switching power supply when the package structure is actually applied to a circuit structure. In other embodiments, a switching device, such as an N-type MOS transistor, may also be disposed on the third base island 303, and may be used as a power switching transistor of a switching power supply when the package structure is actually applied to a circuit structure. Alternatively, a P-substrate freewheeling device and a switching device may be disposed on the third base island 303 at the same time.
Optionally, one side of the third base island 303 may be connected to a tie bar to improve the stability of the base island.
In other embodiments, the main control chip 33 may not be disposed in the package structure, and the connection relationship between the components in the package structure and the pins of the package structure may be adaptively adjusted.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (12)
1. The utility model provides an adopt chip package structure of many baseisland lead frame which characterized in that includes:
the multi-base-island lead frame comprises a first type of pins, and a first base island and a second base island which are electrically isolated from each other, wherein the first base island is connected with at least one connecting rib; the first type of pins comprise a first alternating current input pin, a second alternating current input pin, a bus pin and a grounding pin, the distance between every two adjacent pins is larger than a preset distance value, and the bus pin is directly connected with the second base island;
the double-P substrate diode is arranged on the first base island and comprises a first cathode, a second cathode and a shared anode, wherein the anode of the double-P substrate diode is electrically connected with the first base island and the grounding pin through the first base island, the first cathode of the double-P substrate diode is electrically connected with the first alternating current input pin through a metal lead, and the second cathode of the double-P substrate diode is electrically connected with the second alternating current input pin through a metal lead; two opposite side edges of the double-P substrate diode are parallel to a central axis of the chip packaging structure or form an included angle;
the double-N substrate diode is arranged on the second base island and comprises a first anode, a second anode and a shared cathode; the cathode of the diode is electrically connected with the second base island and is electrically connected with the bus pin through the second base island, the first anode of the diode is electrically connected with the first alternating current input pin through a metal lead, and the second anode of the diode is electrically connected with the second cathode of the double-P substrate diode through a metal lead and is electrically connected with the second alternating current input pin through the second cathode; two opposite side edges of the double-N substrate diode are parallel to a central axis of the chip packaging structure or form an included angle with the central axis.
2. The chip package structure with the multi-base-island lead frame according to claim 1, wherein the dual P-substrate diode and the dual N-substrate diode are respectively attached to the corresponding base islands by using an adhesive.
3. The chip package structure using a multi-base-island lead frame according to claim 1, wherein the ground pin is directly connected to the first base island; or the first base island is of a concave structure, and the concave structure of the first base island is used as the grounding pin.
4. The chip package structure using multi-base island lead frame according to claim 1, wherein the first cathode is disposed opposite to the first anode and on a side of the corresponding base island near the first ac input pin.
5. The chip package structure using a multi-base-island lead frame according to claim 1, wherein the first ac input pin and the second ac input pin are located on a same side of the first base island away from the second base island.
6. The chip package structure using multi-base-island lead frame according to claim 1, wherein the first ac input pin is disposed opposite to the second ac input pin, and one of the first ac input pin and the second ac input pin is located at a side of a pin electrically connected to the second base island.
7. The chip packaging structure using the multi-base-island lead frame according to claim 1, wherein the area of the first base island is greater than or equal to the area of the second base island, and two sides of the first base island are respectively connected to the corresponding connecting ribs.
8. The chip package structure using multi-base-island lead frame according to claim 1, further comprising a main control chip disposed on the first base island.
9. The chip package structure using multi-base-island lead frame according to claim 8, wherein at least one of the main control chip, the double-N substrate diode and the double-P substrate diode has an included angle with a central axis of the chip package structure.
10. The chip package structure using a multi-base-island lead frame according to claim 1 or 8, further comprising an N-substrate freewheeling device disposed on the second base island.
11. The chip packaging structure using the multi-base-island lead frame according to claim 1 or 8, wherein a third base island is further disposed on the multi-base-island lead frame, and the chip packaging structure further comprises a P-substrate freewheeling device and/or a switching device disposed on the third base island.
12. The chip package structure using a multi-base-island lead frame according to claim 11, wherein the third base island is connected to a connecting rib.
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| CN202020339596.9U Active CN211238250U (en) | 2019-12-13 | 2020-03-18 | Chip packaging structure adopting multi-base-island lead frame |
| CN202020339540.3U Active CN211150558U (en) | 2019-12-13 | 2020-03-18 | Chip packaging structure adopting multi-base-island lead frame |
| CN202010189762.6A Pending CN111180437A (en) | 2019-12-13 | 2020-03-18 | Chip packaging structure adopting multi-base-island lead frame |
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| JPS63150954A (en) * | 1986-12-16 | 1988-06-23 | Toshiba Corp | Bridge type semiconductor device |
| JP5067679B2 (en) * | 2010-05-21 | 2012-11-07 | 株式会社デンソー | Semiconductor module and driving device using the same |
| CN102157480A (en) * | 2011-01-30 | 2011-08-17 | 常州银河世纪微电子有限公司 | Bridge rectifier |
| CN102842572A (en) * | 2011-06-24 | 2012-12-26 | 上海金克半导体设备有限公司 | Small double-row bridge rectifier |
| CN207753003U (en) * | 2017-12-28 | 2018-08-21 | 上海东软载波微电子有限公司 | Encapsulating structure |
| CN110010599A (en) * | 2019-04-25 | 2019-07-12 | 广东美的制冷设备有限公司 | Highly integrated intelligent power module and preparation method thereof and air conditioner |
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| CN111180437A (en) | 2020-05-19 |
| CN211150558U (en) | 2020-07-31 |
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