CN211150558U - Chip packaging structure adopting multi-base-island lead frame - Google Patents

Chip packaging structure adopting multi-base-island lead frame Download PDF

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Publication number
CN211150558U
CN211150558U CN202020339540.3U CN202020339540U CN211150558U CN 211150558 U CN211150558 U CN 211150558U CN 202020339540 U CN202020339540 U CN 202020339540U CN 211150558 U CN211150558 U CN 211150558U
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base
island
base island
lead frame
package structure
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李阳德
周占荣
徐鹏
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Shanghai Bright Power Semiconductor Co Ltd
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Shanghai Bright Power Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model discloses a chip packaging structure adopting a multi-base-island lead frame, which is characterized in that a diode with double N substrates and two diodes with N substrates are respectively arranged on three different base islands to form a diode rectifier bridge stack; compared with the traditional four independent diode rectifier bridge stacks, the scheme is simpler to realize, easier to operate and lower in cost.

Description

Chip packaging structure adopting multi-base-island lead frame
Technical Field
The utility model relates to a semiconductor package technical field especially relates to an adopt chip packaging structure of many base island lead frame.
Background
With the rapid development of the IC design and manufacture industries, the packaging technology is greatly improved. Packaging is an important part of the whole integrated circuit manufacturing process, and has heat dissipation and protection functions. The packaging process can seal the chip and isolate the damage of external pollution and external force to the chip.
With the progress of technology, packaging a single chip in one package has not been satisfactory. Packaging multiple chips in one package is becoming the direction of technology development. The chip area is smaller and smaller, the power is larger and larger, the use environment is more and more limited, the heat dissipation requirement is higher and higher, the market competition is more and more intense, and the cost competition is particularly prominent.
At present, an input rectifier bridge, a freewheeling diode and a drive IC in a drive circuit are separated, and belong to different packaged components, and multiple times of board mounting is needed in actual production in a factory, so that the cost of the components is high, and the size of a circuit board is large.
Fig. 1A and 1B are also shown, in which fig. 1A is a schematic circuit diagram of a conventional input rectifier bridge, and fig. 1B is a schematic diagram of a diode package.
As shown in fig. 1A, a conventional input rectifier bridge generally includes four independent diodes (D1-D4) to rectify an input AC and output a DC.
As shown in fig. 1B, in the case of the N-substrate diode 11, when it is packaged, the bottom of the diode is electrically connected to the base island of the lead frame and the top is an anode (i.e., N-substrate), and it can be electrically connected to other components through metal leads, as shown in part a in fig. 1B; for the P-substrate diode 12, when packaged, the bottom is electrically connected to the base island of the lead frame and the top is the cathode (i.e., P-substrate), and can be electrically connected to other components through metal leads, as shown in part B of fig. 1B.
When four independent diodes are packaged, a plurality of independent base islands, multiple times of glue dispensing and core loading are needed, the scheme is complicated, the production capacity (UPH) is low, and the cost is high.
Disclosure of Invention
An object of the utility model is to provide an adopt chip packaging structure of polybase island lead frame to the technical problem who exists among the prior art, can reduce components and parts in the factory production, realize material cost reduction, packaging structure's circuit board volume advantage such as littleer.
In order to achieve the above object, the utility model provides an adopt chip packaging structure of polybase island lead frame, include: the multi-base-island lead frame comprises a first-class pin, and a second base island, a third base island and a fourth base island which are electrically isolated from each other; the first type of pins comprise a first alternating current input pin, a second alternating current input pin, a bus pin and a grounding pin, the distance between every two adjacent pins is larger than a preset distance value, the bus pin is directly connected with the second base island, the first alternating current input pin is directly connected with the third base island, and the second alternating current input pin is directly connected with the fourth base island; the double-N substrate diode is arranged on the second base island, and comprises a first anode, a second anode and a shared cathode, wherein the cathode of the double-N substrate diode is electrically connected with the second base island and the bus pin through the second base island, the first anode of the double-N substrate diode is electrically connected with the first alternating current input pin through a metal lead wire, and the second anode of the double-N substrate diode is electrically connected with the second alternating current input pin through a metal lead wire; two opposite side edges of the double-N substrate diode are parallel to a central axis of the chip packaging structure or form an included angle; a first N-substrate diode disposed on the third base island, having a cathode electrically connected to the third base island and electrically connected to the first ac input pin via the third base island, and having an anode electrically connected to the ground pin via a metal lead; and the second N-substrate diode is arranged on the fourth base island, the cathode of the second N-substrate diode is electrically connected with the fourth base island and the second alternating current input pin through the fourth base island, and the anode of the second N-substrate diode is electrically connected with the grounding pin through a metal lead.
The utility model has the advantages that: the utility model discloses a put a two N substrate diodes and two N substrate diodes respectively on three different base island, constitute diode rectifier bridge heap, compare four traditional independent diode rectifier bridge heaps, this scheme realizes simpler, the operation is easier, the cost is lower. By further sealing the diode rectifier bridge stack and one or more of the drive IC, the fly-wheel diode, the MOS tube and the like in a packaging structure, the integration level of the chip is improved, and the cost of the whole circuit is reduced; the base islands in the packaging structure are electrically isolated, and the distance between the pins is large enough, so that high-voltage breakdown can be effectively prevented, and the requirements of packaging or reliability are met.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1A is a schematic circuit diagram of a conventional input rectifier bridge;
fig. 1B is a schematic diagram of a diode package.
Fig. 2 is a schematic plan view of a first embodiment of a chip package structure using a multi-base island lead frame according to the present invention;
fig. 3 is a schematic plan view of a second embodiment of a chip package structure using a multi-base island lead frame according to the present invention;
fig. 4A is a schematic plane structure diagram of a third embodiment of the chip packaging structure using a multi-base island lead frame according to the present invention;
FIG. 4B is a schematic diagram of FIG. 4A after wire bonding;
fig. 5A is a schematic plane structure diagram of a fourth embodiment of the chip packaging structure using a multi-base island lead frame according to the present invention;
fig. 5B is a schematic plan view of a fifth embodiment of a chip package structure using a multi-base island lead frame according to the present invention;
fig. 5C is a schematic plane structure diagram of a sixth embodiment of the chip packaging structure using the multi-base island lead frame according to the present invention;
fig. 5D is a schematic plane structure diagram of a seventh embodiment of the chip packaging structure using the multi-base island lead frame according to the present invention;
fig. 6 is a schematic plane structure diagram of an eighth embodiment of the chip packaging structure using a multi-base island lead frame according to the present invention;
fig. 7 is a schematic diagram of a wire bonding rear plane structure of a ninth embodiment of the chip packaging structure using the multi-base island lead frame according to the present invention;
fig. 8 is a schematic plan view of a tenth embodiment of a chip package structure using a multi-base island lead frame according to the present invention;
fig. 9 is a schematic plan view of an eleventh embodiment of a chip packaging structure using a multi-base island lead frame according to the present invention;
fig. 10 is a schematic plan view of a twelfth embodiment of a chip package structure using a multi-base island lead frame according to the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without any creative work belong to the protection scope of the present invention. The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
The utility model discloses a put a two N substrate diodes and two N substrate diodes respectively on three different base island, constitute diode rectifier bridge heap, compare four traditional independent diode rectifier bridge heaps, this scheme realizes simpler, the operation is easier, the cost is lower. The diode rectifier bridge stack and one or more of a drive IC, a freewheeling diode, an MOS tube and the like are sealed in a packaging structure, so that a sealed chip with high integration level is formed. The double-N substrate diode is two diodes formed on the same N substrate and comprises a first anode, a second anode and a shared cathode.
The utility model discloses can adopt any suitable encapsulation standard to form packaging structure. In the package structure in the following embodiments, the SOP-6 or ESOP-6 package specifications were selected for demonstration in relation to a 6-pin package. Wherein, the length of the SOP-6 and ESOP-6 packages is 4.84-4.96mm, the width is 3.84-3.96mm, the number of pins is 6, and the width of the pins is 0.35-0.47 mm. By adopting the packaging specification, the packaging body can keep smaller size and bear higher power density on the premise of keeping high integration level. Those skilled in the art will appreciate that the application of the present invention is not limited to the above package format, for example, in the following embodiments, the package structure involving 8 pins is demonstrated using the SOP-8 package specification. In the case of a 7-pin package structure, a mixture of SOP-6 and SOP-8 package specifications is used (i.e., SOP-6 package specifications are used for a 3-pin portion on one side and SOP-8 package specifications are used for a 4-pin portion on one side). In other embodiments, other package specifications, such as QFN, DFN, etc., may also be used to implement the present invention.
Referring to fig. 2, the present invention is a schematic plan view of a chip package structure with multiple base islands according to a first embodiment.
In this embodiment, the chip package structure includes a multi-base-island lead frame, a dual-N-substrate diode 22, and two N-substrate diodes (a first N-substrate diode 23 and a second N-substrate diode 24).
Specifically, the multi-base-island lead frame is a three-base-island lead frame, and the packaging line of the three-base-island lead frame is schematically marked by a graphic frame 208. In this embodiment, the multi-base-island lead frame includes a plurality of first-type pins and three base islands electrically isolated from each other, which are a second base island 202, a third base island 203 and a fourth base island 204; wherein an area of the third base island 203 may be equal to an area of the fourth base island 204. Optionally, at least one side of the second base island 202 is connected with a Tie bar 209, so that the stability of the base island is improved.
The first class of pins includes at least a first alternating current (AC1) input pin, a second alternating current (AC2) input pin, a BUS (BUS) pin, and a Ground (GND) pin. For example, the 4 pins (pin1 to pin4) of the three-island lead frame are: pin1 is a first alternating current (AC1) input pin1, pin2 is a BUS (BUS) pin2, pin3 is a Ground (GND) pin3, and pin4 is a second alternating current (AC2) input pin 4. The distance between every two adjacent pins is large enough (the distance between every two adjacent pins is larger than a preset distance value), so that the high-voltage breakdown risk is effectively reduced. Preferably, the BUS (BUS) pin2 is directly connected to the second base island 202, the first alternating current (AC1) input pin1 is directly connected to the third base island 203, and the second alternating current (AC2) input pin is directly connected to the fourth base island 204.
The double-N substrate diode 22 is attached to the second base island 202 by an adhesive such as a conductive adhesive. The double N-substrate diode 22 includes a first anode, a second anode, and a common cathode, the cathode of which is electrically connected to the second base island 202 and to the BUS (BUS) pin2 via the second base island 202; the first anode (N-substrate) is electrically connected to the first alternating current (AC1) input pin1 through the metal lead 29, and the second anode is electrically connected to the second alternating current (AC2) input pin4 through the metal lead 29. In this embodiment, the cathode of the double N-substrate diode 22 is directly electrically connected to the BUS (BUS) pin 2; in other embodiments, the cathode of the double N-substrate diode 22 may also be electrically connected to the BUS (BUS) pin2 by a conductive paste or a metal wire.
The first N-substrate diode 23 is attached to the third base island 203 with an adhesive such as a conductive adhesive, and has a cathode electrically connected to the third base island 203, and electrically connected to the first alternating current (AC1) input pin1 via the third base island 203, and an anode electrically connected to the Ground (GND) pin3 via a metal lead 29. In other embodiments, the cathode of the first N-substrate diode 23 may also be electrically connected to the first alternating current (AC1) input pin1 through a conductive adhesive or a metal wire.
The second N-substrate diode 24 is attached to the fourth base island 204 by an adhesive such as a conductive adhesive, and has a cathode electrically connected to the fourth base island 204, and electrically connected to the second alternating current (AC2) input pin4 through the fourth base island 204, and an anode electrically connected to the Ground (GND) pin3 through a metal lead 29. In other embodiments, the cathode of the second N-substrate diode 24 may also be electrically connected to the second alternating current (AC2) input pin4 through a conductive adhesive or a metal wire.
In the embodiment, a diode rectifier bridge stack is formed by respectively placing one double-N substrate diode and two N substrate diodes on three different base islands, so that fewer dispensing and core loading times are realized, the production efficiency is improved, and the production cost is reduced.
Referring to fig. 3, the present invention is a schematic plan view of a chip package structure with multiple base islands according to a second embodiment.
In this embodiment, the chip package structure includes a multi-base-island lead frame, a main control chip 21, a dual-N-substrate diode 22, and two N-substrate diodes (a first N-substrate diode 23 and a second N-substrate diode 24).
In this embodiment, the multi-base-island lead frame includes four base islands, which are electrically isolated from each other, namely a first base island 201, a second base island 202, a third base island 203 and a fourth base island 204. The area of the first base island 201 is the largest, the area of the second base island 202 is the second, and the area of the third base island 203 may be equal to the area of the fourth base island 204. The packaging line of the multi-base island lead frame is schematically marked by a graphic wire frame 208.
The first base island 201 is located in the middle of the multi-base island lead frame, and two sides of the first base island are respectively connected with a connecting rib (Tie bar)209, so that the stability of the base island is improved. The second base island 202 and the third base island 203 are arranged side by side and are positioned on the first side of the first base island 201; the fourth base island 204 is disposed opposite to the third base island 203 and on a second side of the first base island 201. The second side and the first side are opposite sides of the first base island 201.
The multi-base-island lead frame at least comprises 6 pins (pin 1-pin 6), in the embodiment, pin1 is a first alternating current (AC1) input pin1, pin2 is a BUS (BUS) pin2, pin3 is a second Drain terminal (Drain2) pin3, pin4 is a first Drain terminal (Drain1) pin4, pin5 is a feedback (CS) pin5, and pin6 is a second alternating current (AC2) input pin 6. Wherein the first alternating current (AC1) input pin1, the BUS (BUS) pin2, and the second alternating current (AC2) input pin6 are directly connected to the corresponding base island. Meanwhile, the distance between the pins is large enough (larger than a preset distance value), so that the high-voltage breakdown risk is effectively reduced.
Figure 3 shows a debossing product, which facilitates heat dissipation. Specifically, the first base island 201 is a recessed structure, and the first base island 201 is recessed and then Grounded (GND) as a ground pin.
The main control chip 21 is attached to the first base island 201 by an adhesive such as a conductive adhesive, and is electrically connected to the first base island 201 and some of the plurality of leads of the multi-base-island lead frame by metal leads 29. For example, the main control chip 21 is electrically connected to the first base island 201 (for GND connection), the second Drain terminal (Drain2) pin3, the first Drain terminal (Drain1) pin4, and the feedback (CS) pin5 through metal wires 29. The main control chip 21 is an integrated circuit chip (IC), such as a driver IC, for controlling other devices. Two opposite side edges of the main control chip 21 are parallel to a central axis of the chip package structure, for example, the main control chip 21 is disposed parallel to a longitudinal central axis 207 of the chip package structure.
The double-N substrate diode 22 is attached to the second base island 202 by an adhesive such as a conductive adhesive, the cathode of the diode is electrically connected to the leads on the second base island 202, and the anode (i.e., the N substrate) of the diode is electrically connected to some of the leads of the multi-base island lead frame through a metal lead 29. For example, the cathode of the double N-substrate diode 22 is electrically connected to the BUS (BUS) pin2 on the second base island 202, the first anode of the double N-substrate diode 22 is electrically connected to the first alternating current (AC1) input pin1 through the metal wire 29, and the second anode is electrically connected to the second alternating current (AC2) input pin6 through the metal wire 29. In other embodiments, the cathode of the double N-substrate diode 22 may also be electrically connected to the BUS (BUS) pin2 by a conductive paste or a metal wire.
The first N-substrate diode 23 is attached to the third base island 203 with an adhesive such as a conductive adhesive, a cathode of the first N-substrate diode is electrically connected to a pin on the third base island 203, and an anode of the first N-substrate diode is electrically connected to the first base island 201 where the main control chip 21 is located through a metal lead 29. For example, the cathode of the first N-substrate diode 23 is electrically connected to the first alternating current (AC1) input pin1 on the third base island 203, and the anode thereof is electrically connected to the first base island 201 through a metal wire 29, thereby being Grounded (GND). For another example, the cathode of the first N-substrate diode 23 may be connected to the first alternating current (AC1) input pin1 through a conductive adhesive or a metal lead.
The second N-substrate diode 24 is attached to the fourth base island 204 by an adhesive such as a conductive adhesive, a cathode of the second N-substrate diode is electrically connected to a pin on the fourth base island 204, and an anode of the second N-substrate diode is electrically connected to the first base island 201 where the main control chip 21 is located through a metal lead 29. For example, the cathode of the second N-substrate diode 24 is electrically connected to the second alternating current (AC2) input pin6 on the fourth base island 204, and the anode thereof is electrically connected to the first base island 201 through a metal wire 29, thereby being Grounded (GND). For another example, the cathode of the second N-substrate diode 24 may be connected to the second alternating current (AC2) input pin6 through a conductive adhesive or a metal lead.
In the embodiment, a diode rectifier bridge stack is formed by respectively placing one double-N substrate diode and two N substrate diodes on three different base islands, so that fewer dispensing and core loading times are realized, the production efficiency is improved, and the production cost is reduced. By further sealing the diode rectifier bridge stack and the drive IC in a packaging structure, a sealed chip with high integration level is formed, and the cost of the whole circuit is reduced.
Fig. 4A and 4B are also shown, wherein fig. 4A is a schematic diagram of a planar structure of a chip packaging structure of a multi-base-island lead frame according to a third embodiment of the present invention, and fig. 4B is a schematic diagram of fig. 4A after wire bonding, in which a wire bonding area is indicated by a grid.
The difference from the embodiment shown in fig. 3 is that, in this embodiment, the third base island 203, the second base island 202, and the fourth base island 204 are arranged in sequence and are all located on the same side of the first base island 201; that is, the third base island 203 and the fourth base island 204 are respectively located at both sides of the second base island 202. Meanwhile, an included angle is formed between two opposite side edges of the main control chip 21 and a central axis of the chip packaging structure. For example, the main control chip 21 has an included angle θ with respect to the longitudinal central axis 207 of the chip package structure, that is, two opposite sides of the main control chip 21 are disposed non-parallel to the longitudinal central axis 207 of the chip package structure.
Correspondingly, the electrical characteristics of the 6 pins (pin 1-pin 6) are adjusted. Specifically, pin1 is a first alternating current (AC1) input pin1, pin2 is a BUS (BUS) pin2, pin3 is a second alternating current (AC2) input pin3, pin4 is a second Drain (Drain2) pin4, pin5 is a first Drain (Drain1) pin5, and pin6 is a feedback (CS) pin 6. Wherein, the first alternating current (AC1) input pin1, the BUS (BUS) pin2 and the second alternating current (AC2) input pin3 are still directly connected with the corresponding base island; and the first alternating current (AC1) input pin1, the second alternating current (AC2) input pin3 and the BUS (BUS) pin2 are all positioned on the same side of the multi-base island lead frame. Meanwhile, the distance between the pins is large enough (larger than a preset distance value), so that the high-voltage breakdown risk is effectively reduced.
The third base island 203, the second base island 202 and the fourth base island 204 are sequentially arranged, so that the length of the metal lead 29 electrically connected with the first alternating current (AC1) input pin1 and the second alternating current (AC2) input pin3 of the double-N substrate diode 22 is effectively shortened.
The main control chip 21 is relative after the vertical axis 207 of the chip packaging structure rotates by an angle theta, the main control chip 21 is relative the vertical axis 207 of the chip packaging structure is a rotary inclined layout of a drive IC with an included angle theta, so that the routing operation in a routing area is more convenient, the close routing can be prevented from being contacted or broken down in a short distance, and the main control chip 21 is also convenient for being electrically connected with corresponding pins. The deflection direction and the deflection angle theta of the main control chip 21 relative to the longitudinal central axis 207 of the chip packaging structure can be set according to actual requirements, and the included angle theta can be larger than 0 degree and smaller than 90 degrees.
Referring to fig. 5A, the present invention is a schematic plan view of a fourth embodiment of a chip packaging structure with a multi-base island lead frame. The difference from the embodiment shown in fig. 4A is that, in this embodiment, the third base island 203, the fourth base island 204, and the second base island 202 are arranged in sequence and are all located on the same side of the first base island 201; that is, the third base island 203 and the fourth base island 204 are located on the same side of the second base island 202.
Correspondingly, the electrical characteristics of the 6 pins (pin 1-pin 6) are adjusted. Specifically, pin1 is a first alternating current (AC1) input pin1, pin2 is a second alternating current (AC2) input pin2, pin3 is a BUS (BUS) pin3, pin4 is a Drain (Drain) pin4, pin5 is a Null (NC) pin5, and pin6 is a feedback (CS) pin 6. Wherein, the first alternating current (AC1) input pin1, the BUS (BUS) pin2 and the second alternating current (AC2) input pin3 are still directly connected with the corresponding base island; and the first alternating current (AC1) input pin1, the second alternating current (AC2) input pin3 and the BUS (BUS) pin2 are arranged in sequence and are positioned on the same side of the multi-base island lead frame. The improved pin position arrangement enables the wiring of the peripheral circuit of the packaged sealed chip to be easier. The peripheral wiring can be realized by adopting a single-layer PCB, the cost is low, and the problems that the complicated peripheral wiring needs to adopt a double-layer PCB and the cost is increased are solved. Meanwhile, the distance between the pins is large enough (larger than a preset distance value), so that the high-voltage breakdown risk is effectively reduced.
The third base island 203, the fourth base island 204 and the second base island 202 are sequentially arranged, so that the length of the metal lead 29 electrically connected with the first alternating current (AC1) input pin1 and the second alternating current (AC2) input pin2 of the double-N substrate diode 22 is effectively shortened.
Please refer to fig. 5B, a schematic diagram of a planar structure of a fifth embodiment of a chip package structure using a multi-base-island lead frame according to the present invention is different from the embodiment shown in fig. 5A, in which two opposite sides of the double N-substrate diode 22 and a central axis (e.g., the illustrated transverse central axis 206) of the chip package structure have an included angle β, that is, after the double N-substrate diode 22 rotates by an angle β with respect to the transverse central axis 206 of the chip package structure, the double N-substrate diode 22 is tilted with respect to the transverse central axis 206 of the chip package structure, which is more beneficial to the layout of the metal leads 29 electrically connected to the first alternating current (AC1) input pin1 and the second alternating current (AC2) input pin2 of the double N-substrate diode 22, respectively, so as to prevent the adjacent wires from contacting or breaking through.
The deflection direction and the deflection angle β of the double-N substrate diode 22 with respect to the transverse central axis 206 of the chip package structure can be set according to actual requirements, and the included angle β can be greater than 0 degree and smaller than 90 degrees, for example, in this embodiment, the included angle β is 15 degrees, and the included angle θ of the main control chip 21 with respect to the longitudinal central axis 207 of the chip package structure is 75 degrees.
In a further embodiment, two opposite sides of the second N-substrate diode 24 and a central axis (such as the illustrated transverse central axis 206) of the chip package structure are disposed in an inclined manner, so as to further facilitate the routing layout of the metal leads 29 electrically connected to the first alternating current (AC1) input pin1 and the second alternating current (AC2) input pin2 of the double N-substrate diode 22, respectively.
In a further embodiment, of the third base island 203 and the fourth base island 204, a base island close to the second base island 202 extends toward the first base island 201 to form a protrusion. The shape of the bulge can be rectangular or chamfered rectangular. Accordingly, the components on the base island formed with the bumps are disposed close to the bumps to further facilitate the routing layout of the metal leads 29 electrically connected to the first alternating current (AC1) input pin1 and the second alternating current (AC2) input pin2 of the double N-substrate diode 22, respectively.
In fig. 5C, the plane structure diagram of the sixth embodiment of the chip packaging structure with a multi-base-island lead frame of the present invention is shown, the fourth base island 204a close to the second base island 202 extends toward the first base island 201 to form a protrusion 501a, and the protrusion 501a is rectangular.
In fig. 5D, the utility model discloses a planar structure schematic diagram of a chip packaging structure seventh embodiment of many baseislands lead frame is shown, be close to fourth baseisland 204b of second baseisland 202 to first baseisland 201 direction extends and forms a arch 501b, arch 501 b's shape is the chamfered rectangle.
Referring to fig. 6, the present invention is a schematic plan view of an eighth embodiment of a chip packaging structure with a multi-base island lead frame.
The difference from the embodiment shown in fig. 3 is that in this embodiment, the chip packaging structure further includes an N substrate component, and the N substrate component is disposed on the second base island 202 a; the first base island 201a is a non-recessed structure, and is directly connected with a Ground (GND) pin; meanwhile, the main control chip 21 on the first base island 201a has an included angle θ with respect to the longitudinal central axis 207 of the chip package structure.
Specifically, the N-substrate component is an N-substrate freewheeling component, such as a third N-substrate diode 25 a; that is, a double N-substrate diode 22 and a third N-substrate diode 25a are disposed on the second base island 202 a. The third N substrate diode 25a is disposed on the second base island 202a at an end away from the third base island 203, so as to facilitate electrical connection between the components.
Correspondingly, the electrical characteristics of the 6 pins (pin 1-pin 6) are adjusted. Specifically, pin1 is a first alternating current (AC1) input pin1, pin2 is a BUS (BUS) pin2, pin3 is a Drain (Drain) pin3, pin4 is a feedback (CS) pin4, pin5 is a Ground (GND) pin5, and pin6 is a second alternating current (AC2) input pin 6. Wherein the first alternating current (AC1) input pin1, the BUS (BUS) pin2, and the second alternating current (AC2) input pin3 are directly connected to the corresponding base island. Meanwhile, the distance between the pins is large enough (larger than a preset distance value), so that the high-voltage breakdown risk is effectively reduced.
Specifically, the cathode of the third N-substrate diode 25a is electrically connected to the pin (bus pin 2) on the second base island 202, and the anode thereof is electrically connected to the drain terminal pin3 and the main control chip 21 respectively through the metal lead 29. In other embodiments, the cathode of the third N substrate diode 25a may also be electrically connected to the BUS (BUS) pin2 by a conductive adhesive or a metal wire. The third N-substrate diode 25a may be used as a freewheeling diode of the switching power supply when the package structure is applied to an actual circuit structure.
In the embodiment, a diode rectifier bridge stack is formed by respectively placing one double-N substrate diode and two N substrate diodes on three different base islands, so that fewer dispensing and core loading times are realized, the production efficiency is improved, and the production cost is reduced. The diode rectifier bridge stack, the driving IC and the freewheeling diode are sealed in a packaging structure to form a high-integration sealed chip, so that the cost of the whole circuit is reduced. Meanwhile, the main control chip 21 is arranged in a rotating and inclined manner, so that the wire bonding operation in a wire bonding area is more convenient.
In other embodiments, the main control chip 21 and the corresponding first base island 201a may not be disposed in the chip package structure, and the connection relationship between the components in the package structure and the pins of the package structure may be adaptively adjusted.
Referring to fig. 7, the present invention is a schematic diagram of a wire bonding rear plane structure of a ninth embodiment of a chip packaging structure with multiple base islands lead frames, in which a wire bonding area is indicated by a grid.
The difference from the embodiment shown in fig. 6 is that, in this embodiment, an end of the second base island 202b far from the third base island 203 extends to the position of the Tie bar 2091 in the direction of the first base island 201 and is connected to the corresponding Tie bar 2091 to form a sub-placement area; the third N substrate diode 25a is disposed in the sub-placement region, so that the third N substrate diode 25a is closer to the main control chip 21, thereby facilitating electrical connection between the components. Meanwhile, the second base island 202b is connected with a reinforcement bar 2091, so that the stability of the base island is further improved, the base island is prevented from being inclined, and the risk of wire bonding errors is reduced. The driving IC rotates the inclined layout, so that the routing operation in the routing area is more convenient. Accordingly, the first base island 201b is connected to a tie bar 2092 to improve the stability of the base island.
In other embodiments, the main control chip 21 and the corresponding first base island 201 may not be disposed in the chip package structure, and the connection relationship between the components in the package structure and the pins of the package structure may be adaptively adjusted.
Referring to fig. 8, the present invention is a schematic plan view of a tenth embodiment of a chip package structure using a multi-base island lead frame.
The difference from the embodiment shown in fig. 6 is that in this embodiment, the multi-base-island lead frame further includes a fifth base island 205a, and the fifth base island 205a is connected to a tie bar 2091 and is directly connected to a pin (drain terminal pin 3) of the multi-base-island lead frame. The fifth base island 205a is positioned substantially side by side with the fourth base island 203 and on both sides of the first base island 201 c. Accordingly, the first base island 201c is connected to a tie bar 2092 to improve the stability of the base island.
A switch component, such as an N-type MOS transistor 26, is disposed on the fifth base island 205a, and the MOS transistor 26 is electrically connected to a pin (drain terminal pin 3) on the fifth base island 205a, and is also electrically connected to the feedback (CS) pin4 and the main control chip 21 through metal leads 29; the main control chip 21 is electrically connected to the second base island 202a through a metal lead 29, and the third N-substrate diode 25a and the main control chip 21 are not directly connected. The MOS transistor 26 can be used as a power switch transistor of a switching power supply when the chip package structure is actually applied to a circuit structure. In other embodiments, a P-substrate freewheeling device, such as a P-substrate freewheeling diode, may be disposed on the fifth base island 205a, and may be used as a freewheeling diode of a switching power supply when the package structure is actually applied to a circuit structure. Alternatively, a P-substrate freewheeling device and a switching device may be disposed on the fifth base island 205a at the same time.
In the embodiment, a diode rectifier bridge stack is formed by respectively placing one double-N substrate diode and two N substrate diodes on three different base islands, so that fewer times of dispensing and core loading are realized, the production efficiency is improved, and the production cost is reduced. By further sealing the diode rectifier bridge stack, the driving IC, the freewheeling diode and the MOS tube in a packaging structure, the chip integration level is greatly improved, and the cost of the whole circuit is reduced.
In other embodiments, only the double N-substrate diode 22 may be disposed on the second base island 202 c.
In other embodiments, the main control chip 21 and the corresponding first base island 201 may not be disposed in the chip package structure, and the connection relationship between the components in the package structure and the pins of the package structure may be adaptively adjusted.
Referring to fig. 9, the present invention is a schematic plan view of a chip package structure with multiple base islands according to an eleventh embodiment.
The difference from the embodiment shown in fig. 8 is that, in this embodiment, the fifth base island 205b extends toward the second base island 202c, and a P-substrate freewheeling device is disposed in the extending portion; that is, the switching device and the P-substrate freewheeling device are provided on the fifth base island 205b at the same time. Specifically, the switch component is an N-type MOS transistor 26, and the P-substrate freewheeling component is a P-substrate diode 25 b. That is, the P-substrate diode 25b as a freewheeling diode and the N-type MOS transistor 26 are both provided on the fifth base island 205 b. Accordingly, only the double N-substrate diode 22 is disposed on the second base island 202 c. In other embodiments, the double N-substrate diode 22 and an N-substrate component (e.g., the aforementioned N-substrate diode 25a) may also be disposed on the second base island 202 c.
The anode of the P-substrate diode 25b is electrically connected to a pin (drain terminal pin 3) on the fifth base island 205b, and the cathode thereof is connected to the second base island 202c where the double-N-substrate diode 22 is located through a metal wire 29; the MOS tube 26 is electrically connected to a pin (drain terminal pin 3) on the fifth base island 205b, and is also electrically connected to the feedback (CS) pin4 and the main control chip 21 through metal leads 29.
In other embodiments, the main control chip 21 and the corresponding first base island 201 may not be disposed in the chip package structure, and the connection relationship between the components in the package structure and the pins of the package structure may be adaptively adjusted.
Referring to fig. 10, the present invention is a schematic plan view of a twelfth embodiment of a chip package structure using a multi-base island lead frame.
The difference from the embodiment shown in fig. 6 is that in this embodiment, the multi-base-island lead frame further includes a fifth base island 205c, and the third base island 203, the second base island 202a, and the fifth base island 205c are arranged in sequence and all located on the same side of the first base island 201 a. A P-substrate freewheeling device is disposed on the fifth base island 205 c.
Specifically, the P-substrate freewheeling component is a P-substrate diode 25c, the P-substrate diode 25c is attached to the fifth base island 205c by using an adhesive such as a conductive adhesive, the anode of the P-substrate diode is electrically connected to a pin (drain terminal pin 3) on the fifth base island 205c, and the cathode of the P-substrate diode is connected to the second base island 202a where the double-N-substrate diode 22 is located through a metal lead 29. In other embodiments, the anode of the P-substrate diode 25c and the pin on the fifth base island 205 can also be connected through a conductive paste or a metal wire.
The main control chip 21 is further connected to the second base island 202a where the double N-substrate diode 22 is located and the fifth base island 205c where the P-substrate diode 25c is located through metal wires 29, respectively. The P-substrate diode 25c may be used as a freewheeling diode when the package structure is applied to an actual circuit structure.
In the embodiment, a diode rectifier bridge stack is formed by respectively placing one double-N substrate diode and two N substrate diodes on three different base islands, so that fewer times of dispensing and core loading are realized, the production efficiency is improved, and the production cost is reduced. The diode rectifier bridge stack, the driving IC and the freewheeling diode are sealed in a packaging structure, so that the chip integration level is further improved. Meanwhile, the main control chip is in a rotary inclined layout, so that the routing operation in a routing area is more convenient.
It should be noted that the chip package structure may only include a multi-base-island lead frame, a dual-N-substrate diode 22, two N-substrate diodes (a first N-substrate diode 23 and a second N-substrate diode 24), and a freewheeling diode or a MOS transistor. That is, the main control chip 21 and the corresponding first base island 201a are not disposed in the chip package structure, and the connection relationship between the components in the package structure and the pins of the package structure are adaptively adjusted.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims (15)

1. The utility model provides an adopt chip package structure of many baseisland lead frame which characterized in that includes:
the multi-base-island lead frame comprises a first-class pin, and a second base island, a third base island and a fourth base island which are electrically isolated from each other; the first type of pins comprise a first alternating current input pin, a second alternating current input pin, a bus pin and a grounding pin, the distance between every two adjacent pins is larger than a preset distance value, the bus pin is directly connected with the second base island, the first alternating current input pin is directly connected with the third base island, and the second alternating current input pin is directly connected with the fourth base island;
the double-N substrate diode is arranged on the second base island, and comprises a first anode, a second anode and a shared cathode, wherein the cathode of the double-N substrate diode is electrically connected with the second base island and the bus pin through the second base island, the first anode of the double-N substrate diode is electrically connected with the first alternating current input pin through a metal lead wire, and the second anode of the double-N substrate diode is electrically connected with the second alternating current input pin through a metal lead wire; two opposite side edges of the double-N substrate diode are parallel to a central axis of the chip packaging structure or form an included angle;
a first N-substrate diode disposed on the third base island, having a cathode electrically connected to the third base island and electrically connected to the first ac input pin via the third base island, and having an anode electrically connected to the ground pin via a metal lead;
and the second N-substrate diode is arranged on the fourth base island, the cathode of the second N-substrate diode is electrically connected with the fourth base island and the second alternating current input pin through the fourth base island, and the anode of the second N-substrate diode is electrically connected with the grounding pin through a metal lead.
2. The chip package structure using multi-base-island lead frame according to claim 1, wherein the double N-substrate diode, the first N-substrate diode and the second N-substrate diode are respectively attached to the corresponding base island by using an adhesive.
3. The chip package structure using a multi-base-island lead frame according to claim 1, wherein the chip package structure further comprises a main control chip, and a first base island is further disposed on the multi-base-island lead frame; the main control chip is arranged on the first base island.
4. The chip package structure using multi-base-island lead frame according to claim 3, wherein the first base island is a recessed structure, and the recessed first base island serves as the ground pin.
5. The chip package structure using multi-base-island lead frame according to claim 3, wherein two opposite sides of the main control chip are parallel to a central axis of the chip package structure or have an included angle.
6. The chip packaging structure adopting the multi-base-island lead frame according to claim 3, wherein the first base island is located in the middle of the multi-base-island lead frame, and two sides of the first base island are respectively connected with the connecting ribs; the second base island and the third base island are arranged side by side and are positioned on the first side of the first base island; the fourth base island and the third base island are arranged oppositely and positioned on the second side of the first base island; wherein the second side and the first side are opposite sides of the first base island.
7. The chip packaging structure adopting the multi-base-island lead frame according to claim 3, wherein two sides of the first base island are respectively connected with the connecting ribs; the second base island, the third base island and the fourth base island are all positioned on the same side of the first base island.
8. The chip package structure using multiple base island lead frames according to claim 3, wherein the first ac input pin, the second ac input pin, and the bus pin are located on the same side of the multiple base island lead frame.
9. The chip package structure using multi-base-island lead frame according to claim 7, wherein the third base island and the fourth base island are respectively located at two sides of the second base island.
10. The chip package structure with the multi-base-island lead frame according to claim 7, wherein the third base island and the fourth base island are located on the same side of the second base island, and two opposite sides of the double-N substrate diode have an included angle with a central axis of the chip package structure.
11. The chip package structure using multi-base-island lead frame according to claim 10, wherein a protrusion is formed by extending the base island close to the second base island toward the first base island in the third base island and the fourth base island.
12. The chip package structure using a multi-base-island lead frame according to claim 1 or 3, further comprising an N-substrate freewheeling device disposed on the second base island.
13. The chip package structure using a multi-base-island lead frame according to claim 12, wherein the second base island is connected to at least one connecting rib.
14. The chip packaging structure using the multi-base-island lead frame according to claim 1 or 3, wherein a fifth base island is further disposed on the multi-base-island lead frame, and the chip packaging structure further comprises a P-substrate freewheeling device and/or a switching device disposed on the fifth base island.
15. The chip package structure using multi-base island lead frame according to claim 14, wherein the fifth base island is connected to a connecting rib.
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