CN214378393U - 一种嵌入式芯片封装结构 - Google Patents

一种嵌入式芯片封装结构 Download PDF

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CN214378393U
CN214378393U CN202120234601.4U CN202120234601U CN214378393U CN 214378393 U CN214378393 U CN 214378393U CN 202120234601 U CN202120234601 U CN 202120234601U CN 214378393 U CN214378393 U CN 214378393U
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base island
package structure
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groove
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蔡择贤
张怡
程浪
冯学贵
卢茂聪
饶锡林
陈勇
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Guangdong Chippacking Technology Co ltd
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Abstract

本实用新型涉及一种嵌入式芯片封装结构，包括芯片、基岛、引脚、引线和塑封体，芯片通过装片胶固定在基岛上，基岛上表面设有凹槽，芯片背面通过去材料的方式形成凸块，凸块嵌入所述凹槽内，装片胶嵌入基岛上的凹槽内，并包裹芯片上的凸块。由于装片胶嵌入基岛上的凹槽内，芯片的凸块也会嵌入基岛的凹槽内，装片胶还会包裹凸块，在原有工艺和参数不变的情况下，增加了装片胶与芯片的接触面积，粘接力会更好，导热能力也会更好，根据电阻公式R＝ρl/S，本设计具有更大的接触面积S，更小的距离l，具有更低的基岛寄生电阻，导电能力也更强；另外，由于芯片相对下沉，与基岛的下表面传热距离更近，更容易将芯片工作时产生的热量传递出去。

Description

一种嵌入式芯片封装结构
技术领域
本实用新型涉及芯片封装技术领域，尤其涉及一种嵌入式芯片封装结构。
背景技术
如图1所示，为现有技术中最常见的一种封装结构，包括芯片1、基岛2、引脚3、引线4和塑封体5，芯片1通过装片胶6固定在基岛1上，装片胶6为导电胶，可以实现芯片1与基岛2之间的电连接，引线4用于实现芯片1和引脚3之间的电连接，塑封体5用于包裹和保护芯片1、基岛2、引脚3和引线4。由于芯片非常薄，尤其是芯片厚度在200μm以下的封装工艺中，需要控制装片胶的爬胶高度，所以装片胶的用量控制非常严格，过少会导致粘接不牢，还会影响芯片和基岛之间的导电性能，过多则爬胶过高，影响后序的工艺步骤，因此，涂覆装片胶工艺中，需要使用更高精度的设备和较慢涂胶的速度，影响生产效率，生产成本无法有效降低，有待改进。
实用新型内容
本实用新型的目的在于提供一种嵌入式芯片封装结构，可以提高芯片的导电导热和粘接性能。
本实用新型提供的技术方案为：一种嵌入式芯片封装结构，包括芯片、基岛、引脚、引线和塑封体，所述芯片通过装片胶固定在基岛上，所述引线用于实现芯片和引脚之间的电连接，塑封体用于包裹和保护芯片、基岛、引脚和引线，所述基岛上表面设有凹槽，所述芯片背面通过去材料的方式形成凸块，所述凸块嵌入所述凹槽内，所述装片胶嵌入基岛上的凹槽内，并包裹芯片上的凸块。
其中，所述基岛上凹槽的深度为基岛基材厚度的1/4-3/4。
其中，所述芯片上凸块的高度为芯片基材厚度的1/4-3/4。
其中，所述凹槽的深度数值大于或等于芯片上凸块的高度数值。
其中，所述凹槽形状为直条形、交错的直条形、曲线条形、圆形、环形或以上图形的组合，所述凸块与凹槽形状相适配。(此处的适配是指存在装片胶的情况下，凸块要能够轻松地嵌入凹槽内，所以凹槽的尺寸应稍大于凸块的尺寸)。
其中，所述凹槽的宽度为10-2000μm，深度为5-300μm。
其中，所述封装结构为DFN封装结构、QFN封装结构、ESOP封装结构、ECPC封装结构或EMSOP封装结构。
本实用新型的有益效果为：通过蚀刻或激光切除的方式在引线框架的基岛上制作出凹槽；在整片的晶圆背面刻划掉一部分材料，形成凸块，然后加工切割道，最后分裂成单个的芯片，这样每个芯片背面都被刻划出凸块来，在引线框架的基岛上涂覆好装片胶，放上芯片，凹槽和凸块的位置要精准对位，此时装片胶会嵌入基岛上的凹槽内，芯片的凸块也会嵌入基岛的凹槽内，装片胶还会包裹凸块，然后进行烘干，再进行后序的键合、塑封、电镀、切割及测试作业。由于装片胶嵌入基岛上的凹槽内，芯片的凸块也会嵌入基岛的凹槽内，装片胶还会包裹凸块，在原有工艺和参数不变的情况下，增加了装片胶与芯片的接触面积，粘接力会更好，导热能力也会更好，根据电阻公式R＝ρl/S，本设计比常规设计具有更大的接触面积S，更小的距离l，意味着具有更低的基岛寄生电阻，其导电能力也更强；在保证一定的粘接力的条件下，对装片胶的用量控制更宽容，可以使用稍低精度的设备和较快的涂胶速度，提高生产效率和降低生产成本；另外，由于芯片相对下沉，与基岛的下表面(此面为主要散热面)传热距离更近，更容易将芯片工作时产生的热量传递出去，增加导热能力；由于芯片部分嵌入基岛内，可实现封装产品厚度进一步减小，对于目前越做越薄的封装结构而言，封装其余工艺标准可以相应放宽，降低封装难度。
附图说明
图1是现有技术中常见封装结构的剖面示意图；
图2是本实用新型所述嵌入式芯片封装结构实施例的剖面示意图；
图3是本实用新型所述芯片和基岛实施例一的配合关系图；
图4是本实用新型所述芯片和基岛实施例二的配合关系图；
图5是本实用新型所述芯片和基岛实施例三的配合关系图；
图6是本实用新型所述芯片和基岛实施例四的配合关系图。
其中，1、芯片；11、凸块；2、基岛；21、凹槽；3、引脚；4、引线；5、塑封体；6、装片胶。
具体实施方式
为了使本实用新型的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本实用新型进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本实用新型，并不用于限定本实用新型。
作为本实用新型所述嵌入式芯片封装结构的实施例，如图2和图3所示，包括芯片1、基岛2、引脚3、引线4和塑封体5，所述芯片1通过装片胶6固定在基岛2上，所述引线4用于实现芯片1和引脚3之间的电连接，塑封体5用于包裹和保护芯片1、基岛2、引脚3和引线4，所述基岛2上表面设有凹槽21，所述芯片1背面通过去材料的方式形成凸块11，所述凸块11嵌入所述凹槽21内，所述装片胶6嵌入基岛2上的凹槽21内，并包裹芯片1上的凸块11。
通过蚀刻或激光切除的方式在引线框架的基岛2上制作出凹槽21；在整片的晶圆背面刻划掉一部分材料，形成凸块11，然后加工切割道，最后分裂成单个的芯片1，这样每个芯片1背面都被刻划出凸块11来，在引线框架的基岛2上涂覆好装片胶6，放上芯片1，凹槽21和凸块11的位置要精准对位，此时装片胶6会嵌入基岛2上的凹槽21内，芯片1的凸块11也会嵌入基岛2的凹槽21内，装片胶6还会包裹凸块11，然后进行烘干，再进行后序的键合、塑封、电镀、切割及测试作业。由于装片胶6嵌入基岛2上的凹槽21内，芯片1的凸块11也会嵌入基岛2的凹槽21内，装片胶6还会包裹凸块11，在原有工艺和参数不变的情况下，增加了装片胶6与芯片1的接触面积，粘接力会更好，导热能力也会更好，根据电阻公式R＝ρl/S，本设计比常规设计具有更大的接触面积S，更小的距离l，意味着具有更低的基岛寄生电阻，其导电能力也更强；在保证一定的粘接力的条件下，对装片胶6的用量控制更宽容，可以使用稍低精度的设备和较快的涂胶速度，提高生产效率和降低生产成本；另外，由于芯片1相对下沉，与基岛2的下表面(此面为主要散热面)传热距离更近，更容易将芯片工作时产生的热量传递出去，增加导热能力；由于芯片1部分嵌入基岛2内，可实现封装产品厚度进一步减小，对于目前越做越薄的封装结构而言，封装其余工艺标准可以相应放宽，降低封装难度。
所述装片胶6也可以扩展为DAF膜。
在本实施例中，所述凹槽21的深度数值大于或等于芯片1上凸块11的高度数值。这样可以保证芯片1底部都能接触到装片胶6，不至于把装片胶6全部挤走。当然所述凹槽21的深度数值小于芯片1上凸块11的高度数值，也是可以的。
在本实用新型中，所述基岛2上凹槽21的深度优选值为基岛基材厚度的1/4-3/4。
在本实用新型中，所述芯片1上凸块11的高度优选值为芯片基材厚度的1/4-3/4。
在本实施例中，所述凹槽21形状为直条形，多条并排设置，所述凸块11与凹槽21形状相适配。此处的适配是指存在装片胶的情况下，凸块要能够轻松地嵌入凹槽内，所以凹槽的尺寸应稍大于凸块的尺寸。凹槽21和凸块11的尺寸和数量均可依据芯片1和基岛2的大小和实际需求进行合理安排。根据本申请人的实验数据，所述凹槽21的宽度优选值为10-2000μm，深度优选值为5-300μm。
在本实用新型中，所述凹槽21和凸块11可以为如图4所示的圆形，如图5所示的环形，如图6所示的斜条形。总之，对凹槽21和凸块11的具体形状和数量不做过多限制，可以为直条形、交错的直条形、曲线条形、圆形、环形或以上图形的组合，均能实现相同的发明目的。
在本实施例中，所述封装结构可以为DFN封装结构、QFN封装结构、ESOP封装结构、ECPC封装结构或EMSOP封装结构，基岛底面露出，导热效果更好。
以上所述仅为本实用新型的较佳实施例而已，并不用以限制本实用新型，凡在本实用新型的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本实用新型的保护范围之内。

Claims (7)

1.一种嵌入式芯片封装结构，包括芯片、基岛、引脚、引线和塑封体，所述芯片通过装片胶固定在基岛上，所述引线用于实现芯片和引脚之间的电连接，塑封体用于包裹和保护芯片、基岛、引脚和引线，其特征在于，所述基岛上表面设有凹槽，所述芯片背面通过去材料的方式形成凸块，所述凸块嵌入所述凹槽内，所述装片胶嵌入基岛上的凹槽内，并包裹芯片上的凸块。
2.根据权利要求1所述的嵌入式芯片封装结构，其特征在于，所述基岛上凹槽的深度为基岛基材厚度的1/4-3/4。
3.根据权利要求1所述的嵌入式芯片封装结构，其特征在于，所述芯片上凸块的高度为芯片基材厚度的1/4-3/4。
4.根据权利要求1所述的嵌入式芯片封装结构，其特征在于，所述凹槽的深度数值大于或等于芯片上凸块的高度数值。
5.根据权利要求1所述的嵌入式芯片封装结构，其特征在于，所述凹槽形状为直条形、交错的直条形、曲线条形、圆形、环形或以上图形的组合，所述凸块与凹槽形状相适配。
6.根据权利要求5所述的嵌入式芯片封装结构，其特征在于，所述凹槽的宽度为10-2000μm，深度为5-300μm。
7.根据权利要求1所述的嵌入式芯片封装结构，其特征在于，所述封装结构为DFN封装结构、QFN封装结构、ESOP封装结构、ECPC封装结构或EMSOP封装结构。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117855165A (zh) * 2024-03-08 2024-04-09 广东气派科技有限公司 低热阻的双面金属散热to247结构及制备方法

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