CN212517181U

CN212517181U - In-line MOS field effect transistor

Info

Publication number: CN212517181U
Application number: CN202021728319.3U
Authority: CN
Inventors: 张开航; 马云洋
Original assignee: Suzhou Qinlv Electronic Technology Co ltd
Current assignee: Suzhou Qinlv Electronic Technology Co ltd
Priority date: 2020-08-18
Filing date: 2020-08-18
Publication date: 2021-02-09
Anticipated expiration: 2030-08-18

Abstract

The utility model discloses an in-line arrangement MOS field effect transistor, include: the MOSFET chip, the ceramic heat conduction body, the source pin, the drain pin and the grid pin are positioned in the epoxy packaging body; a first strip-shaped groove, a second strip-shaped groove and a third groove are formed in one surface of the ceramic heat conduction body, and a first conductive strip, a second conductive strip and a conductive block are respectively filled in the first strip-shaped groove, the second strip-shaped groove and the third groove; the MOSFET chip is provided with a source region, a drain region and a gate region, the MOSFET chip is arranged on the ceramic heat conduction body, and the source region, the drain region and the gate region are respectively and electrically connected with the first conductive strip, one end of the conductive block and the second conductive strip. The utility model discloses the thermal resistance of power MOS has been reduced to be favorable to further improving the power of device, full play power MOS is high-power, the advantage of low-power consumption.

Description

In-line MOS field effect transistor

Technical Field

The utility model relates to a semiconductor device technical field especially relates to an in-line arrangement MOS field effect transistor.

Background

A metal-oxide semiconductor field effect transistor, referred to as a mosfet for short, is a field effect transistor that can be widely used in analog circuits and digital circuits. MOSFETs are classified into two types, an "N type" and a "P type", according to their "channel" polarities. The field effect transistor has higher working temperature and poor heat dissipation effect.

Disclosure of Invention

The utility model aims at providing an in-line arrangement MOS field effect transistor, this in-line arrangement MOS field effect transistor have reduced power MOS's thermal resistance to be favorable to further improving the power of device, full play power MOS is high-power, the advantage of low-power consumption.

In order to achieve the above purpose, the utility model adopts the technical scheme that: an in-line MOS field effect transistor comprising: the MOSFET chip, the ceramic heat-conducting body, the source pin, the drain pin and the grid pin are positioned in the epoxy packaging body, and the source pin, the drain pin and the grid pin extend out of the epoxy packaging body;

a first strip-shaped groove, a second strip-shaped groove and a third groove are formed in one surface of the ceramic heat conduction body, and a first conductive strip, a second conductive strip and a conductive block are respectively filled in the first strip-shaped groove, the second strip-shaped groove and the third groove;

the MOSFET chip is provided with a source region, a drain region and a gate region, the MOSFET chip is arranged on the ceramic heat conduction body, and the source region, the drain region and the gate region are respectively and electrically connected with the first conductive strip, one end of the conductive block and the second conductive strip;

the source electrode pin is electrically connected with the first conductive strip, the drain electrode pin is electrically connected with the other end of the conductive block, and the grid electrode pin is electrically connected with the second conductive strip.

The further improved scheme in the technical scheme is as follows:

1. in the above scheme, the drain pin is located between the source pin and the gate pin.

2. In the scheme, the drain region on the back surface of the MOSFET chip is electrically connected with one end of the conductive block.

3. In the above scheme, the MOSFET chip is located between the first conductive strip and the second conductive strip.

4. In the above scheme, the first conductive strips and the second conductive strips are arranged in parallel.

Because of above-mentioned technical scheme's application, compared with the prior art, the utility model have the following advantage:

1. the utility model discloses in-line arrangement MOS field effect transistor, its MOSFET chip mounting are on ceramic heat conduction body, and this source electrode region, drain electrode region and gate region are connected with first busbar, conducting block one end and second busbar electricity respectively, have reduced power MOS's thermal resistance to be favorable to further improving the power of device, full play power MOS is high-power, the advantage of low-power consumption.

2. The utility model discloses in-line arrangement MOS field effect transistor, open on its pottery heat conduction body surface has first bar groove, second bar groove and third recess, and it has first busbar, second busbar and conducting block to fill respectively in this first bar groove, second bar groove and the third recess, and the source electrode pin is connected with first busbar electricity, and the drain electrode pin is connected with the conducting block other end electricity, the grid electrode pin is connected with second busbar electricity, and existing volume that is favorable to further reducing the device also reduces the figure of part in the device, because radiating area and body are a whole simultaneously, have improved device overall structure stability.

Drawings

Fig. 1 is a schematic structural diagram of an in-line MOS field effect transistor according to the present invention.

In the above drawings: 1. an epoxy package; 2. a MOSFET chip; 21. a source region; 22. a drain region; 23. a gate region; 3. a ceramic thermally conductive body; 31. a first bar-shaped groove; 32. a second strip-shaped groove; 33. a third groove; 4. a source pin; 5. a drain pin; 6. a gate pin; 71. a first conductive strip; 72. a second conductive strip; 73. a conductive block; 8. a conductive wire.

Detailed Description

Example 1: an in-line MOS field effect transistor comprising: the semiconductor device comprises a MOSFET chip 2, a ceramic heat-conducting body 3, a source pin 4, a drain pin 5 and a grid pin 6 which are positioned in an epoxy packaging body 1, wherein the source pin 4, the drain pin 5 and the grid pin 6 extend outwards from the epoxy packaging body 1;

a first strip-shaped groove 31, a second strip-shaped groove 32 and a third groove 33 are formed in one surface of the ceramic heat conducting body 3, and a first conductive strip 71, a second conductive strip 72 and a conductive block 73 are respectively filled in the first strip-shaped groove 31, the second strip-shaped groove 32 and the third groove 33;

the MOSFET chip 2 is provided with a source region 21, a drain region 22 and a gate region 23, the MOSFET chip 2 is mounted on the ceramic heat conducting body, and the source region 21, the drain region 22 and the gate region 23 are electrically connected with the first conductive strip 71, one end of the conductive block 73 and the second conductive strip 72 respectively;

source pin 4 is electrically connected to first conductive strip 71, drain pin 5 is electrically connected to the other end of conductive block 73, and gate pin 6 is electrically connected to second conductive strip 72.

The drain pin 5 is located between the source pin 4 and the gate pin 6.

The drain region 22 on the back side of the MOSFET chip 2 is electrically connected to one end of the conductive bump 73.

The MOSFET chip 2 is located between the first conductive strip 71 and the second conductive strip 72.

Example 2: an in-line MOS field effect transistor comprising: the semiconductor device comprises a MOSFET chip 2, a ceramic heat-conducting body 3, a source pin 4, a drain pin 5 and a grid pin 6 which are positioned in an epoxy packaging body 1, wherein the source pin 4, the drain pin 5 and the grid pin 6 extend outwards from the epoxy packaging body 1;

The first conductive strips 71 and the second conductive strips 72 are arranged in parallel.

When the in-line type MOS field effect transistor is adopted, the MOSFET chip is arranged on the ceramic heat conduction body, and the source region, the drain region and the gate region are respectively and electrically connected with the first conductive strip, one end of the conductive block and the second conductive strip, so that the thermal resistance of the power MOS is reduced, the power of the device is further improved, and the advantages of high power and low power consumption of the power MOS are fully exerted; and a first strip-shaped groove, a second strip-shaped groove and a third groove are formed in one surface of the ceramic heat conduction body, a first conductive strip, a second conductive strip and a conductive block are respectively filled in the first strip-shaped groove, the second strip-shaped groove and the third groove, a source electrode pin is electrically connected with the first conductive strip, a drain electrode pin is electrically connected with the other end of the conductive block, and a grid electrode pin is electrically connected with the second conductive strip, so that the size of the device is further reduced, the number of parts in the device is also reduced, and meanwhile, the whole structure stability of the device is improved as the heat dissipation area and the body are integrated.

The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.

Claims

1. An in-line MOS field effect transistor, characterized by: the method comprises the following steps: the MOSFET chip (2), the ceramic heat-conducting body (3), the source pin (4), the drain pin (5) and the grid pin (6) are positioned in the epoxy packaging body (1), and the source pin (4), the drain pin (5) and the grid pin (6) extend outwards from the epoxy packaging body (1);

a first strip-shaped groove (31), a second strip-shaped groove (32) and a third groove (33) are formed in one surface of the ceramic heat conduction body (3), and a first conductive strip (71), a second conductive strip (72) and a conductive block (73) are respectively filled in the first strip-shaped groove (31), the second strip-shaped groove (32) and the third groove (33);

the MOSFET chip (2) is provided with a source region (21), a drain region (22) and a gate region (23), the MOSFET chip (2) is mounted on the ceramic heat conduction body, and the source region (21), the drain region (22) and the gate region (23) are electrically connected with the first conductive strip (71), one end of the conductive block (73) and the second conductive strip (72) respectively;

the source pin (4) is electrically connected with the first conductive strip (71), the drain pin (5) is electrically connected with the other end of the conductive block (73), and the gate pin (6) is electrically connected with the second conductive strip (72).

2. The in-line MOS field effect transistor of claim 1, wherein: the drain pin (5) is located between the source pin (4) and the gate pin (6).

3. The in-line MOS field effect transistor of claim 1, wherein: the drain region (22) on the back of the MOSFET chip (2) is electrically connected with one end of the conductive block (73).

4. The in-line MOS field effect transistor of claim 1, wherein: the MOSFET chip (2) is located between the first conductive strip (71) and the second conductive strip (72).

5. The in-line MOS field effect transistor of claim 1, wherein: the first conductive strips (71) and the second conductive strips (72) are arranged in parallel.