CN108039366A - A kind of insulated gate bipolar transistor transoid MOS transition plot structures and preparation method thereof - Google Patents
A kind of insulated gate bipolar transistor transoid MOS transition plot structures and preparation method thereof Download PDFInfo
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- CN108039366A CN108039366A CN201711003536.9A CN201711003536A CN108039366A CN 108039366 A CN108039366 A CN 108039366A CN 201711003536 A CN201711003536 A CN 201711003536A CN 108039366 A CN108039366 A CN 108039366A
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- 230000007704 transition Effects 0.000 title claims abstract description 41
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 230000001413 cellular effect Effects 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 claims description 2
- 230000003446 memory effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of insulated gate bipolar transistor transoid MOS transition plot structures and preparation method thereof.The structure includes substrate, the cellular doped region for being arranged on substrate top surface, integrated transoid MOS doped regions, dielectric layer, the electrode metal to match with structure cell and the grid structure for isolating gate electrode.A kind of integrated transoid MOS high turn-off capacities insulated gate bipolar transistor (IGBT) provided by the invention can improve few sub- Extracting Ability during the shut-off of device active region, and then improve the turn-off capacity of chip on the premise of other characteristics are not influenced.
Description
Technical field
The present invention relates to a kind of insulated gate bipolar transistor, and in particular to a kind of insulated gate bipolar transistor transoid
MOS transition plot structures and preparation method thereof.
Background technology
Power semiconductor chip (such as IGBT, MOSFET, MCT) is made of active area and termination environment, and active area is chip
Main flow area, be looped around to reduce the pressure-resistance structure termination environment designed of semiconductor chip surface electric field outside active area
Enclose.Active area and the transitional region in terminal section, one week around chip is grid busbar, for grid pad signal is uniformly passed
It is sent at each cellular.
By taking IGBT common at present as an example, (Insulated Gate Bipolar Transistor, insulated gate are double by IGBT
Bipolar transistor) device structure and MOSFET (metallic oxide semiconductor field
Effecttransistor mos field effect transistor) structure it is quite similar, both Main Differences are
IGBT instead of the N+ cushions of MOSFET with P+ substrates, and a PN junction is created between P+ and N- areas.Share three poles：Grid
G, emitter E and collector C.IGBT device is voltage wholly-controled device, except with low-power consumption, high-frequency, high voltage, big electricity
Outside the advantages that stream, the drive circuit that it is needed is simple with control circuit, and driving power consumption is low, is considered as Power Electronic Technique the by people
The mainstream product of revolution three times, is electric energy intelligent management and the core devices of energy-saving and emission-reduction.
With sustained and rapid development of economy, energy crisis is on the rise, and existing contradiction is increasingly prominent between supply and demand, hair
Open up Energy Saving Industry and New Energy Industry is imperative.Important role is play in energy saving aspect power electronic devices, is both machine
Tool automation, the critical component of intelligent control, and save the semiconductor devices of electric energy.Therefore, power electronics is greatly developed
The design and manufacture of device and the development and application of module are to save the important measures of electric energy.Represented as power electronic devices
IGBT is to improve machine system performance indicator and the preferred product of energy-saving index.
In the prior art, substrate top surface transition plot structure is usually doping and undoped two types, that is, is equivalent to one
Root conducting wire or insulation resistance, without on-off function.There is few sub- Extracting Ability, during conducting during the wire type shut-off of doping
Similarly extract, reduce few sub memory action, increase the pressure drop of device；Undoped insulation resistance type has certain
Few sub- memory action, but turn off when, few sub- extraction heavy load of transition region, easily lead to device shut-off failure.
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art, and by taking IGBT as an example, the present invention proposes a kind of transoid MOS
Transition plot structure, can have few sub- memory action when conducting, meanwhile, grid turn off when adding negative pressure, there is provided few son release
Extra path, improve turn-off capacity.
In order to achieve the above object, the present invention provides following technical proposals：
A kind of insulated gate bipolar transistor transoid MOS transition plot structures, including：
Cellular doped region 102 and 103, busbar 106, the terminal doped region that substrate 101 and 101 upper surface of substrate are set
107 and termination field plate 108；101 lower surface of substrate is provided with back side doped region 104 and back metal electrode 109；
The upper surface of cellular doped region 103 is provided with front metal electrode 105；Front metal electrode 105 is adulterated with cellular
102 Ohmic contact of area；
Busbar 106 forms MOS structure with 101 transition region upper surface of substrate；
The upper surface of terminal doped region 107 is equipped with termination field plate 108；
Back metal electrode 109 and 104 Ohmic contact of back side doped region.
A kind of first preferred solution of insulated gate bipolar transistor transoid MOS transition plot structures, busbar 106 with it is active
Cellular doped region 102, terminal doped region 107 form transoid MOS structure in area.
A kind of second preferred solution of insulated gate bipolar transistor transoid MOS transition plot structures,
Substrate 101 is N-shaped, and cellular doped region 102 is p-type, and cellular doped region 103 is N-shaped, and back side doped region 104 is p
Type, terminal doped region 107 are p-type.
A kind of 3rd preferred solution of insulated gate bipolar transistor transoid MOS transition plot structures,
Substrate 101 is p-type, and cellular doped region 102 is N-shaped, and cellular doped region 103 is p-type, and back side doped region 104 is n
Type, terminal doped region 107 are N-shaped.
A kind of 4th preferred solution of insulated gate bipolar transistor transoid MOS transition plot structures, the busbar of transition region
106 be polysilicon or metal material.
A kind of 5th preferred solution of insulated gate bipolar transistor transoid MOS transition plot structures, transoid MOS structure raceway groove
Length is 1~100um, and 106 length of busbar is 1~500um, and MOS structure insulating layer is thick for 0.01~100um.
A kind of 6th preferred solution of insulated gate bipolar transistor transoid MOS transition plot structures, the transistor are used for
IGBT, MCT and BJT three terminal device based on Si, SiC, GaN semi-conducting material.
A kind of insulated gate bipolar transistor transoid MOS transition region construction manufacturing methods, include the following steps：
(1) cellular doped region 102 and 103 and termination environment doping 107 are formed in the upper surface of substrate 101；
(2) gate oxygen structure is formed in the upper surface of 101 active area of substrate；
(3) busbar 106 is formed in grid oxygen；
(4) upper surface front metal electrode 105 and termination environment field plate 108 are formed in cellular doped region 102；
(5) passivation layer structure is formed on busbar 106 and termination field plate 108；
(6) back side doped region 104 and back metal electrode 109 are formed in 101 lower surface of substrate.
Compared with the immediate prior art, technical solution provided by the invention has following excellent effect：
1st, a kind of IGBT transoids MOS transition region structure designs provided by the invention and preparation method thereof so that IGBT is being led
There is few sub- memory action when logical, meanwhile, during shut-off, by taking n-IGBT as an example, grid turn off when adding negative pressure, there is provided few son release
Extra path, improve turn-off capacity；
2nd, a kind of IGBT transoids MOS transition region structure designs provided by the invention and preparation method thereof, can not increase
On the premise of processing step, the making of transoid MOS transition plot structures is completed, i.e., does not increase additional technical steps and cost.
Brief description of the drawings
Fig. 1：IGBT transoids MOS transition region structure diagrams in the present invention；
Wherein, 101 substrate；102nd, 103 cellular doped region；104 back side doped regions；105 front metal electrodes；106 confluences
Bar；107 terminal doped regions；108 termination field plates；109 back metal electrodes.
Embodiment
Below in conjunction with the accompanying drawings 1 and specific embodiment be described in further detail, technical scheme is carried out it is clear,
It is fully described by, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment, belongs to the scope of protection of the invention.
A kind of transoid MOS transition plot structures provided in an embodiment of the present invention are illustrated below.
Fig. 1 is that the chip of transoid MOS transition plot structures in the embodiment of the present invention throws face schematic diagram, as shown in the figure, insulated gate
Bipolar transistor transoid MOS transition plot structures include：
Substrate 101；
Cellular doped region 102, it is arranged on the upper surface of the substrate 101；
Cellular doped region 103, it is arranged on the upper surface of the substrate 101；
Back side doped region 104, it is arranged on the lower surface of the substrate 101；
Front metal electrode 105, it is arranged on the upper surface of the cellular doped region 103, with 103 ohm of cellular doped region
Contact；
The busbar 106 of positive transition region, it is arranged on the upper surface of the substrate 101, with 101 transition region upper table of substrate
Face forms MOS structure；
Terminal doped region 107, it is arranged on the upper surface of 101 termination environment of substrate；
Termination field plate 108, it (can also be other types of field plate that it, which is arranged on the upper surface of the terminal doped region 107,
Structure)；
Back metal electrode 109, it is arranged on the lower surface of the substrate, with 104 Ohmic contact of back side doped region.
Further, transoid MOS transition plot structure can use following structures in the present embodiment.
The busbar 106 of transition region forms transoid MOS structure with the cellular doped region 102 of active area, terminal doped region 107
(opposite with cellular region MOS types).
When gate electrode applies positive signal (cellular conducting), which is not turned on, and has one to few son
Fixed memory action, reduces on-state voltage drop；
When gate electrode applies negative signal (cellular shut-off), transition region transoid MOS structure conducting, forms few electron current and leads to
Road, few sub- release way, improves turn-off capacity when increase turns off；
At gate electrode no signal (cellular shut-off), which has castering action to the voltage endurance capability of termination environment.
Transoid MOS structure channel length in the present embodiment under busbar 106 is between 1-100 microns, busbar length
For degree between 1-500 microns, MOS structure insulating layer (can be with cellular region MOS structure insulating layer between 0.01-100 microns
Formed at the same time).
Transoid MOS transition plot structures are applicable to multiple material, polytype device in the present embodiment, such as based on Si,
The three terminal devices such as IGBT, MCT, BJT of the semi-conducting material development such as SiC, GaN.
Embodiment 1
Substrate 101 is N-shaped, and cellular doped region 102 is p-type, and cellular doped region 103 is N-shaped, and back side doped region 104 is p
Type, terminal doped region 107 are p-type.
Embodiment 2
Substrate 101 is p-type, and cellular doped region 102 is N-shaped, and cellular doped region 103 is p-type, and back side doped region 104 is n
Type, terminal doped region 107 are N-shaped.
A kind of production method of transoid MOS transition regions provided in an embodiment of the present invention is illustrated below.
Transoid MOS transition regions can be prepared in the present embodiment as steps described below, are specially：
1st, active area and termination environment doping are formed in the upper surface of substrate；
2nd, gate oxygen structure is formed in the upper surface of substrate active area；
3rd, polysilicon busbar or metal bus bars structure are formed in grid oxygen；
4th, upper surface electrode structure and termination environment field plate structure are formed in cellular doped region；
5th, passivation layer structure is formed on busbar and termination field plate；
6th, back side doped region and back metal electrode are formed in substrate lower surface.
The above embodiments are merely illustrative of the technical solutions of the present invention rather than is limited, the common skill of fields
Art personnel should be appreciated that with reference to above-described embodiment can to the present invention embodiment technical scheme is modified or replaced equivalently,
These are applying for pending claim protection model without departing from any modification of spirit and scope of the invention or equivalent substitution
Within enclosing.
Claims (8)
1. a kind of insulated gate bipolar transistor transoid MOS transition plot structures, it is characterised in that the structure includes：
Substrate (101) and the cellular doped region (102,103) of the substrate (101) upper surface setting, busbar (106), terminal
Doped region (107) and termination field plate (108)；Substrate (101) lower surface is provided with back side doped region (104) and back metal
Electrode (109)；
The upper surface of the cellular doped region (103) is provided with front metal electrode (105)；The front metal electrode (105)
With cellular doped region (102) Ohmic contact；
The busbar (106) forms MOS structure with the substrate (101) transition region upper surface；
The upper surface of the terminal doped region (107) is equipped with termination field plate (108)；
The back metal electrode (109) and back side doped region (104) Ohmic contact.
A kind of 2. insulated gate bipolar transistor transoid MOS transition plot structures as claimed in claim 1, it is characterised in that institute
State busbar (106) and form transoid MOS structure with cellular doped region (102) described in active area, terminal doped region (107).
A kind of 3. insulated gate bipolar transistor transoid MOS transition plot structures as claimed in claim 1, it is characterised in that
The substrate (101) is N-shaped, and the cellular doped region (102) is p-type, and the cellular doped region (103) is N-shaped, described
Back side doped region (104) is p-type, and the terminal doped region (107) is p-type.
A kind of 4. insulated gate bipolar transistor transoid MOS transition plot structures as claimed in claim 1, it is characterised in that
The substrate (101) is p-type, and the cellular doped region (102) is N-shaped, and the cellular doped region (103) is p-type, described
Back side doped region (104) is N-shaped, and the terminal doped region (107) is N-shaped.
A kind of 5. insulated gate bipolar transistor transoid MOS transition plot structures as claimed in claim 1, it is characterised in that mistake
The busbar (106) for crossing area is polysilicon or metal material.
A kind of 6. insulated gate bipolar transistor transoid MOS transition plot structures as claimed in claim 2, it is characterised in that institute
It is 1~100um to state transoid MOS structure channel length, and busbar (106) length is 1~500um, and MOS structure insulating layer is
0.01~100um is thick.
A kind of 7. insulated gate bipolar transistor transoid MOS transition plot structures as claimed in claim 1, it is characterised in that
The transistor is used for IGBT, MCT and BJT three terminal device based on Si, SiC, GaN semi-conducting material.
8. a kind of insulated gate bipolar transistor transoid MOS transition region construction manufacturing methods as claimed in claim 1, its feature
It is, described method includes following steps：
(1) cellular doped region (102,103) and termination environment doping (107) are formed in the upper surface of substrate (101)；
(2) gate oxygen structure is formed in the upper surface of substrate (101) active area；
(3) busbar (106) is formed in grid oxygen；
(4) upper surface front metal electrode (105) and termination environment field plate (108) are formed in cellular doped region (102)；
(5) passivation layer structure is formed on the busbar (106) and termination field plate (108)；
(6) back side doped region (104) and back metal electrode (109) are formed in the substrate (101) lower surface.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711003536.9A CN108039366A (en) | 2017-10-24 | 2017-10-24 | A kind of insulated gate bipolar transistor transoid MOS transition plot structures and preparation method thereof |
| PCT/CN2018/101196 WO2019080618A1 (en) | 2017-10-24 | 2018-08-17 | Insulated gate bipolar transistor structure and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711003536.9A CN108039366A (en) | 2017-10-24 | 2017-10-24 | A kind of insulated gate bipolar transistor transoid MOS transition plot structures and preparation method thereof |
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| CN108039366A true CN108039366A (en) | 2018-05-15 |
Family
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| CN201711003536.9A Pending CN108039366A (en) | 2017-10-24 | 2017-10-24 | A kind of insulated gate bipolar transistor transoid MOS transition plot structures and preparation method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109671771A (en) * | 2018-11-19 | 2019-04-23 | 全球能源互联网研究院有限公司 | Backside structure, igbt chip structure and the preparation method of igbt chip |
| WO2019080618A1 (en) * | 2017-10-24 | 2019-05-02 | 全球能源互联网研究院有限公司 | Insulated gate bipolar transistor structure and manufacturing method therefor |
| WO2023045386A1 (en) * | 2021-09-22 | 2023-03-30 | 上海积塔半导体有限公司 | Igbt device and manufacturing method therefor |
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|---|---|---|---|---|
| US20120037954A1 (en) * | 2010-08-10 | 2012-02-16 | Force Mos Technology Co Ltd | Equal Potential Ring Structures of Power Semiconductor with Trenched Contact |
| CN103839993A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Latch-up prevention termination region for insulated gate bipolar transistors |
| CN104282741A (en) * | 2013-07-05 | 2015-01-14 | 无锡华润上华半导体有限公司 | Field stop type reverse conducting insulated gate bipolar transistor (FS type RC-IGBT) and manufacturing method thereof |
| CN104882474A (en) * | 2014-02-27 | 2015-09-02 | 株式会社东芝 | Semiconductor device |
-
2017
- 2017-10-24 CN CN201711003536.9A patent/CN108039366A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120037954A1 (en) * | 2010-08-10 | 2012-02-16 | Force Mos Technology Co Ltd | Equal Potential Ring Structures of Power Semiconductor with Trenched Contact |
| CN103839993A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Latch-up prevention termination region for insulated gate bipolar transistors |
| CN104282741A (en) * | 2013-07-05 | 2015-01-14 | 无锡华润上华半导体有限公司 | Field stop type reverse conducting insulated gate bipolar transistor (FS type RC-IGBT) and manufacturing method thereof |
| CN104882474A (en) * | 2014-02-27 | 2015-09-02 | 株式会社东芝 | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019080618A1 (en) * | 2017-10-24 | 2019-05-02 | 全球能源互联网研究院有限公司 | Insulated gate bipolar transistor structure and manufacturing method therefor |
| CN109671771A (en) * | 2018-11-19 | 2019-04-23 | 全球能源互联网研究院有限公司 | Backside structure, igbt chip structure and the preparation method of igbt chip |
| CN109671771B (en) * | 2018-11-19 | 2022-04-01 | 全球能源互联网研究院有限公司 | Back structure of IGBT chip, IGBT chip structure and preparation method |
| WO2023045386A1 (en) * | 2021-09-22 | 2023-03-30 | 上海积塔半导体有限公司 | Igbt device and manufacturing method therefor |
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Application publication date: 20180515 |