CN207199624U - A kind of compound groove MOS device - Google Patents
A kind of compound groove MOS device Download PDFInfo
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- CN207199624U CN207199624U CN201720851556.0U CN201720851556U CN207199624U CN 207199624 U CN207199624 U CN 207199624U CN 201720851556 U CN201720851556 U CN 201720851556U CN 207199624 U CN207199624 U CN 207199624U
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Abstract
The utility model belongs to semiconductor power device technology field, specifically related to a kind of compound groove MOS device, the utility model is by Schottky diode structure and TMBS structure assemblies in the contact hole of each groove MOSFET unit cell, Schottky contacts are formed in the contact hole side wall of MOSFET unit cells, reduce switching loss and suppress peak voltage and peak current, improve reverse recovery characteristic；And TMBS structures are formed in the bottom of contact hole, equilibrium electric field can be formed in device inside, lift breakdown characteristic of device, it is effective to save silicon face area while improving device performance so as to reach, reduce chip cost；The utility model manufacturing process is simple, and cost is low, and structure is novel, and properties of product and reliability are high, and can effectively suppress the peak voltage and peak current and to improve device pressure-resistant of groove MOSFET device Reverse recovery.
Description
Technical field
It the utility model is related to semiconductor power device technology field, and in particular to a kind of compound groove MOS device knot
Structure.
Background technology
With the fast development of China's economy continuously and healthily, energy resource consumption also increases year by year, particularly in global warming
Under overall background, " low-carbon economy " is increasingly becoming global focus, therefore saves the energy as one of the fundamental state policy in China.It is and new
The type power electronic devices especially important role of performer wherein, wherein groove MOS device be as nowadays quickly grow, city
The good semiconductor devices of field prospect, it has the advantages that, and switching speed is fast, input impedance is high, heat endurance is good, highly reliable,
Computer, communication apparatus, the power supply circuit of normal office equipment and electrical automotive circuits field have a wide range of applications.
One peculiar part of most of power MOSFET devices is the drain-source diode-built-in with one " parasitism ".
In many application scenarios, drain-source diode-built-in is not at reverse-biased, therefore has no effect on the work of circuit.But with
The raising of microprocessor clock frequencies in the last few years, it would be desirable to low-voltage, high current and high current Slew Rate (di/dt>
Voltage modulated module (VRM) 150A), generally for DC-DC converter, working frequency needs to bring up to 1MHZ even more highs.
To meet this requirement, it is highly effective to reduce the QRR Qrr of groove MOS device, and can prevent to turn on
When power consumption penalty and from open.In order to realize this purpose, one of which way is exactly the source S in groove MOSFET device
The Schottky diode SBD in parallel between drain D, its development mainly experienced following course：
First stage is that the groove MOSFET of the Schottky diode of individual packages and individual packages is installed in parallel in electricity
On the plate of road.Shortcoming is cost height, takes circuit board more many areas and because longer cabling introduces the influence of stray inductance, brings
Excess loss and EMC and EMI problems.
Second stage is encapsulated in independent Schottky chip is in parallel with independent groove MOSFET chip same half and led
It is that groove MOSFET chip and Schottky chip realize parallel connection by routing in the encapsulation of body device.Shortcoming is still cost height, and
And high is required to encapsulation, and entire area is big after encapsulation.
Phase III is to design and produce groove MOSFET and Schottky diode in same chip, in processing ditch
All it is to add the scheme distinguished and made using zoning design in the mode of groove MOSFET and Schottky diode, and is realized by routing
Interconnection, still occupies substantial amounts of chip area and cost.Therefore the shortcomings that existing is always：1st, Schottky diode structure takes
A large amount of silicon face areas, cause chip area big, and cost is high；2nd, complex process, manufacturing cost height is caused.
Utility model content
In view of this, main purpose of the present utility model is to provide a kind of compound groove MOS device structure.
The utility model embodiment provides a kind of compound groove MOS device, and the device includes the first conductivity type drain
Area, the N+ monocrystalline substrates above the first conductivity type drain area and N- epitaxial layers, on the N- epitaxial layers
The first conduction type P type trap zone layer, the second conduction type source electrode above the first conduction type P type trap zone layer of side
Region layer, the insulating medium layer above the second conduction type source electrode region layer and above the insulating medium layer
Source metal region layer, in addition to：
Groove, it passes through the first conduction type P type trap zone layer, extends to the inside of the N- epitaxial layers；
Gate oxide, itself and the trench contact；
Polysilicon layer, it is contacted with gate oxide, and top contacts with the insulating medium layer；
Contact hole, the contact hole pass through the insulating medium layer and the first conduction type P type trap zone layer, extended to
The N- epitaxial layers, the contact hole is interior to be filled with metal, and the top of the metal connects the metal region layer；
Contact hole bottom oxidization layer, it is located at the contact hole bottom, with the N- epitaxial layers；
Contact hole bottom polycrystal layer, it is contacted with the contact hole bottom oxidization layer, forms TMBS structures；
Contact metal layer, the contact metal layer bottom contact with contact hole bottom polycrystal layer, the contacting metal
Layer top contacts with the source metal region layer, and the contact metal layer includes schottky contact layer and ohmic contact layer, described
Schottky contact layer is that the contact metal layer contacts in the side wall of source contact openings with the N- epitaxial layers, the Ohmic contact
Layer is that the contact metal layer connects in the side wall of source contact openings with the N+ source electrodes and the first conduction type P type trap zone layer
Touch；
Wherein, the source metal region layer is the anode metal electrodes of metal-oxide-semiconductor source metal electrode, i.e. Schottky, described
First conductivity type drain area is the cathodic metal electrode of metal-oxide-semiconductor drain metal electrode, i.e. Schottky.
In such scheme, the schottky contact layer includes tungsten articulamentum, titanium nitride barrier layer and Titanium and bonded
Layer, the tungsten articulamentum contact with the bottom of the source metal electrode layer, the titanium nitride barrier layer and the metal
The side end in contact of tungsten articulamentum, the side end in contact of the Titanium tack coat and the titanium nitride barrier layer, the metal
Titanium tack coat forms Schottky contacts in the lateral ends of the contact hole with the N- epitaxial layers.
In such scheme, ohmic contact layer described in the ohmic contact layer is located at the side-walls of the contact hole, the gold
Belong to titanium tack coat and the second conduction type source electrode region layer forms N+ source electrode Ohmic contacts；The Titanium tack coat and P+ contact zones
Form the Ohmic contact of p-type trap.
In such scheme, the contact hole bottom oxidization layer is connected with the N- epitaxial layers, contact hole bottom polycrystalline
Layer bottom is connected with the contact hole bottom oxidization layer, and top contacts with the bottom of source metal electrode layer, ultimately forms
TMBS structures.
In such scheme, contact hole bottom polycrystal layer is the polysilicon of N-type heavy doping.
Compared with prior art, the beneficial effects of the utility model：
1st, a kind of compound groove MOS device provided by the utility model, its contact hole side wall in each unit cell source electrode
Integrated TMBS structures, reach the purpose of balancing device internal electric field, effectively lift the breakdown characteristics of device, increase the resistance to of device
Pressure.
2nd, a kind of compound groove MOS device provided by the utility model, its contact hole side wall in each unit cell source electrode
Integrated schottky diode structure, it effectively and substantially reduces switching loss, suppresses peak voltage and peak current.
3rd, a kind of compound groove MOS device provided by the utility model, TMBS structures are integrated in the bottom of contact hole, and
The contact metal layer of Schottky diode is located at contact hole side wall.So that device not only possesses TMBS structures and Schottky diode
Advantage, and effectively save silicon face area, reduce the cost of device.
4th, a kind of compound groove MOS device provided by the utility model, its structure is novel, and properties of product are high.
Brief description of the drawings
Fig. 1 is structural profile illustration of the present utility model.
In Fig. 1,1 is N+ monocrystalline substrates；2 be N- epitaxial layers；3 be the first conduction type P type trap zone layer；4 lead for second
Electric type source area layer；5 be groove；6 be gate oxide；7 be polysilicon layer；8 be contact hole；9 be contact hole bottom oxidization layer；
10 be contact hole bottom polysilicon layer；11 be schottky contact layer；12 be ohmic contact layer；13 be dielectric oxide layer；14
For source region metal electrode layer；15 be back side drain region metal electrode layer.
Fig. 2~11 are processing step schematic diagrames of the present utility model.
Embodiment
In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation
Example, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only explaining
The utility model, it is not used to limit the utility model.
The utility model embodiment provides a kind of compound groove MOS device, as shown in figure 1, the device is led including first
Electric type drain area, the N+ monocrystalline substrates 1 above the first conductivity type drain area and N- epitaxial layers 2, positioned at institute
State the first conduction type P type trap zone layer 3 of the top of N- epitaxial layers 2, above the first conduction type P type trap zone layer 3
Second conduction type source electrode region layer 4, the insulating medium layer 13 above the second conduction type source electrode region layer 4 and it is located at
The source metal region layer 14 of the top of insulating medium layer 13, in addition to：
Groove 5, it passes through the first conduction type P type trap zone layer 3, extends to the inside of the N- epitaxial layers 2；
Gate oxide 6, it is contacted with the groove 5；
Polysilicon layer 7, it is contacted with gate oxide 6, and top contacts with the insulating medium layer；
Contact hole 8, the contact hole 8 pass through the insulating medium layer and the first conduction type P type trap zone layer 3, prolonged
The N- epitaxial layers 2 are extended, metal is filled with the contact hole 8, the top of the metal connects the metal region layer；
Contact hole bottom oxidization layer 9, it is located at the bottom of contact hole 8, with the N- epitaxial layers 2；
Contact hole bottom polycrystal layer 10, it is contacted with the contact hole bottom oxidization layer 9, forms TMBS structures；
Contact metal layer, the contact metal layer bottom contact with contact hole bottom polycrystal layer 10, the contact gold
Contacted at the top of category layer with the source metal region layer, the contact metal layer includes schottky contact layer 11 and ohmic contact layer
12, the schottky contact layer 11 is that contact metal layer contacts in the side wall of source contact openings with the N- epitaxial layers 2, the Europe
Nurse contact layer 12 is that contact metal layer contacts in the side wall of source contact openings with the first conduction type P type trap zone layer 3；
Wherein, the source metal region layer is the anode metal electrodes of metal-oxide-semiconductor source metal electrode, i.e. Schottky, described
First conductivity type drain area is the cathodic metal electrode of metal-oxide-semiconductor drain metal electrode, i.e. Schottky.
The schottky contact layer 11 includes tungsten articulamentum, titanium nitride barrier layer and Titanium tack coat, the gold
Category tungsten articulamentum contacts with the bottom of the source metal electrode layer, the titanium nitride barrier layer and the tungsten articulamentum
Side end in contact, the side end in contact of the Titanium tack coat and the titanium nitride barrier layer, the Titanium tack coat exist
The lateral ends of the contact hole 8 form Schottky contacts with the N- epitaxial layers 2.
The ohmic contact layer 12 is located at the side-walls of the contact hole 8, the Titanium tack coat and the second conductive-type
Type source electrode region layer 4 forms N+ source electrode Ohmic contacts；The Titanium tack coat forms the Ohmic contact of p-type trap with P+ contact zones.
The contact hole bottom oxidization layer 9 is connected with the N- epitaxial layers 2, the bottom of contact hole bottom polycrystal layer 10 with
The contact hole bottom oxidization layer 9 connects, and top contacts with the bottom of source metal electrode layer, ultimately forms TMBS structures.
Contact hole bottom polycrystal layer 10 is the polysilicon of N-type heavy doping.Manufacture method of the present utility model, as Fig. 1-
Shown in 11, specific implementation step：
In the N+ monocrystalline substrates 1 of the N-type high-dopant concentration of the first conduction type, the N-type of the conduction type of growth regulation one
The N- epitaxial layers 2 of low doping concentration；
On the surface of N- epitaxial layers 2 after the dielectric layer of growth regulation one, photoetching is carried out to the first medium layer, defines MOS
The trench area figure of pipe unit cell array；
By dry etching, the first medium layer for not being photo-etched glue protection is removed, exposes N- corresponding to the area's figure of groove 5
Epitaxial layer 2, then after removing photoresist, the first medium layer remained is as the first hard mask；
Using the described first hard mask as barrier layer, the surface in N- epitaxial layers 2 forms groove 5, in the He of groove 5
One layer of the surface deposition of N- epitaxial layers 2 is the second dielectric layer of silica, forms gate oxide 6；
Conductive polycrystalline silicon floor 7 is deposited on the gate oxide 6, leading for the top of N- epitaxial layers 2 is removed by dry etching
Electric polysilicon layer 7 and gate oxide 6；
By in p type impurity ion implanting to the N- epitaxial layers 2, then handled by short annealing, in the N- extensions
The first conduction type P type trap zone layer 3 is formed in layer 2；
The second conduction type source electrode region layer 4 is defined in the top of the first conduction type P type trap zone layer 3；
In the dielectric layer of surface deposition the 3rd of the second conduction type source electrode region layer 4, the 3rd dielectric layer is silicon dioxide layer,
The either composite bed of silicon nitride layer or silicon dioxide layer and silicon nitride layer；
The 3rd dielectric layer above the second conduction type source electrode region layer 4 forms insulating medium layer, to as exhausted
3rd dielectric layer of edge dielectric layer implements dry etching, penetrates the insulating medium layer and the first conduction type P type trap zone
Layer 3, the N- epitaxial layers 2 are extended to, form contact hole 8；
Layer of oxide layer and one layer of polysilicon are deposited in the contact hole 8, the contact hole is formed by dry etching
The TMBS structures of bottom oxidization layer 9 and contact hole bottom polycrystal layer 10；
Metal filled, first deposited metal titanium tack coat is carried out to contact hole 8, titanium nitride resistance is deposited on Titanium tack coat
Barrier, followed by depositing tungsten metal layer and aluminum metal layer, close to the first conduction type P of the lateral ends of contact hole 8
P+ contact zones are provided with type well region layer 3, positioned at the Titanium tack coat and titanium nitride barrier layer of the lateral ends of contact hole 8 and
Two conduction type source electrode region layer 4 form N+ source electrode Ohmic contacts, positioned at the Titanium tack coat and nitrogen of the side wall of the contact hole 8
Change the ohmic contact layer 12 that titanium barrier layer forms p-type trap with P+ contact zones；
In the lower-lying metal titanium tack coat of ohmic contact layer 12 and the contacts side surfaces of N- epitaxial layers 2, in the side of contact hole 8
Wall forms Schottky contacts, deposits titanium nitride barrier layer on Titanium tack coat, tungsten is deposited on titanium nitride barrier layer
Articulamentum, Titanium tack coat, titanium nitride barrier layer and tungsten articulamentum form schottky contact layer 11；
Contact metal layer is formed in the side deposition tungsten metal of the ohmic contact layer 12 and schottky contact layer 11；And
The formed below of the contact metal layer is made up of the contact hole bottom oxidization layer 9 and contact hole bottom polycrystal layer
TMBS structures.
In the metal that the upper surface of the insulating medium layer deposits, source metal region layer is formed, the contact hole 8 is by connecing
Touch metal level to be connected with the source metal region layer, form source metal electrode；
Photoetching is implemented to metal region layer, protects source metal electrode region and the MOS of metal-oxide-semiconductor unit cell array area with photoresist
The gate metal electrode region of pipe unit cell array area periphery, that is, define source metal electrode region and gate metal electrode administrative division map
Shape；
Using dry etching method, selective removal is not photo-etched the metal region layer of glue protection, exposes and is situated between as insulation
3rd dielectric layer of matter layer, after removing photoresist, the metal region layer positioned at unit cell array region left forms metal-oxide-semiconductor source electrode gold
Belong to electrode, while be also the anode metal electrodes of Schottky diode, the metal area positioned at unit cell array region periphery left
Layer forms metal-oxide-semiconductor gate metal electrode；
In the bottom surface deposition metal level of N+ monocrystalline substrates 1, drain region is formed, the metal level forms metal-oxide-semiconductor drain metal
Electrode, while be also the cathodic metal electrode of Schottky diode.
The doping type of the polysilicon layer 7 is that n-type doping or p-type are adulterated.
It is described to deposit metal in the upper surface of insulating medium layer, metal region layer is formed, is specially：In the upper of insulating medium layer
Surface deposition tungsten, tungsten fill up contact hole 8, then using dry etching method, selective removal tungsten, make conduct
3rd dielectric layer of insulating medium layer is exposed, and tungsten is still filled up in contact hole 8, then deposits aluminium lamination again, or doped with
The aluminium lamination of copper, or doped with copper and the aluminium lamination of silicon.
It is described to deposit metal in the upper surface of insulating medium layer, metal region layer is formed, is concretely comprised the following steps：In insulating medium layer
Upper surface deposit aluminium lamination, the either aluminium lamination doped with copper or doped with copper and the aluminium lamination of silicon, and fill up contact hole 8.
The contact hole bottom oxidization layer 9 contacts with the bottom polysilicon layer 7 of contact hole 8, the top of polysilicon layer 7
Contacted with the contact metal layer bottom, the contact metal layer contacts with the source metal region layer.
Dry etching method is finally used, selective removal is not photo-etched the metal region layer of glue protection, form metal-oxide-semiconductor source
Area's metal electrode layer 14, while be also the anode metal electrodes of Schottky diode, what is left is peripheral positioned at unit cell array region
Metal region layer formed metal-oxide-semiconductor gate metal electrode；In the bottom surface deposition metal level of N+ monocrystalline substrates, drain region is formed, should
Metal level forms metal-oxide-semiconductor back side drain region metal electrode layer 15, while is also the cathodic metal electrode of Schottky diode.
The utility model principle is：The silicon chip of N-type groove MOFET devices by N-type high-dopant concentration N+ monocrystalline substrates 1
The N- epitaxial layers 2 of upper growth N-type low doping concentration are formed, and MOSFET drain electrodes are located at the highly doped hetero moiety in silicon chip bottom surface, and source electrode is located at
The more low-doped epitaxial layer portion of silicon chip surface, grid are then made up of the groove 5 perpendicular to silicon chip surface, groove MOSFET chip
The maximum reverse bias voltage that can bear is determined by the thickness and doping concentration of epitaxial layer, and the size of conducting electric current is then by leading
Total length of side of the width of electric raceway groove, i.e. groove determines, the side wall of contact hole 8 Schottky contact barrier by schottky metal and N-
Epitaxial layer 2 determines that the TMBS structures in the bottom of contact hole 8 determine having by contact hole bottom oxidization layer 9 and polysilicon layer 7
Limit under area, trench cycle is arranged to obtain effective length of side of maximum.Include groove, the minimum repeat unit of source electrode is referred to as
Unit cell, each unit cell are a complete MOSFET element.These unit cells are connected in parallel, and form MOSFET chips.
Contact hole side wall integrated schottky diode structure of the utility model in each groove MOSFET unit cell, has
The groove MOSFET of this structure can effectively reduce switching loss in power application and suppress peak voltage and peak current.
The purpose that TMBS structures reach electric field in balancing device body is formed in the bottom of contact hole simultaneously, can effectively lift the breakdown of device
Characteristic, improve device electric breakdown strength.Moreover, the utility model processing step is simple, it can in high volume put into production, reduce cost,
Increase the market competitiveness so that the utility model is progressive with prominent substantive distinguishing features and significantly.
The utility model by Schottky diode structure and TMBS structure assemblies inside source contact openings, the MOS of manufacture
Device can effectively save silicon face area, and compared with traditional approach, it is low to reduce chip cost, and unit cell integrated level is high.
In a word, the groove MOS device in the utility model, can be realized with low cost, the simple mode of processing step, and
And the groove MOSFET device of high-performance and high reliable can be obtained, reach the purpose of energy-saving and emission-reduction.
The utility model also has other selective embodiments, just no longer elaborates here.
Although embodiment of the present utility model is disclosed as above, it is not restricted in specification and embodiment
Listed utilization, it can be applied to various suitable fields of the present utility model completely, for those skilled in the art,
Other modification is easily achieved, therefore under the universal limited without departing substantially from claim and equivalency range, this reality
Specific details is not limited to new and shown here as the legend with description.
Claims (5)
1. a kind of compound groove MOS device, it is characterised in that the device includes the first conductivity type drain area, positioned at described
N+ monocrystalline substrates and N- epitaxial layers above first conductivity type drain area, the first conduction above the N- epitaxial layers
Type P type trap zone layer, the second conduction type source electrode region layer above the first conduction type P type trap zone layer, positioned at institute
State the insulating medium layer above the second conduction type source electrode region layer and the source metal area above the insulating medium layer
Layer, in addition to：
Groove, it passes through the first conduction type P type trap zone layer, extends to the inside of the N- epitaxial layers；
Gate oxide, itself and the trench contact；
Polysilicon layer, it is contacted with gate oxide, and top contacts with the insulating medium layer；
Contact hole, the contact hole pass through the insulating medium layer and the first conduction type P type trap zone layer, extend to described
N- epitaxial layers, the contact hole is interior to be filled with metal, and the top of the metal connects the metal region layer；
Contact hole bottom oxidization layer, it is located at the contact hole bottom, with the N- epitaxial layers；
Contact hole bottom polycrystal layer, it is contacted with the contact hole bottom oxidization layer, forms TMBS structures；
Contact metal layer, the contact metal layer bottom contact with contact hole bottom polycrystal layer, the contact metal layer top
Portion contacts with the source metal region layer, and the contact metal layer includes schottky contact layer and ohmic contact layer, the Xiao Te
Base contact layer is that the contact metal layer contacts in the side wall of source contact openings with the N- epitaxial layers, and the ohmic contact layer is
The contact metal layer contacts in the side wall of source contact openings with the N+ source electrodes and the first conduction type P type trap zone layer；
Wherein, the source metal region layer be metal-oxide-semiconductor source metal electrode, i.e. Schottky anode metal electrodes, described first
Conductivity type drain area is the cathodic metal electrode of metal-oxide-semiconductor drain metal electrode, i.e. Schottky.
2. compound groove MOS device according to claim 1, it is characterised in that：The schottky contact layer includes gold
Belong to tungsten articulamentum, titanium nitride barrier layer and Titanium tack coat, the tungsten articulamentum and the source metal electrode layer
Bottom contacts, the side end in contact of the titanium nitride barrier layer and the tungsten articulamentum, the Titanium tack coat and institute
State the side end in contact of titanium nitride barrier layer, lateral ends and the N- epitaxial layer of the Titanium tack coat in the contact hole
Form Schottky contacts.
3. compound groove MOS device according to claim 1, it is characterised in that ohm described in the ohmic contact layer
Contact layer is located at the side-walls of the contact hole, and the Titanium tack coat and the second conduction type source electrode region layer form N+ source electrodes
Ohmic contact；The Titanium tack coat forms the Ohmic contact of p-type trap with P+ contact zones.
4. compound groove MOS device according to claim 1, it is characterised in that the contact hole bottom oxidization layer with
N- epitaxial layers connection, the contact hole bottom polycrystal layer bottom are connected with the contact hole bottom oxidization layer, and top and
The bottom contact of source metal electrode layer, ultimately forms TMBS structures.
5. a kind of compound groove MOS device as claimed in claim 4, it is characterised in that contact hole bottom polycrystal layer is N
The polysilicon of type heavy doping.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720851556.0U CN207199624U (en) | 2017-07-13 | 2017-07-13 | A kind of compound groove MOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720851556.0U CN207199624U (en) | 2017-07-13 | 2017-07-13 | A kind of compound groove MOS device |
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| Publication Number | Publication Date |
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| CN207199624U true CN207199624U (en) | 2018-04-06 |
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ID=61785606
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| CN201720851556.0U Active CN207199624U (en) | 2017-07-13 | 2017-07-13 | A kind of compound groove MOS device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107863341A (en) * | 2017-07-13 | 2018-03-30 | 西安华羿微电子股份有限公司 | Compound groove MOS device and its manufacture method |
| CN108899277A (en) * | 2018-06-27 | 2018-11-27 | 中国电子科技集团公司第十三研究所 | The preparation method and Schottky diode of epitaxial wafer |
-
2017
- 2017-07-13 CN CN201720851556.0U patent/CN207199624U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107863341A (en) * | 2017-07-13 | 2018-03-30 | 西安华羿微电子股份有限公司 | Compound groove MOS device and its manufacture method |
| CN107863341B (en) * | 2017-07-13 | 2023-07-04 | 华羿微电子股份有限公司 | Composite groove MOS device and manufacturing method thereof |
| CN108899277A (en) * | 2018-06-27 | 2018-11-27 | 中国电子科技集团公司第十三研究所 | The preparation method and Schottky diode of epitaxial wafer |
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Address after: 710000 No. 8928, Shang Ji Road, an ecological industrial park in Xi'an, Shaanxi economic and Technological Development Zone Patentee after: HUAYI MICROELECTRONICS Co.,Ltd. Address before: 710000 No. 8928, Shang Ji Road, an ecological industrial park in Xi'an, Shaanxi economic and Technological Development Zone Patentee before: XI'AN HUAYI MICROELECTRONICS Co.,Ltd. |