CN212257385U - 晶体管封装结构 - Google Patents

晶体管封装结构 Download PDF

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CN212257385U
CN212257385U CN202021435327.9U CN202021435327U CN212257385U CN 212257385 U CN212257385 U CN 212257385U CN 202021435327 U CN202021435327 U CN 202021435327U CN 212257385 U CN212257385 U CN 212257385U
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triode
base
diode chip
temperature
package structure
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严邦杰
冯驰
林远
陆乐
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Ningbo Liyuan Technology Co ltd
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Ningbo Liyuan Technology Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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Abstract

本实用新型公开一种晶体管封装结构,包括基座,基座上固定有第一三极管、第二三极管,第一三极管的集电极与第二三极管的发射极电性连接,第一三极管的发射极和集电极之间连接有第一二极管芯片,第二三极管的发射极和集电极之间连接有第二二极管芯片,第一三极管和第二三极管分别电性连接外接引脚,还包括连接在基座上的热感应器,热感应器靠近第一三极管的发射极。本实用新型将第一三极管、第二三极管、第一二极管芯片和第二二极管芯片集成在基座上,能够节省使用时单独锡接这些芯片的时间,将上述芯片集成焊接到一个基座上,不但节省了时间,还节省了空间,热敏电阻可以将热变化为电信号,用于电磁炉等进行温度检测。

Description

晶体管封装结构
技术领域
本实用新型为晶体管封装结构领域,具体涉及一种晶体管封装结构。
背景技术
IGBT的运动温度是非常重要的参数,关乎设备的正常运行,现在普遍采取热敏电阻对IGBT进行温度检测,但是现有采用零散的电子元器件组装呈模块进行IGBT的温度检测,不但占用了大量连接空间,还增加了组装的时间,因此获得一种能够克服上述缺点的爽晶体管封装结构十分重要。
实用新型内容
为解决上述技术问题,本实用新型提供一种晶体管封装结构,包括基座,基座上固定有第一三极管、第二三极管,第一三极管的集电极与第二三极管的发射极电性连接,第一三极管的发射极和集电极之间连接有第一二极管芯片,第二三极管的发射极和集电极之间连接有第二二极管芯片,第一三极管和第二三极管分别电性连接外接引脚,还包括连接在基座上的热感应器,热感应器靠近第一三极管的发射极。
基座上电性连接有两个温度引脚,温度传感器两端分别连接在两个温度引脚上,温度引脚靠近第一IGBT的发射极。热感应器为热敏电阻。
第一三极管、第二三极管、第一二极管芯片和第二二极管芯片集成在基座上。基座为铜基座。基座上芯片外封装有树脂。
外接引脚一端固定在基座上,另一端延伸至基座外。温度引脚和外接引脚上均一体成型有凸出,能够增加引脚使用寿命,不易断裂。
与现有技术相比,本实用新型的优点在于:本实用新型将第一三极管、第二三极管、第一二极管芯片和第二二极管芯片集成在基座上,能够节省使用时单独锡接这些芯片的时间,将上述芯片集成焊接到一个基座上,不但节省了时间,还节省了空间,热敏电阻可以将热变化为电信号,用于电磁炉等进行温度检测。
附图说明
图1为本实用新型封装内部结构示意图;
图2为本实用新型封装外部结构主视图;
图3为本实用新型封装外部结构侧视图;
图4为本实用新型电路图;
附图标记:1-第一三极管;2-第二三极管;3-第一二极管芯片;4-第二二极管芯片;5-外接引脚;6-温度引脚;7-热敏电阻;8-基座;9-凸出。
具体实施方式
为了使本领域技术人员更好地理解本实用新型,从而对本实用新型要求保护的范围作出更清楚地限定,下面就本实用新型的某些具体实施例对本实用新型进行详细描述。需要说明的是,以下仅是本实用新型构思的某些具体实施方式仅是本实用新型的一部分实施例,其中对于相关结构的具体的直接的描述仅是为方便理解本实用新型,各具体特征并不当然、直接地限定本实用新型的实施范围。
参阅附图所示,本实用新型采用以下技术方案,一种晶体管封装结构,包括基座,基座上固定有第一三极管、第二三极管,第一三极管的集电极与第二三极管的发射极电性连接,第一三极管的发射极和集电极之间连接有第一二极管芯片,第二三极管的发射极和集电极之间连接有第二二极管芯片,第一三极管和第二三极管分别电性连接外接引脚,还包括连接在基座上的热感应器,热感应器靠近第一三极管的发射极。
基座上电性连接有两个温度引脚,温度传感器两端分别连接在两个温度引脚上,温度引脚靠近第一IGBT的发射极。热感应器为热敏电阻或温度传感器。
第一三极管、第二三极管、第一二极管芯片和第二二极管芯片集成在基座上。基座为铜基座。基座上芯片外封装有树脂。外接引脚一端固定在基座上,另一端延伸至基座外。温度引脚和外接引脚上均一体成型有凸出,能够增加引脚使用寿命,不易断裂。
其中第一三极管和第二三极管的大小为4900*4500um,第一二极管芯片和第二二极管芯片的大小为3500*3500um,热敏电阻大小为3200*1600um。图2和图3中的标注单位为mm。
本实用新型将第一三极管、第二三极管、第一二极管芯片和第二二极管芯片集成在基座上,能够节省使用时单独锡接这些芯片的时间,将上述芯片集成焊接到一个基座上,不但节省了时间,还节省了空间,热敏电阻可以将热变化为电信号,用于电磁炉等进行温度检测。
上述说明并非是对本实用新型的限制,本实用新型也并不仅限于上述举例,本技术领域的技术人员在本实用新型的实质范围内所做出的变化、改型、添加或替换,也应属于本实用新型的保护范围。

Claims (8)

1.一种晶体管封装结构,包括基座(8),基座(8)上固定有第一三极管(1)、第二三极管(2),第一三极管(1)的集电极与第二三极管(2)的发射极电性连接,其特征在于:所述第一三极管(1)的发射极和集电极之间连接有第一二极管芯片(3),第二三极管(2)的发射极和集电极之间连接有第二二极管芯片(4),第一三极管(1)和第二三极管(2)分别电性连接外接引脚(5),还包括连接在基座(8)上的热感应器,热感应器靠近第一三极管(1)的发射极。
2.根据权利要求1所述的晶体管封装结构,其特征在于:所述基座(8)上电性连接有两个温度引脚(6),温度传感器两端分别连接在两个温度引脚(6)上,温度引脚(6)靠近第一IGBT的发射极。
3.根据权利要求1所述的晶体管封装结构,其特征在于:所述第一三极管(1)、第二三极管(2)、第一二极管芯片(3)和第二二极管芯片(4)集成在基座(8)上。
4.根据权利要求1所述的晶体管封装结构,其特征在于:所述基座(8)为铜基座(8)。
5.根据权利要求1所述的晶体管封装结构,其特征在于:所述基座(8)上芯片外封装有树脂。
6.根据权利要求1或2所述的晶体管封装结构,其特征在于:所述热感应器为热敏电阻(7)。
7.根据权利要求1所述的晶体管封装结构,其特征在于:所述外接引脚(5)一端固定在基座(8)上,另一端延伸至基座(8)外。
8.根据权利要求2所述的晶体管封装结构,其特征在于:所述温度引脚(6)和外接引脚(5)上均一体成型有凸出(9)。
CN202021435327.9U 2020-07-20 2020-07-20 晶体管封装结构 Active CN212257385U (zh)

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