CN211957636U

CN211957636U - Wafer test structure

Info

Publication number: CN211957636U
Application number: CN202021054157.XU
Authority: CN
Inventors: 余诗李; 王子豪; 李俊成
Original assignee: Inmicro Xiamen Microelectronic Technology Co ltd
Current assignee: Inmicro Xiamen Microelectronic Technology Co ltd
Priority date: 2020-06-10
Filing date: 2020-06-10
Publication date: 2020-11-17
Anticipated expiration: 2030-06-10

Abstract

The utility model relates to a wafer test field. The utility model discloses a wafer test structure, including the wafer and form a plurality of cluster units on the wafer, the cluster unit includes a plurality of ICs and a test control unit, and each IC's test end is connected with test control unit's input through a switch circuit respectively, and switch circuit's control termination test control unit's control output end, test control unit are equipped with the output for with CP test probe card communication connection. The utility model discloses can reduce CP test needle card quantity and the number of times of pricking, improve wafer CP efficiency of software testing, reduce wafer CP test cost.

Description

Wafer test structure

Technical Field

The utility model belongs to the wafer test field specifically relates to a wafer test structure.

Background

Before the post-processing, each IC (integrated circuit) must be subjected to a wafer test (CP) to verify that the IC Die (Die) is functioning properly and to sort out bad IC dies. CP testing has become a critical step in process control, product yield management, product quality, and reduced testing costs.

The CP test is performed by contacting a probe card with a PAD (PAD) on a wafer to transmit an electrical signal using a test instrument. The existing testing method needs a probe card to perform a needle inserting test independently for each IC on a wafer, and has the following defects: with the progress of semiconductor process, the number of IC dies realized on a single wafer is increasing (for example, RFID tag IC, etc., and several tens of thousands of IC dies can be realized on a single wafer), so that the CP test is performed on the single wafer, the number of CP test pins and the number of pin pricking times are increasing, the test efficiency is low, and the test cost is high, which needs to be improved.

Disclosure of Invention

An object of the utility model is to provide a wafer test structure for solve the technical problem that the aforesaid exists.

In order to achieve the above object, the utility model adopts the following technical scheme: a wafer test structure comprises a wafer and a plurality of cluster units formed on the wafer, wherein each cluster unit comprises a plurality of ICs and a test control unit, the test end of each IC is connected with the input end of the test control unit through a switch circuit, the control end of each switch circuit is connected with the control output end of the test control unit, and the test control unit is provided with an output end used for being in communication connection with a CP test pin card.

Furthermore, a power line and a ground line connected with the plurality of cluster units are formed on the wafer, and the power line is used for supplying power to each cluster unit.

Furthermore, a plurality of ICs of each cluster unit are averagely divided into N groups, the test control unit is provided with N input ends, the N input ends are in one-to-one correspondence with the N groups of ICs, wherein N is an integer larger than 1, the number of ICs of each group of ICs is N, the test control unit is provided with N control output ends, and the control ends of N switch circuits corresponding to each group of ICs are respectively connected with the N control output ends.

Furthermore, the test control unit is composed of an MCU processor and an ADC circuit, the MCU processor is connected with the ADC circuit, and the input end of the ADC circuit is connected with the N input ends of the test control unit.

Furthermore, the number of the ADC circuits is one, the ADC circuit has N channels, and input ends of the N channels are respectively connected to N input ends of the test control unit.

Furthermore, the number of the ADC circuits is N, and the input ends of the N ADC circuits are respectively connected with the N input ends of the test control unit.

Further, the switching circuit is realized by adopting an MOS (metal oxide semiconductor) tube.

Further, the IC is an RFID chip IC.

The utility model has the advantages of:

the utility model discloses a set up the cluster unit on the wafer, adopt the cluster mode to test, CP test needle card quantity that can significantly reduce and the number of times of pricking, improve wafer CP efficiency of software testing, reduce wafer CP test cost.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a wafer test structure according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a cluster unit according to a first embodiment of the present invention;

fig. 3 is a schematic structural diagram of a cluster unit according to the second embodiment of the present invention.

Detailed Description

To further illustrate the embodiments, the present invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. With these references, one of ordinary skill in the art will appreciate other possible embodiments and advantages of the present invention. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.

The present invention will now be further described with reference to the accompanying drawings and detailed description.

Example one

As shown in fig. 1 and 2, a wafer test structure includes a wafer 1 and a plurality of cluster units 2 formed on the wafer 1, where the cluster units 2 include a plurality of ICs 21 and a test control unit 22, test terminals of the ICs 21 in each cluster unit 2 are respectively connected to input terminals of the test control unit 22 through a switch circuit 23, a control terminal of the switch circuit 23 is connected to a control output terminal (not shown in the drawings) of the test control unit 22 (to avoid complicated connection), and the test control unit 22 is provided with an output terminal for contacting and communicating with a CP test probe card.

In this embodiment, the IC 21 is an RFID tag IC, but is not limited thereto, and in other embodiments, the IC 21 may be other various ICs.

In this embodiment, the plurality of ICs 21 of each cluster unit 2 are arranged around the test control unit 2, so that the structure is compact, the size of each cluster unit 2 is reduced, the waste of the wafer 1 is reduced, and the cost is reduced, but the invention is not limited thereto.

In this embodiment, each cluster unit 2 includes 200 ICs 21, but is not limited to this, and in other embodiments, the number of ICs 21 of each cluster unit 2 may be set according to actual needs, for example, more than 200 ICs, or less than 200 ICs.

Preferably, 200 ICs 21 of each cluster unit 2 are equally divided into N groups, in this embodiment, 200 ICs 21 of each cluster unit 2 are equally divided into 10 groups, that is, each group has 20 ICs 21, the test control unit 22 is provided with 10 input terminals 223, 10 input terminals 223 are in one-to-one correspondence with 10 groups of ICs 21, that is, one input terminal 223 is simultaneously connected with 20 ICs 21 in one group of ICs 21, the test control unit 22 is provided with 20 control output terminals, the control terminals of 20 switch circuits 23 corresponding to each group of ICs 21 are respectively connected with 20 control output terminals, that is, each control output terminal of the test control unit 22 is simultaneously connected with the control terminal of one switch circuit 23 in each group of ICs 21, with this structure, the number of IO ports can be greatly saved, manufacturing is easy, and cost is low.

Of course, in other embodiments, the plurality of ICs 21 of each cluster unit 2 may be divided into more than 10 groups or less than 10 groups on average, which may be selected according to actual situations, and this is not described in detail.

Of course, in other embodiments, the plurality of ICs 21 of each cluster unit 2 may not be grouped, and are connected to the same input 223, and the switch circuit 23 corresponding to each IC 21 is connected to one control output.

In this embodiment, the test control unit 22 is composed of an MCU processor 222 and an ADC circuit 221, the MCU processor 222 is connected to the ADC circuit 221, and the input end of the ADC circuit 221 is connected to the N input ends 223 of the test control unit 22. The test control unit 22 has a simple structure and is easy to implement, but the test control unit is not limited to this, and in other embodiments, other existing test control units may also be implemented, for example, an MCU processor with an ADC acquisition function is used.

In this embodiment, the number of the ADC circuits 221 is one, the ADC circuit 221 has 10 channels, the input ends of the 10 channels are respectively connected to the 10 input ends 223, during the test, each control output end simultaneously gates one IC 21 in each group of ICs 21, and the ADC circuit 221 collects the 10 channels in a polling manner. The ADC circuit 221 is simple in structure, small in size, and low in cost, but is not limited thereto.

In this embodiment, the switch circuit 23 is preferably implemented by using MOS switches, and has high sensitivity and low power consumption, but not limited thereto, and in other embodiments, the switch circuit 23 may also be implemented by using other existing switch tubes.

In this embodiment, a power line 3 and a ground line 4 connected to the plurality of cluster units 2 are further formed on the wafer 1, and the power line 3 is used to provide power for each cluster unit 2.

In this embodiment, the output end of the test control unit 22 includes a pair of communication ports 2221 and a status indication port 2222, and the communication ports 2221 and the status indication port 2222 are both formed with pads for performing a pricking communication connection with a test pin card of the tester.

Example two

As shown in fig. 3, the present embodiment is different from the first embodiment in that: the number of the ADC circuits 221 in this embodiment is 10, and the input terminals of the 10 ADC circuits 221 are respectively connected to the 10 input terminals 223 of the test control unit 22, so that the 10 ICs 21 can be tested simultaneously, and the test efficiency is greatly improved.

Of course, in other embodiments, the number of the ADC circuits 221 may be more than 1 and less than 10, for example, 5, and each ADC circuit 221 has two channels connected to two input terminals 223, which not only improves the test efficiency, but also controls the number of the ADC circuits 221 to some extent, thereby avoiding the cost being too high.

The utility model discloses a working process:

the cluster unit 2 is supplied with power through the power line 3 and the ground line 4, and the test control unit 22 correspondingly controls the conduction of each switch circuit 23, tests each IC 21 in sequence, and records the position, the result value and the result judgment value of the IC 21.

The test pin card of the tester is adopted to perform needle inserting communication connection with the communication port 2221 and the state indication port 2222 (output end) of the test control unit 22, the tester detects the level of the state indication port 2222, and after the high level is changed into the low level, the tester can perform communication through the communication port 2221 to read the test result of the cluster unit 2, so that one time of one group of pin cards and needle inserting is realized, the test of 200 ICs 21 can be realized, the number of CP test pin cards and the number of needle inserting times are greatly reduced, the CP test efficiency of a wafer is improved, and the CP test cost of the wafer is reduced.

The utility model discloses specially adapted need not the follow-up CP test that need not to encapsulate just the small-size IC that uses, like the CP test of RFID label IC.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A wafer test structure is characterized in that: the test system comprises a wafer and a plurality of cluster units formed on the wafer, wherein each cluster unit comprises a plurality of ICs and a test control unit, the test end of each IC is connected with the input end of the test control unit through a switch circuit, the control end of each switch circuit is connected with the control output end of the test control unit, and the test control unit is provided with an output end used for being in communication connection with a CP test pin card.

2. The wafer test structure of claim 1, wherein: and a power line and a ground line which are connected with the plurality of cluster units are also formed on the wafer, and the power line is used for supplying power to each cluster unit.

3. The wafer test structure of claim 1, wherein: the multiple ICs of each cluster unit are averagely divided into N groups, the test control unit is provided with N input ends, the N input ends are in one-to-one correspondence with the N groups of ICs, wherein N is an integer larger than 1, the number of the ICs of each group of ICs is N, the test control unit is provided with N control output ends, and the control ends of the N switch circuits corresponding to each group of ICs are respectively connected with the N control output ends.

4. The wafer test structure of claim 3, wherein: the test control unit is composed of an MCU processor and an ADC circuit, the MCU processor is connected with the ADC circuit, and the input end of the ADC circuit is connected with the N input ends of the test control unit.

5. The wafer test structure of claim 4, wherein: the number of the ADC circuit is one, the ADC circuit is provided with N channels, and the input ends of the N channels are respectively connected with the N input ends of the test control unit.

6. The wafer test structure of claim 4, wherein: the number of the ADC circuits is N, and the input ends of the N ADC circuits are respectively connected with the N input ends of the test control unit.

7. The wafer test structure of claim 1, wherein: the switching circuit is realized by adopting an MOS tube.

8. The wafer test structure of claim 1, wherein: the IC is an RFID chip IC.