CN111554662A - Wafer test structure and method - Google Patents

Wafer test structure and method Download PDF

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Publication number
CN111554662A
CN111554662A CN202010522037.6A CN202010522037A CN111554662A CN 111554662 A CN111554662 A CN 111554662A CN 202010522037 A CN202010522037 A CN 202010522037A CN 111554662 A CN111554662 A CN 111554662A
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China
Prior art keywords
test
wafer
control unit
ics
test control
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CN202010522037.6A
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Chinese (zh)
Inventor
余诗李
王子豪
李俊成
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Inmicro Xiamen Microelectronic Technology Co ltd
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Inmicro Xiamen Microelectronic Technology Co ltd
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Priority to CN202010522037.6A priority Critical patent/CN111554662A/en
Publication of CN111554662A publication Critical patent/CN111554662A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention relates to the field of wafer testing. The invention discloses a wafer test structure and a method, wherein the wafer test structure comprises a wafer and a plurality of cluster units formed on the wafer, each cluster unit comprises a plurality of ICs and a test control unit, the test end of each IC is respectively connected with the input end of the test control unit through a switch circuit, the control end of each switch circuit is connected with the control output end of the test control unit, and the test control unit is provided with an output end for being in communication connection with a CP test pin card. The invention can reduce the number of CP test pins and the number of times of pin insertion, improve the CP test efficiency of the wafer, and reduce the CP test cost of the wafer.

Description

Wafer test structure and method
Technical Field
The invention belongs to the field of wafer testing, and particularly relates to a wafer testing structure and a wafer testing method.
Background
Before the post-processing, each IC (integrated circuit) must be subjected to a wafer test (CP) to verify that the IC Die (Die) is functioning properly and to sort out bad IC dies. CP testing has become a critical step in process control, product yield management, product quality, and reduced testing costs.
The CP test is performed by contacting a probe card with a PAD (PAD) on a wafer to transmit an electrical signal using a test instrument. The existing testing method needs a probe card to perform a needle inserting test independently for each IC on a wafer, and has the following defects: with the progress of semiconductor process, the number of IC dies realized on a single wafer is increasing (for example, RFID tag IC, etc., and several tens of thousands of IC dies can be realized on a single wafer), so that the CP test is performed on the single wafer, the number of CP test pins and the number of pin pricking times are increasing, the test efficiency is low, and the test cost is high, which needs to be improved.
Disclosure of Invention
The present invention is directed to a wafer testing structure and method for solving the above-mentioned problems.
In order to achieve the purpose, the invention adopts the technical scheme that: a wafer test structure comprises a wafer and a plurality of cluster units formed on the wafer, wherein each cluster unit comprises a plurality of ICs and a test control unit, the test end of each IC is connected with the input end of the test control unit through a switch circuit, the control end of each switch circuit is connected with the control output end of the test control unit, and the test control unit is provided with an output end used for being in communication connection with a CP test pin card.
Furthermore, a power line and a ground line connected with the plurality of cluster units are formed on the wafer, and the power line is used for supplying power to each cluster unit.
Furthermore, a plurality of ICs of each cluster unit are averagely divided into N groups, the test control unit is provided with N input ends, the N input ends are in one-to-one correspondence with the N groups of ICs, wherein N is an integer larger than 1, the number of ICs of each group of ICs is N, the test control unit is provided with N control output ends, and the control ends of N switch circuits corresponding to each group of ICs are respectively connected with the N control output ends.
Furthermore, the test control unit is composed of an MCU processor and an ADC circuit, the MCU processor is connected with the ADC circuit, and the input end of the ADC circuit is connected with the N input ends of the test control unit.
Furthermore, the number of the ADC circuits is one, the ADC circuit has N channels, and input ends of the N channels are respectively connected to N input ends of the test control unit.
Furthermore, the number of the ADC circuits is N, and the input ends of the N ADC circuits are respectively connected with the N input ends of the test control unit.
Further, the switching circuit is realized by adopting an MOS (metal oxide semiconductor) tube.
Further, the IC is an RFID chip IC.
The invention also provides a wafer testing method, which comprises the following steps:
s1, providing a wafer;
s2, forming a plurality of cluster units on the wafer, wherein each cluster unit comprises a plurality of ICs and a test control unit, the test end of each IC is connected with the input end of the test control unit through a switch circuit, the control end of the switch circuit is connected with the control output end of the test control unit, and the test control unit is provided with an output end;
s3, supplying power to the cluster unit, and controlling the conduction of each switch circuit by the test control unit correspondingly, testing each IC in sequence, and recording the position, result value and result judgment value of the IC;
and S4, adopting the communication connection between the test pin card of the test machine and the output end of the test control unit, and reading the test result of the cluster unit.
The invention has the beneficial technical effects that:
according to the invention, the cluster unit is arranged on the wafer, and the test is carried out in a cluster mode, so that the number of CP test pins and the number of times of inserting the CP test pins can be greatly reduced, the CP test efficiency of the wafer is improved, and the CP test cost of the wafer is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a wafer test structure according to a first embodiment of the invention;
fig. 2 is a schematic structural diagram of a cluster unit according to a first embodiment of the present invention;
fig. 3 is a schematic structural diagram of a cluster unit according to a second embodiment of the present invention.
Detailed Description
To further illustrate the various embodiments, the invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. Those skilled in the art will appreciate still other possible embodiments and advantages of the present invention with reference to these figures. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.
The invention will now be further described with reference to the accompanying drawings and detailed description.
Example one
As shown in fig. 1 and 2, a wafer test structure includes a wafer 1 and a plurality of cluster units 2 formed on the wafer 1, where the cluster units 2 include a plurality of ICs 21 and a test control unit 22, test terminals of the ICs 21 in each cluster unit 2 are respectively connected to input terminals of the test control unit 22 through a switch circuit 23, a control terminal of the switch circuit 23 is connected to a control output terminal (not shown in the drawings) of the test control unit 22 (to avoid complicated connection), and the test control unit 22 is provided with an output terminal for contacting and communicating with a CP test probe card.
In this embodiment, the IC21 is an RFID tag IC, but is not limited thereto, and in other embodiments, the IC21 may be other various ICs.
In this embodiment, the plurality of ICs 21 of each cluster unit 2 are disposed around the test control unit 2, so that the structure is compact, the size of each cluster unit 2 is reduced, the waste of the wafer 1 is reduced, and the cost is reduced, but not limited thereto,
in this embodiment, each cluster unit 2 includes 200 ICs 21, but is not limited to this, and in other embodiments, the number of ICs 21 of each cluster unit 2 may be set according to actual needs, for example, more than 200 ICs, or less than 200 ICs.
Preferably, 200 ICs 21 of each cluster unit 2 are equally divided into N groups, in this embodiment, 200 ICs 21 of each cluster unit 2 are equally divided into 10 groups, that is, each group has 20 ICs 21, the test control unit 22 is provided with 10 input terminals 223, 10 input terminals 223 are in one-to-one correspondence with 10 groups of ICs 21, that is, one input terminal 223 is simultaneously connected with 20 ICs 21 in one group of ICs 21, the test control unit 22 is provided with 20 control output terminals, the control terminals of 20 switch circuits 23 corresponding to each group of ICs 21 are respectively connected with 20 control output terminals, that is, each control output terminal of the test control unit 22 is simultaneously connected with the control terminal of one switch circuit 23 in each group of ICs 21, with this structure, the number of IO ports can be greatly saved, manufacturing is easy, and cost is low.
Of course, in other embodiments, the plurality of ICs 21 of each cluster unit 2 may be divided into more than 10 groups or less than 10 groups on average, which may be selected according to actual situations, and this is not described in detail.
Of course, in other embodiments, the plurality of ICs 21 of each cluster unit 2 may not be grouped, and are connected to the same input 223, and the switch circuit 23 corresponding to each IC21 is connected to one control output.
In this embodiment, the test control unit 22 is composed of an MCU processor 222 and an ADC circuit 221, the MCU processor 222 is connected to the ADC circuit 221, and the input end of the ADC circuit 221 is connected to the N input ends 223 of the test control unit 22. The test control unit 22 has a simple structure and is easy to implement, but the test control unit is not limited to this, and in other embodiments, other existing test control units may also be implemented, for example, an MCU processor with an ADC acquisition function is used.
In this embodiment, the number of the ADC circuits 221 is one, the ADC circuit 221 has 10 channels, the input ends of the 10 channels are respectively connected to the 10 input ends 223, during the test, each control output end simultaneously gates one IC21 in each group of ICs 21, and the ADC circuit 221 collects the 10 channels in a polling manner. The ADC circuit 221 is simple in structure, small in size, and low in cost, but is not limited thereto.
In this embodiment, the switch circuit 23 is preferably implemented by using MOS switches, and has high sensitivity and low power consumption, but not limited thereto, and in other embodiments, the switch circuit 23 may also be implemented by using other existing switch tubes.
In this embodiment, a power line 3 and a ground line 4 connected to the plurality of cluster units 2 are further formed on the wafer 1, and the power line 3 is used to provide power for each cluster unit 2.
In this embodiment, the output end of the test control unit 22 includes a pair of communication ports 2221 and a status indication port 2222, and the communication ports 2221 and the status indication port 2222 are both formed with pads for performing a pricking communication connection with a test pin card of the tester.
Example two
As shown in fig. 3, the present embodiment is different from the first embodiment in that: the number of the ADC circuits 221 in this embodiment is 10, and the input terminals of the 10 ADC circuits 221 are respectively connected to the 10 input terminals 223 of the test control unit 22, so that the 10 ICs 21 can be tested simultaneously, and the test efficiency is greatly improved.
Of course, in other embodiments, the number of the ADC circuits 221 may be more than 1 and less than 10, for example, 5, and each ADC circuit 221 has two channels connected to two input terminals 223, which not only improves the test efficiency, but also controls the number of the ADC circuits 221 to some extent, thereby avoiding the cost being too high.
The invention also provides a wafer testing method, which comprises the following steps:
s1, a wafer 1 is provided.
S2, a plurality of the above-mentioned cluster units 2 are formed on the wafer 1, and the forming process thereof can adopt the existing semiconductor processing process, which is a well-established prior art and will not be described in detail.
S3, the power supply line 3 and the ground line 4 supply power to the cluster unit 2, and the test control unit 22 correspondingly controls the switch circuits 23 to be turned on, sequentially tests the ICs 21, and records the positions, result values, and result judgment values of the ICs 21.
S4, the test probe card of the tester is used to connect with the communication port 2221 and the status indication port 2222 (output end) of the test control unit 22 for probe insertion communication, and the tester detects the level of the status indication port 2222, and after the level is changed from high level to low level, the tester can read the test result of the cluster unit 2 through the communication port 2221, and realizes one set of probe card and one probe insertion, so as to realize the test of 200 ICs 21, thereby greatly reducing the number of CP test probe cards and the number of probe insertions, improving the CP test efficiency of the wafer, and reducing the CP test cost of the wafer.
The invention is particularly suitable for the subsequent CP test of ICs which are used without packaging and have small size, such as the CP test of RFID label ICs.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. A wafer test structure is characterized in that: the test system comprises a wafer and a plurality of cluster units formed on the wafer, wherein each cluster unit comprises a plurality of ICs and a test control unit, the test end of each IC is connected with the input end of the test control unit through a switch circuit, the control end of each switch circuit is connected with the control output end of the test control unit, and the test control unit is provided with an output end used for being in communication connection with a CP test pin card.
2. The wafer test structure of claim 1, wherein: and a power line and a ground line which are connected with the plurality of cluster units are also formed on the wafer, and the power line is used for supplying power to each cluster unit.
3. The wafer test structure of claim 1, wherein: the multiple ICs of each cluster unit are averagely divided into N groups, the test control unit is provided with N input ends, the N input ends are in one-to-one correspondence with the N groups of ICs, wherein N is an integer larger than 1, the number of the ICs of each group of ICs is N, the test control unit is provided with N control output ends, and the control ends of the N switch circuits corresponding to each group of ICs are respectively connected with the N control output ends.
4. The wafer test structure of claim 3, wherein: the test control unit is composed of an MCU processor and an ADC circuit, the MCU processor is connected with the ADC circuit, and the input end of the ADC circuit is connected with the N input ends of the test control unit.
5. The wafer test structure of claim 4, wherein: the number of the ADC circuit is one, the ADC circuit is provided with N channels, and the input ends of the N channels are respectively connected with the N input ends of the test control unit.
6. The wafer test structure of claim 4, wherein: the number of the ADC circuits is N, and the input ends of the N ADC circuits are respectively connected with the N input ends of the test control unit.
7. The wafer test structure of claim 1, wherein: the switching circuit is realized by adopting an MOS tube.
8. The wafer test structure of claim 1, wherein: the IC is an RFID chip IC.
9. A wafer testing method is characterized by comprising the following steps:
s1, providing a wafer;
s2, forming a plurality of cluster units on the wafer, wherein each cluster unit comprises a plurality of ICs and a test control unit, the test end of each IC is connected with the input end of the test control unit through a switch circuit, the control end of the switch circuit is connected with the control output end of the test control unit, and the test control unit is provided with an output end;
s3, supplying power to the cluster unit, and controlling the conduction of each switch circuit by the test control unit correspondingly, testing each IC in sequence, and recording the position, result value and result judgment value of the IC;
and S4, adopting the communication connection between the test pin card of the test machine and the output end of the test control unit, and reading the test result of the cluster unit.
CN202010522037.6A 2020-06-10 2020-06-10 Wafer test structure and method Pending CN111554662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010522037.6A CN111554662A (en) 2020-06-10 2020-06-10 Wafer test structure and method

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Application Number Priority Date Filing Date Title
CN202010522037.6A CN111554662A (en) 2020-06-10 2020-06-10 Wafer test structure and method

Publications (1)

Publication Number Publication Date
CN111554662A true CN111554662A (en) 2020-08-18

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CN202010522037.6A Pending CN111554662A (en) 2020-06-10 2020-06-10 Wafer test structure and method

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Country Link
CN (1) CN111554662A (en)

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