CN210954958U - Point-to-point ultra-clear image processing equipment based on multi-window FPGA (field programmable Gate array) framework - Google Patents
Point-to-point ultra-clear image processing equipment based on multi-window FPGA (field programmable Gate array) framework Download PDFInfo
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- CN210954958U CN210954958U CN202020317017.0U CN202020317017U CN210954958U CN 210954958 U CN210954958 U CN 210954958U CN 202020317017 U CN202020317017 U CN 202020317017U CN 210954958 U CN210954958 U CN 210954958U
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Abstract
The utility model discloses a point-to-point ultra-clear image processing device based on a multi-window FPGA architecture, which comprises an input port, an input end chip group, an FPGA chip, a display and a heat dissipation device, the input port is used for connecting a plurality of monitoring devices or image receiving devices, the input end chip set is connected with the input port, the input terminal chip set is used for converting the data signal of the monitoring device or the image receiving device, the FPGA chip is connected with the input end chip group and is used for processing, analyzing and optimizing noise reduction of a plurality of data signals, the display is connected with the FPGA chip and used for converting the data signals transmitted by the FPGA chip into image signals, a plurality of image signals are displayed on the same display, the heat dissipation device is used for dissipating heat of the FPGA chip so as to improve data processing and optimize noise reduction performance. The heat dissipation effect of the FPGA chip is improved through the arrangement of the heat dissipation device, so that the damage of the FPGA chip caused by overhigh temperature is avoided.
Description
Technical Field
The utility model belongs to the technical field of the display device, more specifically say, it relates to a point-to-point super clear image processing equipment based on multi-window FPGA framework.
Background
The FPGA device belongs to a semi-custom circuit in an application-specific integrated circuit, is a programmable logic array, can effectively solve the problem of less circuits of the original device, and particularly for image processing equipment, the FPGA device can clearly and stably watch image display through multi-window-structure point-to-point ultra-clear image processing equipment formed by an FPGA chip. The basic structure of the FPGA comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, wiring resources, an embedded special hard core and a bottom layer embedded functional unit. The FPGA has the characteristics of abundant wiring resources, high repeatable programming and integration level and low investment, and is widely applied to the field of digital circuit design. The design process of the FPGA comprises algorithm design, code simulation, design and board machine debugging, wherein an algorithm framework is established by a designer and actual requirements, an EDA (electronic design automation) is used for establishing a design scheme or an HD (high definition) for compiling design codes, the code simulation is used for ensuring that the design scheme meets the actual requirements, finally, board level debugging is carried out, related files are downloaded into an FPGA chip by a configuration circuit, and the actual operation effect is verified.
FPGAThe chip is divided into a commercial grade (commercial) chip and an industrial grade (industrial), wherein the junction temperature range of the commercial grade chip for normal operation is 0-85 ℃, and the junction temperature range of the industrial grade chip is-40-100 ℃. In practiceCircuit arrangementWe must ensure that the junction temperature of the chip is within the range it can withstand.
As the power consumption of the chip increases, more and more heat is generated during operation. If the junction temperature of the chip is to be maintained within a normal range, some method is needed to quickly dissipate the heat generated by the chip to the environment. Wherein, the chip heat dissipation mode mainly has: conduction, convection, and radiation.
The heat generated by the traditional FPGA chip is generally radiated or pasted with a radiating fin through the external packaging of the chip and is directly scattered to the environment through a chip packaging shell; if the heat sink is added, the heat will be transferred from the external package of the chip to the heat sink through the heat sink glue and then from the heat sink to the environment. However, the existing heat dissipation structure still cannot make the heat dissipation effect reach the best, and cannot make the display device display and play stably; especially, when the multi-window is played, the heat generated by the chip is larger, when the chip is loaded with heat, the multi-window generates a splash screen or a flower point (though not necessarily visible to the naked eye) on the same display, and especially for a display device with high-definition display, the generated interference is more obvious (such as the chroma or the chroma is reduced).
SUMMERY OF THE UTILITY MODEL
Not enough to prior art exists, the utility model aims to provide a point-to-point super clear image processing equipment based on multi-window FPGA framework, its advantage lies in improving the radiating effect of FPGA chip to avoid the FPGA chip to lead to damaging because of the high temperature, simultaneously through the temperature that reduces the FPGA chip, improve image processing equipment's image definition and colour saturation, guarantee the steady operation at the simultaneous display multi-window simultaneously.
In order to achieve the above purpose, the utility model provides a following technical scheme:
a point-to-point ultra-clear image processing device based on a multi-window FPGA architecture comprises:
an input port for connecting a plurality of monitoring apparatuses or image receiving apparatuses;
the input end chip set is connected with the input port and used for converting data signals of the monitoring device or the image receiving device;
the FPGA chip is connected with the input end chip group and used for processing, analyzing and optimizing the noise reduction of a plurality of data signals;
the display is connected with the FPGA chip and used for converting the data signals transmitted by the FPGA chip into image signals, and the image signals are displayed on the same display;
and the heat dissipation device is used for dissipating heat of the FPGA chip so as to improve data processing and optimize noise reduction performance.
The utility model discloses further set up to: the display is divided into a plurality of windows, and the plurality of windows correspond to the plurality of image signals.
The utility model discloses further set up to: the input port is provided with a plurality of slots, the slots support hot plug function through FPGA chips, and the slots comprise HDMI sockets or DisplayPort sockets.
The utility model discloses further set up to: the FPGA chip is further connected with a split screen output port, the split screen output port is an HDMI socket or a DisplayPort socket, and the split screen output port is used for outputting different image signals to an independent display device.
The utility model discloses further set up to: the FPGA chip is also connected with a controller, and the controller is used for controlling the on-off of the FPGA chip and the cooperation with each device.
The utility model discloses further set up to: the heat dissipation device comprises a heat dissipation cover and a metal heat dissipation block, the heat dissipation cover is installed on a PCB (printed circuit board), the PCB is provided with an FPGA (field programmable gate array) chip, the FPGA chip is connected with an input end chip set through the PCB, the heat dissipation cover covers the FPGA chip in the heat dissipation cover and is tightly attached to the FPGA chip, the top wall of the heat dissipation cover is provided with the metal heat dissipation block, the bottom wall of the metal heat dissipation block is tightly attached to the top wall of the heat dissipation cover, and the metal heat dissipation block.
The utility model discloses further set up to: the radiator cap top wall is provided with the holding tank that holds the metal radiating block, holding tank demountable installation has the metal radiating block to fasten in the heat dissipation apron of radiator cap.
The utility model discloses further set up to: the circuit board corresponds the position at heat exchanger edge and has seted up a plurality of via holes that run through the PCB circuit board, heat exchanger bottom and the position that the via hole corresponds are equipped with elastic pothook, and after the pothook crowded card hole, the pothook is hung in the diapire of circuit board.
The utility model discloses further set up to: an extension block horizontally extends above the clamping hook, and the extension block is matched with the clamping hook to fix the heat dissipation cover on the PCB.
The utility model discloses further set up to: the metal radiating block is made of copper or aluminum.
To sum up, the utility model has the advantages of it is following:
1. the heat conduction capability is effectively improved by improving the contact area between the FPGA chip in the heat dissipation device and the heat dissipation cover; the metal radiating block provided with the through hole is arranged above the radiating cover, the heat of the radiating cover is absorbed through the heat conductivity of the metal, the radiating effect of the FPGA chip is further improved, and the structure is simple;
2. the heat dissipation effect of the FPGA chip is improved through the arrangement of the heat dissipation device, so that the damage of the FPGA chip caused by overhigh temperature is avoided, meanwhile, the image definition and the color saturation of the image processing equipment are improved through reducing the temperature of the FPGA chip, and meanwhile, the stable operation of multiple windows of the display is ensured.
Drawings
Fig. 1 is a perspective view of the present invention;
FIG. 2 is a schematic view of the operation principle of the present invention;
fig. 3 is a cross-sectional view of a heat dissipation device.
Description of reference numerals: 1 is the input port, 2 is the input end chipset, 3 is the FPGA chip, 4 is the display, 41 is the window, 5 is heat abstractor, 51 is the heat exchanger that looses, 52 is the metal radiating block, 53 is the heat dissipation apron, 54 is the pothook, 55 is the extension piece, 56 is the holding tank, 57 is the louvre, 6 is the output port of split screen, 7 is the controller, 8 is the PCB circuit board, 81 is the via hole.
Detailed Description
The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention.
The components of the embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention.
Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
A point-to-point ultra-clear image processing device based on multi-window 41FPGA architecture, as shown in fig. 1, includes:
an input port 1, wherein the input port 1 is used for connecting a plurality of monitoring devices or image receiving devices;
the input end chip set 2 is connected with the input port 1, and the input end chip set 2 is used for converting data signals of a monitoring device or an image receiving device;
the FPGA chip 3 is connected with the input end chip group 2, and the FPGA chip 3 is used for processing, analyzing and optimizing the noise reduction of a plurality of data signals;
the display 4 is connected with the FPGA chip 3, the display 4 is used for converting data signals transmitted by the FPGA chip 3 into image signals, and a plurality of image signals are displayed on the same display 4;
and the heat dissipation device 5 is used for dissipating heat of the FPGA chip 3 so as to improve data processing and optimize noise reduction performance.
The heat conduction capability is effectively improved by increasing the contact area between the FPGA chip 3 and the heat dissipation cover 51 in the heat dissipation device 5; a metal heat dissipation block 52 provided with a through hole is arranged above the heat dissipation cover 51, so that the heat of the heat dissipation cover 51 is absorbed through the heat conductivity of metal, the heat dissipation effect of the FPGA chip 3 is further improved, and the structure is simple; the heat dissipation effect of the FPGA chip 3 is improved through the arrangement of the heat dissipation device 5, so that the damage of the FPGA chip 3 caused by overhigh temperature is avoided, meanwhile, the image definition and the color saturation of the image processing equipment are improved through reducing the temperature of the FPGA chip 3, and meanwhile, the stable operation of the multiple windows 41 of the display 4 is ensured.
In the embodiment of the present invention, the display 4 is divided into a plurality of windows 41, and the plurality of windows 41 correspond to a plurality of image signals. The FPGA chip 3 is used for processing, analyzing, optimizing and reducing noise of the graph, and a plurality of high-definition image signals are displayed on a plurality of windows 41 of the same display 4.
The embodiment of the utility model provides an in, input port 1 is equipped with a plurality of slots and is used for being connected with different monitoring device or image receiving device, the slot supports the hot plug function through the FPGA chip, the slot includes HDMI socket or DisplayPort socket (generally for the super clear output of 4K), and the point-to-point super clear demonstration from the input to the output is followed in the realization through FPGA framework, supports the hot plug, and plug and play, the equipment interface of being convenient for subtracts the dilatation, and convenient and easy operation in the practical application has reduced the incremental cost that the function change caused by the flexibility by force, has improved customer's use and has experienced.
In the embodiment of the present invention, the FPGA chip 3 is further connected to a split screen output port 6, the split screen output port is an HDMI socket or a DisplayPort socket (generally 4K super-clear output), and the split screen output port is used for outputting different image signals to an independent display device. Such as wirelessly configured cloud playback, television, mobile device (tablet computer or mobile phone), and the like.
In the embodiment of the present invention, the FPGA chip 3 is further connected to a controller 7, and the controller 7 is used for controlling the switch of the FPGA chip 3 and cooperating with each device.
The embodiment of the utility model provides an in, heat abstractor 5 is including heat exchanger 51 and metal radiating block 52, heat exchanger 51 is installed on PCB circuit board 8, FPGA chip 3 is installed to the PCB circuit board, FPGA chip 3 is connected with input chipset 2 through PCB circuit board 8, heat exchanger 51 will FPGA chip 3 covers in it and closely laminates, and heat exchanger 51 roof is provided with the metal radiating block 52 that diapire and heat exchanger 51's roof closely laminate, metal radiating block 52 is provided with louvre 57.
Specifically, the top wall of the heat dissipation cover 51 is provided with a receiving groove 56 for receiving the metal heat dissipation block 52, and the receiving groove 56 is detachably mounted with a heat dissipation cover plate 53 for fastening the metal heat dissipation block 52 to the heat dissipation cover 51.
More specifically, the circuit board is provided with a plurality of via holes 81 penetrating through the PCB circuit board at positions corresponding to the edges of the heat dissipation cover 51, elastic hooks 54 are arranged at positions corresponding to the via holes 81 at the bottom of the heat dissipation cover 51, and the hooks 54 are hung on the bottom wall of the PCB circuit board after being extruded through the hook holes. Through the structure, the heat dissipation cover 51 is installed on the PCB, and is simple, quick and good in stability.
In the embodiment of the present invention, an extending block 55 is horizontally extended above the hook 54, and the extending block 55 and the hook 54 are matched to fix the heat sink 51 to the PCB. The heat sink 51 is fixed to the PCB by the hook 54 abutting against the extension 55.
The embodiment of the utility model provides an in, the material of metal radiating block 52 is copper or aluminium, and in metal material, copper and aluminium have better heat conductivility, are favorable to improving the radiating effect.
The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention, any modification, equivalent replacement, or improvement made within the design concept of the present invention should be included within the protection scope of the present invention.
Claims (10)
1. A point-to-point ultra-clear image processing device based on a multi-window FPGA architecture is characterized by comprising:
an input port for connecting a plurality of monitoring apparatuses or image receiving apparatuses;
the input end chip set is connected with the input port and used for converting data signals of the monitoring device or the image receiving device;
the FPGA chip is connected with the input end chip group and used for processing, analyzing and optimizing the noise reduction of a plurality of data signals;
the display is connected with the FPGA chip and used for converting the data signals transmitted by the FPGA chip into image signals, and the image signals are displayed on the same display;
and the heat dissipation device is used for dissipating heat of the FPGA chip so as to improve data processing and optimize noise reduction performance.
2. The point-to-point ultra-clear image processing device based on multi-window FPGA architecture of claim 1, characterized in that: the display is divided into a plurality of windows, and the plurality of windows correspond to the plurality of image signals.
3. The point-to-point ultra-clear image processing device based on multi-window FPGA architecture of claim 1, characterized in that: the input port is provided with a plurality of slots, the slots support hot plug functions through an FPGA chip, and the slots comprise HDMI sockets or DisplayPort sockets.
4. The point-to-point ultra-clear image processing device based on multi-window FPGA architecture of claim 1, characterized in that: the FPGA chip is further connected with a split screen output port, the split screen output port is an HDMI socket or a DisplayPort socket, and the split screen output port is used for outputting different image signals to an independent display device.
5. The point-to-point ultra-clear image processing device based on multi-window FPGA architecture of claim 1, characterized in that: the FPGA chip is also connected with a controller, and the controller is used for controlling the on-off of the FPGA chip and the cooperation with each device.
6. The point-to-point ultra-clear image processing device based on multi-window FPGA architecture of claim 1, characterized in that: the heat dissipation device comprises a heat dissipation cover and a metal heat dissipation block, the heat dissipation cover is installed on a PCB (printed circuit board), the PCB is provided with an FPGA (field programmable gate array) chip, the FPGA chip is connected with an input end chip set through the PCB, the heat dissipation cover covers the FPGA chip in the heat dissipation cover and is tightly attached to the FPGA chip, the top wall of the heat dissipation cover is provided with the metal heat dissipation block, the bottom wall of the metal heat dissipation block is tightly attached to the top wall of the heat dissipation cover, and the metal heat dissipation block.
7. The point-to-point ultra-clear image processing device based on multi-window FPGA architecture of claim 6, characterized in that: the radiator cap top wall is provided with the holding tank that holds the metal radiating block, holding tank demountable installation has the metal radiating block to fasten in the heat dissipation apron of radiator cap.
8. The point-to-point ultra-clear image processing device based on multi-window FPGA architecture of claim 7, characterized in that: the circuit board corresponds the position at heat exchanger edge and has seted up a plurality of via holes that run through the PCB circuit board, heat exchanger bottom and the corresponding position of via hole are equipped with elastic pothook, and after the pothook crowded card hole, the pothook is hung in the diapire of PCB circuit board.
9. The point-to-point ultra-clear image processing device based on multi-window FPGA architecture of claim 8, characterized in that: an extension block horizontally extends above the clamping hook, and the extension block is matched with the clamping hook to fix the heat dissipation cover on the PCB.
10. The point-to-point ultra-clear image processing device based on multi-window FPGA architecture of claim 6, characterized in that: the metal radiating block is made of copper or aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020317017.0U CN210954958U (en) | 2020-03-15 | 2020-03-15 | Point-to-point ultra-clear image processing equipment based on multi-window FPGA (field programmable Gate array) framework |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020317017.0U CN210954958U (en) | 2020-03-15 | 2020-03-15 | Point-to-point ultra-clear image processing equipment based on multi-window FPGA (field programmable Gate array) framework |
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| Publication Number | Publication Date |
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| CN210954958U true CN210954958U (en) | 2020-07-07 |
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| CN202020317017.0U Expired - Fee Related CN210954958U (en) | 2020-03-15 | 2020-03-15 | Point-to-point ultra-clear image processing equipment based on multi-window FPGA (field programmable Gate array) framework |
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Address after: A20-22, Kechuang Plaza, No. 320, pubin Road, Nanjing area, Jiangsu Free Trade Zone, Nanjing City, Jiangsu Province, 210009 Patentee after: Jiangsu maopu Intelligent Technology Co.,Ltd. Address before: Room 202, building 58, 346 Zhongshan North Road, Gulou District, Nanjing City, Jiangsu Province Patentee before: Jiangsu maopu Intelligent Technology Co.,Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200707 |