CN210837731U - Novel pin structure - Google Patents

Novel pin structure Download PDF

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Publication number
CN210837731U
CN210837731U CN201921878516.0U CN201921878516U CN210837731U CN 210837731 U CN210837731 U CN 210837731U CN 201921878516 U CN201921878516 U CN 201921878516U CN 210837731 U CN210837731 U CN 210837731U
Authority
CN
China
Prior art keywords
silicon wafer
pin
encapsulation
fixed body
pin structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201921878516.0U
Other languages
Chinese (zh)
Inventor
陈红丽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Keruitec Integrated Circuit Co ltd
Original Assignee
Shenzhen Keruitec Integrated Circuit Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Keruitec Integrated Circuit Co ltd filed Critical Shenzhen Keruitec Integrated Circuit Co ltd
Priority to CN201921878516.0U priority Critical patent/CN210837731U/en
Application granted granted Critical
Publication of CN210837731U publication Critical patent/CN210837731U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model relates to an electronic component technical field discloses a novel pin structure for high-speed data exchange chip, high-speed data exchange chip includes the fixed body and sets up encapsulation pin, silicon wafer in the fixed body, the encapsulation pin is respectively the interval setting around the silicon wafer, the length homogeneous phase of encapsulation pin, just the setting that the encapsulation pin is crooked respectively is in the fixed body, the one end of encapsulation pin respectively with the silicon wafer electricity is connected, the other end of encapsulation pin stretches out respectively the lateral wall setting of fixed body. The technical scheme of the utility model delay in can reducing the data transmission process has improved plastic envelope intensity, has improved the reliability of chip, and simple structure, low cost, the practicality is strong.

Description

Novel pin structure
Technical Field
The utility model relates to an electronic component technical field, in particular to novel pin structure.
Background
Semiconductor chips are used as core devices in electronics technology in a large number of applications in various industries. The application of the semiconductor chip greatly promotes the social productivity and facilitates the human life. However, the high degree of social development has made people rely more and more on electronic technology, from high-performance processors to tentatively accessible communication chips, memory chips, and the like. Therefore, the demand for information is increasing sharply, and the data processing capability and transmission of electronic products are required to be more efficient and stable, and the data transmission capability of semiconductor chips (data processing chips, communication chips, and memory chips) becomes a key factor that restricts the data processing capability, transmission rate, and stability of electronic products, so that the stability and reliability of data transmission are drawing attention of people while pursuing high data transmission rate, especially in the coming 5G era.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a novel pin structure aims at improving the data transmission's of chip reliability.
In order to achieve the above object, the utility model provides a novel pin structure for high-speed data exchange chip, high-speed data exchange chip includes the fixed body and sets up encapsulation pin, silicon wafer in the fixed body, the encapsulation pin is respectively the interval setting around the silicon wafer, a serial communication port, the length homogeneous phase of encapsulation pin, just the setting that the encapsulation pin is crooked respectively is in the fixed body, the one end of encapsulation pin respectively with the silicon wafer electricity is connected, the other end of encapsulation pin stretches out respectively the lateral wall setting of fixed body.
Furthermore, the packaging pins are respectively arranged in the fixing bodies in a wave-shaped bending manner.
Furthermore, the package pins are respectively spirally bent and arranged in the fixing body.
Furthermore, the packaging structure also comprises leads, wherein the leads are respectively arranged around the silicon wafer in a surrounding manner, and two ends of the leads are respectively electrically connected with the packaging pins and the silicon wafer.
Further, the length and the outer diameter of the lead are the same.
Further, the silicon wafer fixing device comprises a substrate, wherein the silicon wafer is arranged on the substrate, and the substrate is arranged in the fixing body.
Furthermore, the substrate is made of metal.
Furthermore, the fixing body is made of plastic materials.
Adopt the technical scheme of the utility model, following beneficial effect has: the technical scheme of the utility model, through designing the encapsulation pin into the wave or spiral bending structure, thereby can realize the regulation to the length of the encapsulation pin inside the chip, make the length of the inner pin tend to be consistent, reduce the delay in the data transmission process; meanwhile, the pins of the bending structure increase the external impact resistance of the chip, when external impact acts on the external pins of the chip through the pins, part of impact force is absorbed by the pins of the bending structure in the process that the impact acts on the internal part of the chip through the pins, and the damage effect of the external impact on the joint of the pins and the leads is relieved; in addition, the packaging pins of the bending structures can fully utilize space, so that the contact area between the fixing body and the pins is increased, the plastic packaging strength is improved, and the reliability of the chip is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic view of an overall structure of a novel pin structure according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view taken along line a-a in fig. 1.
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a novel pin structure.
As shown in fig. 1 and fig. 2, in an embodiment of the present invention, the novel pin structure is mainly used for a high-speed data exchange chip, the high-speed data exchange chip includes a fixing body 3 and package pins 1 and silicon wafers 4 arranged in the fixing body 3, the package pins 1 are respectively arranged around the silicon wafers 4 at intervals, the package pins 1 have the same length, the package pins 1 are respectively arranged in the fixing body 3 in a bent manner, one end of each package pin 1 is respectively electrically connected with the silicon wafers 4, the other end of each package pin 1 extends out of the outer side wall of the fixing body 3, the package pins 1 are fixed on a circuit board of an electronic product through conductive materials (such as solder, silver paste, etc.), and data exchange is performed through the package pins 1 and the silicon wafers 44.
Specifically, the package pins 1 are respectively arranged in the fixing body 3 in a wave-shaped bending manner.
Specifically, the package pins 1 are respectively spirally bent and arranged in the fixing body 3.
Specifically, the packaging structure further comprises leads 2, wherein the leads 2 are respectively arranged around the silicon wafer 4 in a surrounding mode, and two ends of each lead 2 are respectively electrically connected with the packaging pin 2 and the silicon wafer 4.
Specifically, the length and the outer diameter of the lead 2 are the same.
In particular, it also comprises a base plate 5, said silicon wafer 4 being arranged on said base plate 5, said base plate 5 being arranged inside said fixture.
Specifically, the substrate 5 is formed of a metal material.
Specifically, the fixing body 3 is made of plastic, and the substrate 5 fixes the fixing body 3 and plays roles of protecting the chip internal packaging structure and supporting the silicon wafer 4 respectively.
Particularly, the utility model discloses a design into wave or spiral curved structure with the encapsulation pin to can realize the regulation to the length of chip internal packaging pin, make internal pin length tend to unanimous, reduce the delay in the data transmission process; meanwhile, the pins of the bending structure increase the external impact resistance of the chip, when external impact acts on the external pins of the chip through the pins, part of impact force is absorbed by the pins of the bending structure in the process that the impact acts on the internal part of the chip through the pins, and the damage effect of the external impact on the joint of the pins and the leads is relieved; in addition, the packaging pins of the bending structures can fully utilize space, so that the contact area between the fixing body and the pins is increased, the plastic packaging strength is improved, and the reliability and the stability of the chip are further improved.
The above only be the preferred embodiment of the utility model discloses a not consequently restriction the utility model discloses a patent range, all are in the utility model discloses a conceive, utilize the equivalent structure transform of what the content was done in the description and the attached drawing, or direct/indirect application all is included in other relevant technical field the utility model discloses a patent protection within range.

Claims (8)

1. The utility model provides a novel pin structure for high-speed data exchange chip, high-speed data exchange chip includes the fixed body and sets up encapsulation pin, silicon wafer in the fixed body, encapsulation pin interval respectively sets up around the silicon wafer, a serial communication port, the length homogeneous phase of encapsulation pin, just the setting that encapsulation pin is crooked respectively is in the fixed body, the one end of encapsulation pin respectively with the silicon wafer electricity is connected, the other end of encapsulation pin stretches out respectively the lateral wall setting of fixed body.
2. The novel pin structure of claim 1, wherein the package pins are respectively disposed in the fixing body in a wave-shaped bending manner.
3. The novel pin structure of claim 1, wherein the package pins are respectively spirally bent and disposed in the fixing body.
4. The novel pin structure according to claim 1, further comprising leads, wherein the leads are respectively disposed around the silicon wafer, and both ends of the leads are respectively electrically connected to the package pins and the silicon wafer.
5. The novel pin structure of claim 4, wherein the length and outer diameter of the leads are the same.
6. The novel pin structure of claim 1, further comprising a substrate, said silicon wafer being disposed on said substrate, said substrate being disposed within said fixture.
7. The novel pin structure of claim 6, wherein the substrate is formed of a metal material.
8. The novel pin structure of claim 1, wherein the fixing body is made of plastic.
CN201921878516.0U 2019-11-04 2019-11-04 Novel pin structure Expired - Fee Related CN210837731U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201921878516.0U CN210837731U (en) 2019-11-04 2019-11-04 Novel pin structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201921878516.0U CN210837731U (en) 2019-11-04 2019-11-04 Novel pin structure

Publications (1)

Publication Number Publication Date
CN210837731U true CN210837731U (en) 2020-06-23

Family

ID=71260262

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201921878516.0U Expired - Fee Related CN210837731U (en) 2019-11-04 2019-11-04 Novel pin structure

Country Status (1)

Country Link
CN (1) CN210837731U (en)

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GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20200623

Termination date: 20201104