CN216354180U - Integrated circuit packaging structure - Google Patents
Integrated circuit packaging structure Download PDFInfo
- Publication number
- CN216354180U CN216354180U CN202122076399.XU CN202122076399U CN216354180U CN 216354180 U CN216354180 U CN 216354180U CN 202122076399 U CN202122076399 U CN 202122076399U CN 216354180 U CN216354180 U CN 216354180U
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- China
- Prior art keywords
- integrated circuit
- pin
- base island
- circuit chip
- pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The application provides an integrated circuit packaging structure, which comprises a base island for providing a supporting function; the integrated circuit chip is arranged on the upper side surface of the base island in an adhering mode; the pins are arranged on one side of the base island, and a plurality of leads are connected between the integrated circuit chip and the pins; and the packaging piece is used for packaging and fixing each electronic element. The application provides an integrated circuit packaging structure can connect the pin of many leads through the setting, increases output pin and outside laminating area, and unit work produces the heat and passes through pin and outside laminating department conduction to the outside, increases the radiating efficiency.
Description
Technical Field
The present application belongs to the technical field of integrated circuit design, and more particularly, to an integrated circuit package structure.
Background
The flat non-leaded package (QFN/DFN) of integrated circuit is rapidly developed in recent years along with the popularization of communication devices (such as base stations and switches), smart phones, portable devices (such as tablet computers), wearable devices (such as smart watches, smart glasses, smart bracelets, etc.), and is particularly suitable for the package of large-scale integrated circuits with electrical requirements of high frequency, high bandwidth, low noise, high heat conductivity, small volume, high speed, etc.
The flat no-lead package (QFN/DFN) of the integrated circuit effectively utilizes the packaging space of the terminal pin, thereby greatly improving the packaging efficiency. The package has good heat dissipation performance due to short lead, small size of the plastic package body and thin package body. The flat pin-free integrated circuit package consists of high molecular epoxy resin, pins, base islands, micron level noble metal leads, integrated circuit chips and adhesive. The integrated circuit chip is loaded on the base island through bonding glue, IO signals on the integrated circuit are interconnected through a micron-sized noble metal lead wire through a high-frequency ultrasonic thermal welding technology, and the signals are input to the integrated circuit through the pins, processed and transmitted to the signal output pins through the micron-sized noble metal lead wire through the output ports of the integrated circuit.
However, the existing pin design connecting wire has small welding effective area, large conduction current for application requirements, and high heat dissipation requirements, and cannot be met.
Disclosure of Invention
An object of the embodiment of the present application is to provide an integrated circuit package structure to solve the problem that the effective welding area of the pin design connecting wire in the prior art is small, the conduction current is large for the application requirement, and the product with high heat dissipation requirement cannot meet the requirement.
In order to achieve the purpose, the technical scheme adopted by the application is as follows: an integrated circuit package structure is provided, comprising:
a base island for supporting;
the integrated circuit chip is arranged on the upper side surface of the base island in an adhering mode;
the pins are arranged on one side of the base island, and a plurality of leads are connected between the integrated circuit chip and the pins;
and the packaging piece is used for packaging and fixing each electronic element.
Optionally, at least 15 leads are provided, and the leads are respectively connected with the integrated circuit chip and the plurality of pins.
Optionally, the pins include a first pin and at least one second pin, and an area of the first pin with respect to the base island is larger than an area of the second pin with respect to the base island.
Optionally, a heat sink is disposed on the first pin, one end of the lead is connected to the ic chip, and the other end of the lead is uniformly and alternately distributed on the pin and the heat sink.
Optionally, the first pin is directly connected to the base island.
Optionally, an adhesive is filled between the integrated circuit chip and the base island.
Optionally, the adhesive glue has a thickness of 10 to 35 microns.
Optionally, the package is a polymer epoxy, and the package covers the base island, the integrated circuit chip, the pins, and the leads.
Optionally, the lead is a silver wire, a copper wire, or an aluminum wire.
Optionally, the diameter of the wire is 50 microns and the length of the wire is 2 mm.
The application provides an integrated circuit packaging structure's beneficial effect lies in: compared with the prior art, the integrated circuit packaging structure of this application can connect the pin of many leads through setting up, increases output pin and outside laminating area, and unit work produces heat and passes through pin and outside laminating department conduction to the outside, increases the radiating efficiency.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of an integrated circuit package structure according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a front side heat dissipation area of an integrated circuit package structure according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a reverse heat dissipation area of an integrated circuit package structure according to an embodiment of the disclosure.
Wherein, in the figures, the respective reference numerals:
a 10-base island; 20-an integrated circuit chip; 30-pin; 31-a first pin; 32-a second pin; 33-a lead; 34-a heat sink; 35-a third pin; 40-a package; 50-adhesive glue.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1 to fig. 3, an integrated circuit package structure according to an embodiment of the present disclosure will be described. The embodiment of the application provides an integrated circuit chip packaging structure, which comprises a base island 10, an integrated circuit chip 20 and a plurality of pins 30, wherein the base island is arranged in the integrated circuit chip as a supporting part, and the integrated circuit chip 20 is arranged on the upper side of the base island 10. The integrated circuit chip 20 mainly performs signal receiving, processing and outputting functions, and a large amount of heat is generated during the operation of the integrated circuit chip 20. Therefore, the base island 10 is a member to be bonded to the integrated circuit chip 20, and heat generated from the integrated circuit chip 20 is transferred from the integrated circuit chip 20 to the base island 10, thereby performing partial heat dissipation. The lead 30 is disposed at one side of the base island 10, and the lead 30 is electrically connected to the integrated circuit chip 20. The pins 30 have the function of inputting and outputting signals of the integrated circuit chip, the pins 30 are connected with the mainboard, receive electric signals through the mainboard and transmit the electric signals to the integrated circuit chip 20, and meanwhile, command signals sent by the integrated circuit chip 20 are transmitted to all components from the mainboard.
In addition, since additional heat dissipation needs to be provided to the ic chip 20 and the electrical connection transmission effect between the ic chip 20 and the pins 30 is achieved, a plurality of leads 33 are disposed between the ic chip 20 and the pins 30. The lead 33 is a micron-sized noble metal lead, such as a silver wire, a copper wire, or an aluminum wire. In order to ensure the transmission effect and control cost and improve the thermal conductivity, in this embodiment, the lead 33 is a copper lead, which is mainly used to connect an external signal with a signal receiving port of the ic chip, so as to perform the functions of signal transmission and power output, and meanwhile, part of heat of the ic chip 20 can be transferred to the pins 30, so as to perform an additional heat dissipation function.
When the integrated circuit chip 20 works, the integrated circuit chip 20 receives signals of other components on the mainboard through the input terminal pins, the signals are transmitted through the pins and input to the input port of the integrated circuit chip 20, the integrated circuit chip 20 performs operational amplification calculation processing after receiving the signals, the result is transmitted to the output pin through the output port of the integrated circuit chip 20, the signals and the power are transmitted to the output pin through the micron-sized noble metal lead 33, and the lead 33 transmits the heat energy generated when the integrated circuit chip 20 works to the pins at the same time of signal transmission, so that a partial heat dissipation effect is achieved.
In addition, in order to improve the heat dissipation effect, in the embodiment, a plurality of pins 30 are provided, a heat sink 34 is provided on one pin 30, the heat sink 34 plays an additional role in heat dissipation on the pin 30, and heat energy transmitted to the pin 30 is dissipated to the outside of the unit device by the heat sink 34, so that excellent heat dissipation performance is achieved, and the heat dissipation effect is improved.
In the present embodiment, the lead 33 is made of a copper material lead, the diameter of the lead is 50 micrometers, the length of a single lead is designed to be calculated according to 2mm, and the conduction current of the single lead is 7.434 a. In a conventional pin design, there are typically 5 OUT PUT pins, two per pin, and the total output current is 7.434x2x 5-74.34A. However, when the on-current is greater than 80A or more, the large current and high heat dissipation requirements cannot be satisfied. For this reason, in the present embodiment, at least 15 leads 33 are optionally provided, and both ends of the leads 33 are uniformly and intermittently distributed on the integrated circuit chip 20 and the heat sink 34. The area of one of the pins 30 is designed to be larger, so that the attaching area of the pin 30 and the circuit board is increased, and at this time, the pin 30 can be connected with more leads 33. For example, in the embodiment, the number of the connectable bonding wires of the OUT PUT pin is greater than 15, and the total output current is 7.434x 15-111.48 a calculated by 15 bonding wires, so that the requirement of large current can be met, and a better heat dissipation effect is provided. In the present embodiment, one end of the plurality of leads 33 is connected to the integrated circuit chip 20, and the other end is connected to the leads 30 and the heat sink 34, respectively. Note that, in the present embodiment, the leads 30 are provided in plural, and the plural leads 30 are distributed on the peripheral side of the base island 10. A heat sink 34 is disposed on at least one of the pins 30. The number of the heat dissipation fins 34 may also be multiple, and the plurality of heat dissipation fins 34 are respectively disposed on each of the pins 30, so that a better heat dissipation effect can be achieved, which is not limited in this embodiment.
To this end, the leads 30 may optionally include a first lead 31 and at least one second lead 32, and the area of the first lead 31 with respect to the base island 10 is larger than the area of the second lead 32 with respect to the base island 10. That is, the size of the first leads 31 is larger than that of the second leads 32, so that the corresponding heat sink 34 can be disposed on the first leads 31 with larger size, and more leads 33 can be connected to the first leads 31 accordingly.
The first pin 31 and the second pin 32 are both provided with external heat dissipating points, wherein the first pin 31 is provided with two external heat dissipating points, including the surface of the first pin 31 and the heat sink 34 arranged on the other side of the first pin 31. The heat generated by the operation of the integrated circuit chip 20 is transferred to the heat dissipation points by the leads 33, thereby better providing heat dissipation.
In this embodiment, optionally, the pins 30 may further include a third pin 35, where the third pin 35 is directly connected to the base island 10, that is, when the integrated circuit chip 20 generates heat during operation, a part of heat on the base island 10 may also be transferred to the third pin 35, so that the structure is more compact while the part of heat on the base island 10 is taken away, and the heat dissipation efficiency is improved.
In the present embodiment, compared with the conventional design in which the pin and the base island are connected by the micron-sized bonding wire, the conductive cross-sectional area in the present embodiment is more than 20 times of the conductive area in the conventional design, and the heat dissipation efficiency achieved by the present embodiment is also higher than that in the conventional design, and can be more than 20 times of the heat dissipation efficiency in the conventional design, and meanwhile, the present embodiment can also be used in a use environment with a larger current.
It should be noted that, in order to ensure the stability of the connection between the integrated circuit chip 20 and the base island 10 and improve the heat conduction effect between the integrated circuit chip 20 and the base island 10, optionally, an adhesive 50 is filled between the integrated circuit chip 20 and the base island 10, and the adhesive 50 fixes and connects the integrated circuit chip 20 and the base island 10, thereby completing the fixing of the integrated circuit chip 20. It should be noted that, in order to ensure the stability of the heat conduction between the base island 10 and the integrated circuit chip 20, an adhesive material with better heat conductivity may be selected, so as to improve the heat dissipation effect to the greatest extent, which is not limited in this embodiment. In addition, in order to ensure the stability of the bonding of the adhesive 50, the thickness of the adhesive 50 is usually set to be between 10 micrometers and 35 micrometers, so that the fixing effect of the integrated circuit chip 20 can be ensured while ensuring a good heat dissipation effect.
In addition, in the present embodiment, when assembling the package structure, after the integrated circuit chip 20 and the connection pins 30 are mounted and bonded, the electronic components need to be packaged by using an additional package 40 so as to be fixed in a single unit. Generally, the package 40 is made of epoxy resin, and in order to make the components in the same unit, the package 40 needs to cover the base island 10, the integrated circuit chip 20, the pins 30 and the leads 33, and fix the relative positions of the electronic components, which is convenient for the subsequent transportation and installation.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Claims (10)
1. An integrated circuit package structure, comprising:
a base island for supporting;
the integrated circuit chip is arranged on the upper side surface of the base island in an adhering mode;
the pins are arranged on one side of the base island, and a plurality of leads are connected between the integrated circuit chip and the pins;
and the packaging piece is used for packaging and fixing each electronic element.
2. The integrated circuit package structure of claim 1, wherein: the lead wires are provided with at least 15 and are respectively connected with the integrated circuit chip and the pins.
3. The integrated circuit package structure of claim 2, wherein: the pins comprise a first pin and at least one second pin, and the area of the first pin relative to the base island is larger than that of the second pin relative to the base island.
4. The integrated circuit package structure of claim 3, wherein: the first pin is provided with a radiating fin, one end of the lead is connected with the integrated circuit chip, and the other end of the lead is uniformly distributed on the pin and the radiating fin at intervals.
5. The integrated circuit package structure of claim 3, wherein: and the third pin is directly connected with the base island.
6. The integrated circuit package structure of claim 1, wherein: and adhesive glue is filled between the integrated circuit chip and the base island.
7. The integrated circuit package structure of claim 6, wherein: the thickness of the adhesive glue is 10 to 35 microns.
8. The integrated circuit package structure of claim 1, wherein: the packaging piece is made of high polymer epoxy resin, and covers the base island, the integrated circuit chip, the pins and the leads.
9. The integrated circuit package structure of claim 1, wherein: the lead is a silver wire, a copper wire or an aluminum wire.
10. The integrated circuit package structure of claim 9, wherein: the diameter of the lead is 50 microns, and the length of the lead is 2 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122076399.XU CN216354180U (en) | 2021-08-30 | 2021-08-30 | Integrated circuit packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122076399.XU CN216354180U (en) | 2021-08-30 | 2021-08-30 | Integrated circuit packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216354180U true CN216354180U (en) | 2022-04-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122076399.XU Active CN216354180U (en) | 2021-08-30 | 2021-08-30 | Integrated circuit packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216354180U (en) |
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2021
- 2021-08-30 CN CN202122076399.XU patent/CN216354180U/en active Active
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