CN209844932U - Digital circuit for filtering signal burrs - Google Patents

Abstract

The utility model provides a digital circuit for filtering signal burrs, which comprises N time delay device chains, an AND gate, a NOR gate and a latch, wherein each time delay device chain is connected in series in sequence, and the output end of each time delay device chain is respectively connected with the input ends of the AND gate and the NOR gate; the output end of the AND gate is connected with the set end of the latch; the output terminal of the nor gate is connected to the clear terminal of the latch. The utility model provides a pair of digital circuit of filtering signal burr can effectively reduce system's consumption, and can clear away low level burr and high level burr in the filtering signal effectively, is favorable to improving the stability of chip work.

Description

Digital circuit for filtering signal burrs

Technical Field

The utility model relates to the technical field of circuits, especially, relate to a digital circuit of filtering signal burr.

Background

The chip is often disturbed by the external environment during operation, so that some digital signals inside the chip are burred. In the digital circuit, the influence of different width burr signals appears in different signals is also different, and the burr appears in some signals, will directly influence whether the chip can continue normal work, has reduced the stability of chip.

At present, in the existing technology for filtering burrs in a chip, filtering is performed in a circuit for filtering signal burrs by using a clock plus register mode, so that the effect of filtering burrs is achieved. The method needs a high-frequency clock provided by the system during filtering, increases the power consumption of the system, and because the register is used during filtering, the delay of the filtered signal before and after filtering is larger, thereby affecting the normal work of the chip.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a digital circuit of filtering signal burr is provided, the power consumption that can effectively reduce the system and the job stabilization nature that improves the chip.

To achieve the above object, an embodiment of the present invention provides a digital circuit for filtering signal glitches, which includes N chains of delay devices, an and gate, a nor gate, and a latch, wherein,

each delay device chain is sequentially connected in series, and the output end of each delay device chain is respectively connected with the input ends of an AND gate and a NOR gate;

the output end of the AND gate is connected with the set end of the latch; and the output end of the NOR gate is connected with the clearing end of the latch.

Further, the delay device chain is formed by connecting standard delay devices in series or a plurality of inverters.

The utility model provides a pair of digital circuit of filtering signal burr can effectively reduce system's consumption, and can clear away low level burr and high level burr in the filtering signal effectively, is favorable to improving the stability of chip work.

Drawings

Fig. 1 is a schematic structural diagram of a digital circuit for filtering signal glitches provided by an embodiment of the present invention.

Wherein the reference numbers in the drawings of the specification are as follows:

1. a chain of delay devices; 2. an AND gate; 3. a NOR gate; 4. a latch.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

Referring to fig. 1, a digital circuit for filtering signal glitches according to an embodiment of the present invention includes N Delay Cell chains (Delay Cell Chain), an AND gate (AND) or not gate (NOR) AND a Latch (Latch), wherein,

each delay device chain is sequentially connected in series, and the output end of each delay device chain is respectively connected with the input ends of an AND gate and a NOR gate;

the output end of the AND gate is connected with the Set end (Set) end of the latch; the output of the nor gate is connected to the clear (Clr) terminal of the latch.

In the embodiment of the present invention, the present invention provides an F _ COMB portion formed by AND gate, NOR gate AND latch instead of using AND gate AND or gate in the prior art, when the input signal of AND gate is all 1, i.e. when the output signal Q [0] Q [ N ] signal of each delay device chain is all 1, the input signal Q _ AND of AND gate is 1, AND similarly, only when the input signal Q [0] Q [ N ] signal is all 0, the output signal Q _ NOR of NOR gate is 1. The utility model discloses be connected the output of AND gate and the set end of latch, when the input signal of AND gate Q [0] ~ Q [ N ] signal is whole to be 1, the filtering result signal F _ OUT of latch output just is 1, can filter the influence of the high level burr in the front signal effectively. The utility model discloses an output with the NOR gate is connected with the end of clearing away of latch, and when the input signal of NOR gate Q [0] ~ Q [ N ] signal was all for 0 promptly, the filtering result signal F _ OUT of latch output just was 0, the influence of the low level burr in the signal before can filtering effectively.

Referring to fig. 1, in the embodiment of the present invention, the delay device chain is composed of standard delay devices connected in series, or is composed of a plurality of inverters.

The embodiment of the utility model provides an in, do delay processing through time delay device chain to the signal before the filtering, can break away from filter circuit to the demand of system clock, can reduce filter circuit's consumption effectively.

Implement the embodiment of the utility model provides a, following beneficial effect has:

the utility model carries out time delay processing on the signal before filtering through the chain connection of a plurality of time delay devices, can get rid of the requirement of the filter circuit on the system clock, and can effectively reduce the power consumption of the filter circuit; by connecting the output end of the AND gate with the set end of the latch, when the input signals of the AND gate, namely Q0-Q N signals, are all 1, the filtering result signal F _ OUT output by the latch is 1, and the influence of high level burrs in the filtering front signal can be effectively filtered. The utility model discloses an output with the NOR gate is connected with the end of clearing away of latch, and when the input signal of NOR gate Q [0] ~ Q [ N ] signal was all for 0 promptly, the filtering result signal F _ OUT of latch output just was 0, the influence of the low level burr in the signal before can filtering effectively.

The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations are also considered as the protection scope of the present invention.

Claims (2)

1. A digital circuit for filtering signal burrs is characterized by comprising N delay device chains, an AND gate, a NOR gate and a latch, wherein N is a positive integer greater than or equal to 3;

each delay device chain is sequentially connected in series, and the output end of each delay device chain is respectively connected with the input ends of the AND gate and the NOR gate;

the output end of the AND gate is connected with the set end of the latch; and the output end of the NOR gate is connected with the clearing end of the latch.

2. The digital circuit for filtering signal glitches of claim 1 in which said chain of delay devices is comprised of a series of standard delay devices or a plurality of inverters.