CN210609211U - Digital signal transmission circuit with bus idle state at high level - Google Patents
Digital signal transmission circuit with bus idle state at high level Download PDFInfo
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- CN210609211U CN210609211U CN201921626263.8U CN201921626263U CN210609211U CN 210609211 U CN210609211 U CN 210609211U CN 201921626263 U CN201921626263 U CN 201921626263U CN 210609211 U CN210609211 U CN 210609211U
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Abstract
The utility model discloses a BUS idle state is in digital signal transmission circuit of high level, including the rectifier bridge, two alternating current input ends of rectifier bridge are connected with BUS BUS1 and BUS BUS2 respectively, the anodal output of rectifier bridge is connected with the C utmost point of optoelectronic coupler U3 receiving terminal and triode Q1's C utmost point, triode Q1's E utmost point is connected with resistance RA 5's one end, resistance RA 5's the other end be connected with resistance RA 2's one end with the E utmost point of optoelectronic coupler U3 receiving terminal, resistance RA 2's the other end is connected triode Q1's B utmost point, the positive pole of optoelectronic coupler U3 transmitting terminal is connected with resistance RA 1's one end, the TX end is connected to resistance RA 1's the other end, the negative pole ground connection of optoelectronic coupler U3 transmitting terminal. The utility model discloses a circuit makes bus idle state be in the high level, the state of the real-time supervision bus of being convenient for.
Description
Technical Field
The utility model relates to a circuit field particularly, relates to a bus idle state is in digital signal transmission circuit of high level.
Background
In a general digital signal transmission circuit, a bus is in a low level state when the bus is idle, but sometimes, when a circuit fails, the bus is also in an idle state, and a large influence may be caused once the bus is found out to be not timely.
An effective solution to the problems in the related art has not been proposed yet.
SUMMERY OF THE UTILITY MODEL
To the above-mentioned technical problem among the correlation technique, the utility model provides a bus idle state is in the digital signal transmission circuit of high level, can solve above-mentioned problem.
In order to achieve the technical purpose, the technical scheme of the utility model is realized as follows:
the utility model provides a BUS idle state is in digital signal transmission circuit of high level, includes the rectifier bridge, two interchange input ends of rectifier bridge are connected with BUS BUS1 and BUS BUS2 respectively, the anodal output end of rectifier bridge is connected with the C utmost point of optoelectronic coupler U3 receiving terminal and triode Q1's C utmost point, triode Q1's E utmost point is connected with the one end of resistance RA5, the other end of resistance RA5 is connected with the one end of resistance RA2 and the E utmost point of optoelectronic coupler U3 receiving terminal, the other end of resistance RA2 is connected the B utmost point of triode Q1, the positive pole of optoelectronic coupler U3 transmitting terminal is connected with the one end of resistance RA1, the other end of resistance RA1 connects the TX terminal, the negative pole ground connection of optoelectronic coupler U3 transmitting terminal.
Further, the E pole of the transistor Q1 is connected to the signal ground.
Further, the resistance of the resistor RA1 is 330 ohms.
The utility model has the advantages that: the utility model discloses a circuit makes bus idle state be in the high level, the state of the real-time supervision bus of being convenient for.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a circuit diagram of a digital signal transmission circuit in which a bus idle state is at a high level.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art all belong to the protection scope of the present invention.
As shown in fig. 1, according to the embodiment of the present invention, a digital signal transmission circuit with a BUS idle state at a high level includes a rectifier bridge, two ac input ends of the rectifier bridge are respectively connected with a BUS1 and a BUS2, an anode output end of the rectifier bridge is connected with a C electrode of a receiving end of a photoelectric coupler U3 and a C electrode of a triode Q1, an E electrode of the triode Q1 is connected with one end of a resistor RA5, the other end of the resistor RA5 is connected with one end of a resistor RA2 and an E electrode of a receiving end of the photoelectric coupler U3, the other end of the resistor RA2 is connected with a B electrode of the triode Q1, an anode of a transmitting end of the photoelectric coupler U3 is connected with one end of the resistor RA1, the other end of the resistor RA1 is connected with a TX end, and a cathode of the transmitting end of the photoelectric coupler U3 is grounded.
In one embodiment of the present invention, the E pole of the transistor Q1 is connected to signal ground.
In a specific embodiment of the present invention, the resistance RA1 has a resistance of 330 ohms.
For the convenience of understanding the above technical solutions of the present invention, the above technical solutions of the present invention are explained in detail through specific use modes below.
When the digital signal transmission circuit is used specifically, according to the utility model discloses a bus idle state is in high level, and the bus is in high level for a long time when idle, then when the TX position has the signal to pass through, the photoelectric coupler U3 works when the TX position is high level, triode Q1 works this moment, leads to bus signal to draw down; when the TX position is low, the photo-electric coupler U3 does not work, and the bus is still high, so that the bus generates high-low level changes to transmit signals.
The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (3)
1. The utility model provides a BUS idle state is in digital signal transmission circuit of high level, includes the rectifier bridge, its characterized in that, two ac input end of rectifier bridge are connected with BUS BUS1 and BUS BUS2 respectively, the positive output end of rectifier bridge is connected with the C utmost point of photoelectric coupler U3 receiving terminal and triode Q1's C utmost point, triode Q1's E utmost point is connected with the one end of resistance RA5, the other end of resistance RA5 is connected with the one end of resistance RA2 and the E utmost point of photoelectric coupler U3 receiving terminal, the other end of resistance RA2 is connected the B utmost point of triode Q1, the positive pole of photoelectric coupler U3 transmitting terminal is connected with the one end of resistance RA1, the other end of resistance RA1 connects the TX terminal, the negative pole ground connection of photoelectric coupler U3 transmitting terminal.
2. The digital signal transmission circuit of claim 1, wherein the bus idle state is at a high level, and wherein: the E-pole of the transistor Q1 is connected to signal ground.
3. The digital signal transmission circuit of claim 1, wherein the bus idle state is at a high level, and wherein: the resistance of the resistor RA1 is 330 ohms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921626263.8U CN210609211U (en) | 2019-09-27 | 2019-09-27 | Digital signal transmission circuit with bus idle state at high level |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921626263.8U CN210609211U (en) | 2019-09-27 | 2019-09-27 | Digital signal transmission circuit with bus idle state at high level |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210609211U true CN210609211U (en) | 2020-05-22 |
Family
ID=70697362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921626263.8U Active CN210609211U (en) | 2019-09-27 | 2019-09-27 | Digital signal transmission circuit with bus idle state at high level |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210609211U (en) |
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2019
- 2019-09-27 CN CN201921626263.8U patent/CN210609211U/en active Active
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