CN103297032A - Anti-backflow circuit of multiplex interface - Google Patents

Anti-backflow circuit of multiplex interface Download PDF

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Publication number
CN103297032A
CN103297032A CN2013102101356A CN201310210135A CN103297032A CN 103297032 A CN103297032 A CN 103297032A CN 2013102101356 A CN2013102101356 A CN 2013102101356A CN 201310210135 A CN201310210135 A CN 201310210135A CN 103297032 A CN103297032 A CN 103297032A
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China
Prior art keywords
diode
triode
resistance
interface
output pin
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Pending
Application number
CN2013102101356A
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Chinese (zh)
Inventor
汪磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Ruiyi Information Technology Co Ltd
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Chengdu Ruiyi Information Technology Co Ltd
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Application filed by Chengdu Ruiyi Information Technology Co Ltd filed Critical Chengdu Ruiyi Information Technology Co Ltd
Priority to CN2013102101356A priority Critical patent/CN103297032A/en
Publication of CN103297032A publication Critical patent/CN103297032A/en
Pending legal-status Critical Current

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Abstract

The invention discloses an anti-backflow circuit of a multiplex interface. The anti-backflow circuit comprises a diode D1, a triode T1, a resistor R1 and a resistor R2. An cathode of the diode D1 is connected with a system hardware interface. An anode of the diode D1 is connected with an emitter E of the triode T1. A base set B of the triode T1 is connected with a chip output pin. A collector C of the triode T1 is grounded. The resistor R1 and the resistor R2 which are in parallel connection are connected with the anode of the diode D1. The resistor R2 is further connected with the chip output pin. By the structure, multiplex signals at the same interface are achieved, signal power supply backflow into a system chip is avoided, and abnormality and damage of the chip are avoided.

Description

The anti-back flow circuit of multiplex interface
Technical field
The present invention relates to the multiplexed signals interface, be specifically related to the anti-back flow circuit of multiplex interface.
Background technology
UART communication is a kind of transport communication of serial data bus, is that the parallel data that will receive converts serial data to and transmits, and is mainly used in asynchronous communication.This bus two-way communication can realize full duplex transmission and reception.In embedded design, UART communicates by letter with auxiliary equipment in order to main frame, as communicating by letter and communicating by letter with PC between automobile audio and the external AP.PC communication wherein comprises and monitors communicating by letter of debugger and other device.Needs for reality in communication process are understood multiplexing multiple signals on same interface usually; multiple signals appear on the same physical interface; same physical interface; did output interface when both can be used as certain signaling interface; do input interface when also can be used as other signaling interface again; if circuit is not done any isolation, just the signal power source that might occur importing is poured in down a chimney the chip of the system of entering, and causes the unusual even damage of chip.And not having corresponding technology to overcome the defective of this technology in the available circuit, this also is that we shall need improved place from now on.
Summary of the invention
The present invention has overcome the deficiencies in the prior art, and the anti-back flow circuit of multiplex interface is provided, even if on same interface multiplexing multiple signals, can not occur signal power source yet and pour in down a chimney and enter System on Chip/SoC, avoid the unusual of chip and damage.
For solving above-mentioned technical problem, the present invention is by the following technical solutions: the anti-back flow circuit of multiplex interface, comprise diode D1, triode T1, resistance R 1 and resistance R 2, the negative pole of described diode D1 is connected with the system hardware interface, and the positive pole of diode D1 is connected with the emitter E of triode T1; The basis set B of described triode T1 is connected with the chip output pin, the collector electrode C ground connection of triode T1; Described resistance R 1 and resistance R 2 are in parallel and all be connected with the positive pole of diode D1, and resistance R 2 also is connected with the chip output pin.
Further, described diode D1 is Schottky diode.
Further, described system hardware interface connects the output pin of power input or UART communication.
Further, described power input is the power input of 9V/10mA or 5V/500mA.
Compared with prior art, the invention has the beneficial effects as follows:
1, this circuit design has realized when the system hardware interface is re-used, while is as the input and output pin of unlike signal, can not produce the input signal reverse irrigated current to the signal output pin, thereby the system that influences moves normally, even damage System on Chip/SoC.The harmful effect to normal communications signal has been considered in this design simultaneously, and influence has dropped to minimum for the sequential of signal of communication.
2, the triode T1 among the present invention is as the physical isolation of chip output pin and system hardware interface, and the high-voltage large current power supply that the pin of assurance System on Chip/SoC can not be subjected to the input of system hardware interface directly impacts.
3, add a Schottky diode D1 who prevents from pouring in down a chimney at hardware interface between hardware interface and T1,5V is worked as in assurance or the 9V power supply can't pour into the UART circuit, but the signal of UART circuit can externally be exported.
Description of drawings
Fig. 1 is schematic diagram of the present invention.
Embodiment
The present invention is further elaborated below in conjunction with accompanying drawing, and embodiments of the invention are not limited thereto.
Embodiment:
As shown in Figure 1, the present invention includes diode D1, triode T1, resistance R 1 and resistance R 2, the negative pole of diode D1 wherein is connected with the system hardware interface, and the positive pole of diode D1 is connected with the emitter E of triode T1, and diode D1 is Schottky diode.The system hardware interface connects the output pin of power input or UART communication.Power input is the power input of 9V/10mA or 5V/500mA.The basis set B of the triode T1 of present embodiment is connected with the chip output pin, the collector electrode C ground connection of triode T1.The resistance R 1 of present embodiment and resistance R 2 are in parallel and all be connected with the positive pole of diode D1, and resistance R 2 also is connected with the chip output pin.
In the circuit at first with the level conversion triode T1 of UART communication simultaneously as the physical isolation of chip output pin and system hardware interface, the high-voltage large current power supply that the pin that guarantees System on Chip/SoC can not be subjected to the input of system hardware interface directly impacts.Add a Schottky diode D1 who prevents from pouring in down a chimney simultaneously between hardware interface and T1,5V is worked as in assurance or the 9V power supply can't pour into the UART circuit, but the signal of UART circuit can externally be exported.
Because this circuit is used for UART communication, when therefore requiring conducting for this Schottky diode pressure drop little, reverse recovery time is fast, just can not cause too much influence to normal UART signal of communication, and then influences normal UART communication.
Just can realize this invention as mentioned above.

Claims (4)

1. the anti-back flow circuit of multiplex interface, it is characterized in that: comprise diode D1, triode T1, resistance R 1 and resistance R 2, the negative pole of described diode D1 is connected with the system hardware interface, and the positive pole of diode D1 is connected with the emitter E of triode T1; The basis set B of described triode T1 is connected with the chip output pin, the collector electrode C ground connection of triode T1; Described resistance R 1 and resistance R 2 are in parallel and all be connected with the positive pole of diode D1, and resistance R 2 also is connected with the chip output pin.
2. the anti-back flow circuit of multiplex interface according to claim 1, it is characterized in that: described diode D1 is Schottky diode.
3. the anti-back flow circuit of multiplex interface according to claim 1 is characterized in that: described system hardware interface connects the output pin of power input or UART communication.
4. the anti-back flow circuit of multiplex interface according to claim 3, it is characterized in that: described power input is the power input of 9V/10mA or 5V/500mA.
CN2013102101356A 2013-05-31 2013-05-31 Anti-backflow circuit of multiplex interface Pending CN103297032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2013102101356A CN103297032A (en) 2013-05-31 2013-05-31 Anti-backflow circuit of multiplex interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2013102101356A CN103297032A (en) 2013-05-31 2013-05-31 Anti-backflow circuit of multiplex interface

Publications (1)

Publication Number Publication Date
CN103297032A true CN103297032A (en) 2013-09-11

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CN2013102101356A Pending CN103297032A (en) 2013-05-31 2013-05-31 Anti-backflow circuit of multiplex interface

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104038713A (en) * 2014-06-20 2014-09-10 深圳市九洲电器有限公司 Reverse current preventing device and set top box
CN104242901A (en) * 2013-11-19 2014-12-24 深圳市邦彦信息技术有限公司 Device for achieving input function and output function of single IO port at the same time and implementation method thereof
CN105357580A (en) * 2015-12-03 2016-02-24 浪潮软件集团有限公司 Set top box and system for supplying power to front-end equipment
CN106249659A (en) * 2016-08-31 2016-12-21 宁波祈禧智能科技股份有限公司 A kind of circuit being obtained signal pulse by detection change in voltage

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278615A (en) * 1990-03-28 1991-12-10 Nec Corp Level conversion circuit
CN201113972Y (en) * 2007-10-19 2008-09-10 深圳市同洲电子股份有限公司 Level switching circuit
CN202178607U (en) * 2011-08-11 2012-03-28 深圳长城开发科技股份有限公司 Handheld device and battery and external power source power supply switching circuit thereof
CN202721661U (en) * 2012-08-20 2013-02-06 安徽中兴继远信息技术股份有限公司 UART level switching circuit
CN203243306U (en) * 2013-05-31 2013-10-16 成都锐奕信息技术有限公司 Anti-backflow circuit of chip multiplexing signal interface

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03278615A (en) * 1990-03-28 1991-12-10 Nec Corp Level conversion circuit
CN201113972Y (en) * 2007-10-19 2008-09-10 深圳市同洲电子股份有限公司 Level switching circuit
CN202178607U (en) * 2011-08-11 2012-03-28 深圳长城开发科技股份有限公司 Handheld device and battery and external power source power supply switching circuit thereof
CN202721661U (en) * 2012-08-20 2013-02-06 安徽中兴继远信息技术股份有限公司 UART level switching circuit
CN203243306U (en) * 2013-05-31 2013-10-16 成都锐奕信息技术有限公司 Anti-backflow circuit of chip multiplexing signal interface

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104242901A (en) * 2013-11-19 2014-12-24 深圳市邦彦信息技术有限公司 Device for achieving input function and output function of single IO port at the same time and implementation method thereof
CN104038713A (en) * 2014-06-20 2014-09-10 深圳市九洲电器有限公司 Reverse current preventing device and set top box
CN105357580A (en) * 2015-12-03 2016-02-24 浪潮软件集团有限公司 Set top box and system for supplying power to front-end equipment
CN106249659A (en) * 2016-08-31 2016-12-21 宁波祈禧智能科技股份有限公司 A kind of circuit being obtained signal pulse by detection change in voltage

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Application publication date: 20130911