CN103326338A - Anti-interference protective circuit - Google Patents
Anti-interference protective circuit Download PDFInfo
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- CN103326338A CN103326338A CN2013102101572A CN201310210157A CN103326338A CN 103326338 A CN103326338 A CN 103326338A CN 2013102101572 A CN2013102101572 A CN 2013102101572A CN 201310210157 A CN201310210157 A CN 201310210157A CN 103326338 A CN103326338 A CN 103326338A
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- triode
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- protective circuit
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Abstract
The invention discloses an anti-interference protective circuit. The anti-interference protective circuit comprises a signal input port, a resistor R1, a resistor R2, a resistor R3, a triode T1, a diode D1 and a chip receiving pin. The signal input port, the resistor R1, the resistor R3 and the triode T1 are sequentially in series connection, the resistor R3 is connected to an emitter E of the triode T1, the resistor R2 is in linkage with the triode T1, the chip receiving pin is connected to the emitter E of the triode T1, the diode D1 is in parallel connection with the resistor R1, and the positive pole of the diode D1 is connected with the ground. By means of the structure, the anti-interference protective circuit avoids physical damage to a chip device caused by impact of a signal with high voltage and a large current.
Description
Technical field
The present invention relates to the multiplexed signals interface, be specifically related to anti-tampering protective circuit.
Background technology
UART communication is a kind of transport communication of serial data bus, is that the parallel data transformed into serial data that will receive transmits, and is mainly used in asynchronous communication.This bus two-way communication can realize full duplex transmission and reception.In embedded design, UART communicates by letter with auxiliary equipment in order to main frame, such as communicating by letter and communicating by letter with PC between automobile audio and the external AP.PC communication wherein comprises and monitors communicating by letter of debugger and other device.Needs for reality in communication process are understood multiplexing multiple signals on same interface usually; multiple signals appear on the Same Physical interface; same physical interface; did output interface when both can be used as certain signaling interface; do again input interface when also can be used as other signaling interface; inevitably interfering with each other between the different circuit signals can occur, be subject to the impact of high voltage and high current signal, cause chip device is impacted the physical damage that causes.
Summary of the invention
The present invention has overcome the deficiencies in the prior art, and anti-tampering protective circuit is provided, and avoids the signal of high-voltage large current, chip device is impacted the physical damage that causes.
For solving above-mentioned technical problem, the present invention is by the following technical solutions: anti-tampering protective circuit, comprise that signal input port, resistance R 1, resistance R 2, resistance R 3, triode T1, diode D1 and chip receive pin, described signal input port, resistance R 1, triode T1 and resistance R 3 are connected successively, and resistance R 3 is connected on the emitter E of triode T1; Described resistance R 2 is in parallel with triode T1; Described chip receives pin and is connected on the emitter E of triode T1, the plus earth of the in parallel and diode D1 of described diode D1 and resistance R 1.
Further, the basis set B of described triode T1 is connected with the negative pole of diode D1, the collector electrode C ground connection of triode T1.
Further, described diode D1 is voltage stabilizing didoe.
Further, the voltage of voltage regulation of described diode D1 is 4.3V.
Further, described signal input port can receive 9V/10mA, 5V/500mA and normal UART signal of communication.
Further, the withstand voltage of the basis set B of described triode T1 is 5V.
Compared with prior art, the invention has the beneficial effects as follows:
1, the present invention when input port is re-used, can by hanging down the signal circuit of withstand voltage and low current, not be subject to the impact failure of high voltage and high current signal by said structure.
2, the resistance R 1 of the basis set B front end of triode T1 is used as current limliting, can adjust very easily resistance, to adjust the basis set electric current of triode T1, under the large current conditions of input triode T1 is protected.
Description of drawings
Fig. 1 is schematic diagram of the present invention.
Embodiment
The present invention is further elaborated below in conjunction with accompanying drawing, and embodiments of the invention are not limited to this.
Embodiment:
As shown in Figure 1, the present invention includes signal input port, resistance R 1, resistance R 2, resistance R 3, triode T1, diode D1 and chip and receive pin, signal input port can receive 9V/10mA, 5V/500mA and normal UART signal of communication.The signal input port of the present embodiment, resistance R 1, triode T1 and resistance R 3 are connected successively, resistance R 3 is connected on the emitter E of triode T1, the basis set B of triode T1 is connected with the negative pole of diode D1, the collector electrode C ground connection of triode T1, and the withstand voltage of the basis set B of triode T1 is 5V.Resistance R 2 wherein is in parallel with triode T1, and chip receives pin and is connected on the emitter E of triode T1.The plus earth of the in parallel and diode D1 of the diode D1 of the present embodiment and resistance R 1, diode D1 is voltage stabilizing didoe, the voltage of voltage regulation of diode D1 is 4.3V.
Signal input part may receive respectively 9V/10mA in this design, 5V/500mA and normal UART signal of communication, this circuit is the level match design for UART communication, and the reception pin of System on Chip/SoC can not receive the above signal input of 3.3V, otherwise easily burns chip.At first, the triode T1 that level conversion is used can play the buffer action of signal input and System on Chip/SoC pin, guarantees that 9V and the 5V voltage of non-UART communication usefulness can not act directly on the chip, guarantees that chip is not subjected to high-voltage impact.Secondly, be the level conversion of signal of communication because of the T1 Main Function, therefore selected a switching speed fast, but the withstand voltage VEBO of base stage only is the triode of 5V, so added a voltage stabilizing didoe D1 in the base stage of T1, voltage of voltage regulation is 4.3V.Like this, when port input be 9V or 5V power supply the time, voltage stabilizing didoe D1 conducting is stabilized in 4.3V with base voltage, guarantees the safety of triode T1.The resistance R 1 of base stage front end is to use as current limliting, can adjust very easily resistance, to adjust the base current of T1, under the large current conditions of input T1 is protected.
Just can realize this invention as mentioned above.
Claims (6)
1. anti-tampering protective circuit, it is characterized in that: comprise that signal input port, resistance R 1, resistance R 2, resistance R 3, triode T1, diode D1 and chip receive pin, described signal input port, resistance R 1, triode T1 and resistance R 3 are connected successively, and resistance R 3 is connected on the emitter E of triode T1; Described resistance R 2 is in parallel with triode T1; Described chip receives pin and is connected on the emitter E of triode T1, the plus earth of the in parallel and diode D1 of described diode D1 and resistance R 1.
2. anti-tampering protective circuit according to claim 1, it is characterized in that: the basis set B of described triode T1 is connected with the negative pole of diode D1, the collector electrode C ground connection of triode T1.
3. anti-tampering protective circuit according to claim 1, it is characterized in that: described diode D1 is voltage stabilizing didoe.
4. according to claim 1 or 3 described anti-tampering protective circuits, it is characterized in that: the voltage of voltage regulation of described diode D1 is 4.3V.
5. anti-tampering protective circuit according to claim 1, it is characterized in that: described signal input port can receive 9V/10mA, 5V/500mA and normal UART signal of communication.
6. anti-tampering protective circuit according to claim 1, it is characterized in that: the withstand voltage of the basis set B of described triode T1 is 5V.
Priority Applications (1)
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CN2013102101572A CN103326338A (en) | 2013-05-31 | 2013-05-31 | Anti-interference protective circuit |
Applications Claiming Priority (1)
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CN2013102101572A CN103326338A (en) | 2013-05-31 | 2013-05-31 | Anti-interference protective circuit |
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CN103326338A true CN103326338A (en) | 2013-09-25 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106443364A (en) * | 2016-11-17 | 2017-02-22 | 济南龙航电力设备有限公司 | Active distribution network maintenance system |
CN112764451A (en) * | 2019-10-21 | 2021-05-07 | 圣邦微电子(北京)股份有限公司 | Protection circuit for improving withstand voltage of logic input port |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201204574Y (en) * | 2007-12-07 | 2009-03-04 | 中兴通讯股份有限公司 | Circuit for switching RS232 signal level |
CN101662279A (en) * | 2008-08-29 | 2010-03-03 | 深圳长城开发科技股份有限公司 | Level converting device |
CN203276158U (en) * | 2013-05-31 | 2013-11-06 | 成都锐奕信息技术有限公司 | Multiplex signal interface voltage protection circuit |
-
2013
- 2013-05-31 CN CN2013102101572A patent/CN103326338A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN201204574Y (en) * | 2007-12-07 | 2009-03-04 | 中兴通讯股份有限公司 | Circuit for switching RS232 signal level |
CN101662279A (en) * | 2008-08-29 | 2010-03-03 | 深圳长城开发科技股份有限公司 | Level converting device |
CN203276158U (en) * | 2013-05-31 | 2013-11-06 | 成都锐奕信息技术有限公司 | Multiplex signal interface voltage protection circuit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106443364A (en) * | 2016-11-17 | 2017-02-22 | 济南龙航电力设备有限公司 | Active distribution network maintenance system |
CN112764451A (en) * | 2019-10-21 | 2021-05-07 | 圣邦微电子(北京)股份有限公司 | Protection circuit for improving withstand voltage of logic input port |
CN112764451B (en) * | 2019-10-21 | 2022-09-30 | 圣邦微电子(北京)股份有限公司 | Protection circuit for improving voltage resistance of logic input port |
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Application publication date: 20130925 |