CN205563562U - FFT that can dynamicly dispose adds window device based on FPGA - Google Patents

Abstract

The utility model relates to a field, the utility model provides a FFT that can dynamicly dispose adds window device based on FPGA, in order to reduce the influence that the frequency spectrum leaked, the device includes FPGA and window function generation module, FPGA includes the ROM unit, DSP multiplication unit, address count state machine, window function generation module and ROM unit connection, the ROM unit is connected with address count state machine, the input and the ROM unit connection of DSP multiplication unit, the IQ data of window are waited to add in another input of DSP multiplication unit. The utility model provides an adding the window device and having realized that FFT adds the window, the window function type can dynamicly dispose with counting, has more that the efficient adds the window performance, and the device can work under the high frequency clock in addition, has higher stability and reliability and relatively low consumption, very big reduction the influence that brings of FFT frequency spectrum leakage.

Description

The FFT windowing device that can dynamically configure based on FPGA

Technical field

This utility model belongs to signal processing technology field, based on FPGA can dynamically join particularly to a kind of The FFT windowing device put.

Background technology

At present, FFT (Fast Fourier Transform) i.e. fast fourier transform, is that discrete Fourier becomes Change a kind of implementation rapidly and efficiently of (DFT), it is possible to realize the conversion of power side the sampled point of 2. FFT has that amount of calculation is little, be prone to hard-wired advantage, has obtained extensively should in technical field of information processing With, also it is one of the most important technological means of spectrum analysis.

But FFT realizes algorithm itself exists the defect of spectrum leakage, fence effect, need to take extra skill The impact that art means reduce spectrum leakage, spectrum analysis is brought by fence effect.It is former that spectrum leakage produces Because being that the sampled signal that FFT processes is time-limited data segment, limited data length may cause sampling Blocking of cycle, thus cause the frequency spectrum after conversion occurs in that the frequency component that signal itself does not has.

In digital signal processing, the data after sampling can be carried out windowing process, the number after will sampling According to being multiplied by a window function, such as Hanning window (Hanning), Hamming window (Hamming), Blackman window (Blackman) etc..Selecting suitable window containing postoperative, the data after windowing are being carried out FFT computing, can Significantly reduce the impact of spectrum leakage.

Domestic current digital receiver is commonly used carries out the skill of windowing process on computers to I/Q data Art, computer program, after calculating window function coefficient, be multiplied the data after obtaining windowing with I/Q data. This method itself have can select flexibly window function type, window function coefficient count be prone to configuration, design Realize the advantages such as speed is fast, but be limited to the disposal ability of computer, in the face of the data processing amount of rapid growth Time often seem unable to do what one wishes.

Utility model content

[solving the technical problem that]

The purpose of this utility model is to provide a kind of FFT windowing device that can dynamically configure based on FPGA, To reduce the impact of spectrum leakage.

[technical scheme]

This utility model is achieved through the following technical solutions.

This utility model relates to a kind of FFT windowing device that can dynamically configure based on FPGA, including FPGA With window function generation module, described FPGA includes ROM cell, DSP multiplication unit, Address count shape State machine, described window function generation module is connected with ROM cell, described ROM cell and Address count state Machine connects, and an input of described DSP multiplication unit is connected with ROM cell, described DSP multiplication list The I/Q data of windowing is treated in another input input of unit.

As one preferred embodiment, described window function generation module is configured to: according to window function and Window function coefficient count generate window function coefficient and window function, window function coefficient are counted, the corresponding window generated Function coefficients preserves the ROM cell to FPGA.

As another preferred embodiment, described Address count state machine is according to the window function type of configuration And window function coefficient counts and dynamically generates corresponding address sequence, and by mono-to ROM for the output of this address sequence The address bus of unit, ROM cell reads out the corresponding window function coefficient of storage also according to the address sequence of input This window function coefficient is sent to DSP multiplication unit.

As another preferred embodiment, also include that the IP kernel that the ROM cell with FPGA is connected is raw Become module.

As another preferred embodiment, the outfan of described DSP multiplication unit and the FFT of FPGA Unit connects.

[beneficial effect]

The technical scheme that the utility model proposes has the advantages that

(1) device that this utility model provides achieves FFT windowing, window function type and count and can dynamically join Put, there is more efficient windowing performance.

(2) this utility model provide device can be operated under high frequency clock, have higher stability and Reliability and relatively low power consumption, greatly reduce FFT spectrum and leak the impact brought.

Accompanying drawing explanation

The FFT windowing that can dynamically configure based on FPGA that Fig. 1 provides for embodiment one of the present utility model The principle schematic of device.

Detailed description of the invention

For making the purpose of this utility model, technical scheme and advantage clearer, below will be to this utility model Detailed description of the invention carry out clear, complete description.

The FFT windowing dress that can dynamically configure based on FPGA that Fig. 1 provides for this utility model embodiment one The principle schematic put.As it is shown in figure 1, include FPGA, window function generation module and IP kernel generation module, FPGA includes ROM cell, DSP multiplication unit, Address count state machine and FFT unit, wherein, DSP multiplication unit is the DSP stone unit within FPGA, and DSP stone unit can realize fixed efficiently That counts is multiply-add, and can be operated under the highest clock frequency, the DSP within current high-end FPGA Energy steady operation is the highest at 500MHz.

Window function generation module, IP kernel generation module are all connected with ROM cell, and ROM cell is counted with address Number state machine connects, and an input of DSP multiplication unit is connected with ROM cell, DSP multiplication unit The input of another input treat the I/Q data of windowing, the outfan of DSP multiplication unit is connected with FFT unit.

In the present embodiment, window function generation module is configured to: count life according to window function and window function coefficient Become window function coefficient and window function, window function coefficient are counted, the corresponding window function coefficient generated preserves extremely The ROM cell of FPGA, specifically, common window function include Hamming window, Hanning window, Blackman window, Rectangular window, quarter window etc., define window function coefficient count just can use corresponding window function generate system Number, the coefficient of generation can save as .coe file and exist to FPGA within ROM cell confession its call, It is to be appreciated that ROM cell receives the window function of window function generation module transmission, window function coefficient is counted, After the corresponding window function coefficient generated, generating corresponding IP kernel by IP kernel generation module, ROM cell can With by calling IP kernel to read corresponding window function coefficient.Address count state machine is according to the window function of configuration Type and window function coefficient are counted and are dynamically generated corresponding address sequence, and are exported extremely by this address sequence The address bus of ROM cell, ROM cell reads out the corresponding window letter of storage according to the address sequence of input This window function coefficient is also sent to DSP multiplication unit by number system number.ROM is exported by DSP multiplication unit Window function coefficient carries out multiplying with the I/Q data of input, and the result after being multiplied is directly sent in FPGA FFT unit.

As can be seen from the above embodiments, the device that this utility model embodiment provides achieves FFT windowing, Window function type and count and can dynamically configure, has more efficient windowing performance.It addition, this utility model carries The device of confession can be operated under high frequency clock, has higher stability and reliability and relatively low Power consumption, greatly reduces FFT spectrum and leaks the impact brought.

It is to be appreciated that embodiments described above is a part of embodiment of the present utility model rather than all Embodiment, is not to restriction of the present utility model.Based on embodiment of the present utility model, this area is common The every other embodiment that technical staff is obtained under not paying creative work premise, broadly falls into this practicality Novel protection domain.

Claims (5)

1. the FFT windowing device that can dynamically configure based on FPGA, it is characterised in that include FPGA With window function generation module, described FPGA includes ROM cell, DSP multiplication unit, Address count shape State machine, described window function generation module is connected with ROM cell, described ROM cell and Address count state Machine connects, and an input of described DSP multiplication unit is connected with ROM cell, described DSP multiplication list The I/Q data of windowing is treated in another input input of unit.

The FFT windowing device that can dynamically configure based on FPGA the most according to claim 1, it is special Levy and be that described window function generation module is configured to: counting according to window function and window function coefficient generates window letter Number system number and window function, window function coefficient are counted, the corresponding window function coefficient generated preserves to FPGA's ROM cell.

The FFT windowing device that can dynamically configure based on FPGA the most according to claim 2, it is special Levy and be that described Address count state machine is counted the most raw according to window function type and the window function coefficient of configuration Become corresponding address sequence, and by the address bus of this address sequence output to ROM cell, ROM cell Address sequence according to input reads out the corresponding window function coefficient of storage and is sent extremely by this window function coefficient DSP multiplication unit.

The FFT windowing device that can dynamically configure based on FPGA the most according to claim 1, it is special Levy and be also to include the IP kernel generation module that the ROM cell with FPGA is connected.

The FFT windowing device that can dynamically configure based on FPGA the most according to claim 1, it is special Levy and be that the described outfan of DSP multiplication unit is connected with the FFT unit of FPGA.