CN206629047U - A kind of anti-jamming signal processor - Google Patents
A kind of anti-jamming signal processor Download PDFInfo
- Publication number
- CN206629047U CN206629047U CN201720183799.1U CN201720183799U CN206629047U CN 206629047 U CN206629047 U CN 206629047U CN 201720183799 U CN201720183799 U CN 201720183799U CN 206629047 U CN206629047 U CN 206629047U
- Authority
- CN
- China
- Prior art keywords
- electric capacity
- base chip
- interference simulation
- interference
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model discloses a kind of anti-jamming signal processor, base chip, first resistor to the 4th resistance, the first electric capacity to the 5th electric capacity during including battery, anti-interference simulation, once run into strong jamming pulse signal, when there is deadlock phenomenon in base chip during anti-interference simulation, oscillating circuit starting of oscillation immediately, the 6th pin reset terminal of base chip, makes base chip during anti-interference simulation rework by force when exporting reset signal to an anti-interference simulation.Base chip output order during anti-interference simulation, the state for making signal remain to connect before failure continues to run with, the anti-interference of signal transmission is improved, compared with prior art, the utility model circuit structure is simple, formed using the electronic components of only ten, its cost is cheap, and the transmission to signal provides stable processing, effective anti-interference, efficiency of transmission is improved, there is the value promoted the use of.
Description
Technical field
It the utility model is related to a kind of computer-assisted device, more particularly to a kind of anti-jamming signal processor.
Background technology
Signal transacting is the system that various types of electric signals are processed with process by various expected purposes and requirement
Claim.Processing to analog signal is referred to as analog signal processing, and the processing to data signal is referred to as Digital Signal Processing.So-called " letter
Number processing ", seek to the signal being recorded on certain media to be handled, to extract the process of useful information, it is
The general designation of processing procedure such as extracted, converted, being analyzed, being integrated to signal.In the prior art, the transmission of signal can be by various
Interference, such as electromagnetic wave, reduces effectiveness, and various for the processor species of signal, function is each has something to recommend him, in line with
Excelsior spirit is, it is necessary to constantly improve and innovate.
Utility model content
The purpose of this utility model is that to solve the above problems and provides a kind of anti-jamming signal processor.
The utility model is achieved through the following technical solutions above-mentioned purpose：
The utility model includes base chip when battery, anti-interference simulation, first resistor to the 4th resistance, the first electric capacity to the
When five electric capacity, battery 6V, anti-interference simulation the model KA555 of base chip, first resistor be 200 Ω, second resistance 720
Ω, 3rd resistor are 1k Ω, the 4th resistance is 10k Ω, the first electric capacity is 0.01uf, the second electric capacity is 470uf, the 3rd electric capacity is
0.1uf, the 4th electric capacity are 800uf, the 5th electric capacity is 1000uf；
The positive pole of the battery simultaneously with base chip when the 4th pin of base chip, anti-interference simulation during anti-interference simulation
8th pin, the first end of the 3rd electric capacity, the connection of the first end of second resistance, the negative pole of battery while first with the 4th resistance
The first pin of base chip, the first end of the 4th electric capacity connect with the first end of the second electric capacity when end, anti-interference simulation, the first electricity
The first end of appearance and the first end of first resistor connect and are used as the signal input part of anti-jamming signal processor, first electricity
The second end held simultaneously with the second end of the second electric capacity, the first end of 3rd resistor, the second end of first resistor, the 3rd electric capacity
The second pin of base chip connects with the 6th pin of base chip during anti-interference simulation when the second end, anti-interference simulation, the 3rd electricity
Second end of resistance is connected with the 7th pin of base chip during anti-interference simulation and the second end of second resistance simultaneously, anti-interference simulation
When base chip the 5th pin be connected with the second end of the 4th electric capacity, the 3rd pin of base chip is simultaneously in the during anti-interference simulation
Second end of four resistance connects with the first end of the 5th electric capacity, and the second end of the 5th electric capacity is the signal of anti-jamming signal processor
Output end.
The beneficial effects of the utility model are：
The utility model is a kind of anti-jamming signal processor, compared with prior art, the letter of the utility model circuit structure
It is single, formed using the electronic components of only ten, its cost is cheap, and the transmission to signal provides stable processing, effectively
It is anti-interference, efficiency of transmission is improved, there is the value promoted the use of.
Brief description of the drawings
Fig. 1 is circuit structure schematic diagram of the present utility model.
Embodiment
The utility model is described in further detail below in conjunction with the accompanying drawings：
As shown in Figure 1：The utility model includes base chip IC when battery E, anti-interference simulation, the electricity of first resistor R1 to the 4th
Hinder the model KA555 of base chip IC, first when R4, the first electric capacity C1 to the 5th electric capacity C5, battery E are 6V, anti-interference simulation
Resistance R1 is 200 Ω, second resistance R2 is 720 Ω, 3rd resistor R3 is 1k Ω, the 4th resistance R4 is 10k Ω, the first electric capacity C1
For 0.01uf, the second electric capacity C2 be 470uf, the 3rd electric capacity C3 is 0.1uf, the 4th electric capacity C4 is 800uf, the 5th electric capacity C5 is
1000uf；
The positive pole of the battery E simultaneously with base core when the 4th pin of base chip IC, anti-interference simulation during anti-interference simulation
Piece IC the 8th pin, the 3rd electric capacity C3 first end, the connection of second resistance R2 first end, battery E negative pole is simultaneously with the
First pin of base chip IC, the 4th electric capacity C4 first end and the second electric capacity when four resistance R4 first end, anti-interference simulation
C2 first end connection, the first electric capacity C1 first end are connected with first resistor R1 first end and are used as anti-jamming signal to handle
The signal input part IN, the first electric capacity C1 of device the second end the second end with the second electric capacity C2,3rd resistor R3 simultaneously
When first end, first resistor R1 the second end, the 3rd electric capacity C3 the second end, anti-interference simulation the second pin of base chip IC and
The 6th pin connection of base chip IC during anti-interference simulation, 3rd resistor R3 the second end simultaneously with base chip during anti-interference simulation
IC the 7th pin connects with second resistance R2 the second end, the 5th pin and the 4th electric capacity of base chip IC during anti-interference simulation
C4 the second end connection, the 3rd pin of base chip IC is simultaneously in the 4th resistance R4 the second end and the 5th electricity during anti-interference simulation
Hold C5 first end connection, the 5th electric capacity C5 the second end is the signal output part OUT of anti-jamming signal processor.
Operation principle of the present utility model is as follows：
Multi-harmonic-oscillations are formed by base chip IC, the first electric capacity Cl, the 4th electric capacity C4 and the 5th electric capacity C5 during anti-interference simulation
Device circuit, the 4th electric capacity C4 are constantly changed by the pin discharge and recharge of base chip IC the 5th during anti-interference simulation, its voltage levels, are resisted
The pin of base chip IC the 3rd is output end during interference simulation, and second resistance R2 is feedback resistance.In normal work, anti-interference mould
The 3rd pin timing of base chip IC sends pulse signal during plan, plays clamping action by second resistance R2, oscillating circuit is not
Can starting of oscillation.Once running into strong jamming pulse signal, when deadlock phenomenon occurs in base chip IC during anti-interference simulation, oscillating circuit is immediately
Starting of oscillation, the 6th pin reset terminal of base chip IC, makes anti-interference simulation by force when exporting reset signal to an anti-interference simulation
When base chip IC rework.Base chip IC output order during anti-interference simulation, signal is set to remain to connect the state continuation before failure
Operation, the anti-interference of signal transmission is improved, the input of signal filter by the first electric capacity C1, and it is electric to pass through the 5th again during output
Hold C5 secondary filterings, effective trap signal.
The advantages of general principle and principal character of the present utility model and the utility model has been shown and described above.One's own profession
The technical staff of industry it should be appreciated that the utility model is not limited by examples detailed above, described in examples detailed above and specification only
It is to illustrate principle of the present utility model, on the premise of the spirit and scope of the utility model is not departed from, the utility model also has
Various changes and modifications, these changes and improvements are both fallen within claimed the scope of the utility model.The requires of the utility model
Protection domain is by appended claims and its equivalent thereof.
Claims (1)
- A kind of 1. anti-jamming signal processor, it is characterised in that：Base chip, first resistor be extremely during including battery, anti-interference simulation The model KA555 of base chip, first resistor when the 4th resistance, the first electric capacity to the 5th electric capacity, battery 6V, anti-interference simulation For 200 Ω, second resistance be 720 Ω, 3rd resistor is 1k Ω, the 4th resistance is 10k Ω, the first electric capacity is 0.01uf, second Electric capacity is 470uf, the 3rd electric capacity is 0.1uf, the 4th electric capacity is 800uf, the 5th electric capacity is 1000uf；The positive pole of the battery simultaneously with during anti-interference simulation when the 4th pin of base chip, anti-interference simulation base chip the 8th Pin, the first end of the 3rd electric capacity, the connection of the first end of second resistance, the negative pole of battery simultaneously the first end with the 4th resistance, The first pin of base chip, the first end of the 4th electric capacity connect with the first end of the second electric capacity during anti-interference simulation, the first electric capacity First end and the first end of first resistor connect and be used as the signal input part of anti-jamming signal processor, first electric capacity The second end simultaneously with the second end of the second electric capacity, the first end of 3rd resistor, the second end of first resistor, the 3rd electric capacity the The second pin of base chip connects with the 6th pin of base chip during anti-interference simulation when two ends, anti-interference simulation, 3rd resistor The second end be connected simultaneously with the 7th pin of base chip during anti-interference simulation and the second end of second resistance, during anti-interference simulation 5th pin of base chip is connected with the second end of the 4th electric capacity, and the 3rd pin of base chip is simultaneously in the 4th during anti-interference simulation Second end of resistance connects with the first end of the 5th electric capacity, and the second end of the 5th electric capacity is defeated for the signal of anti-jamming signal processor Go out end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720183799.1U CN206629047U (en) | 2017-02-28 | 2017-02-28 | A kind of anti-jamming signal processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720183799.1U CN206629047U (en) | 2017-02-28 | 2017-02-28 | A kind of anti-jamming signal processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206629047U true CN206629047U (en) | 2017-11-10 |
Family
ID=60210161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720183799.1U Expired - Fee Related CN206629047U (en) | 2017-02-28 | 2017-02-28 | A kind of anti-jamming signal processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206629047U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107818070A (en) * | 2017-11-23 | 2018-03-20 | 商洛学院 | A kind of data transfer of computer anti-interference process device |
-
2017
- 2017-02-28 CN CN201720183799.1U patent/CN206629047U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107818070A (en) * | 2017-11-23 | 2018-03-20 | 商洛学院 | A kind of data transfer of computer anti-interference process device |
| CN107818070B (en) * | 2017-11-23 | 2023-03-21 | 商洛学院 | Computer data transmission anti-interference processor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171110 Termination date: 20180228 |