CN209626199U - 半导体封装 - Google Patents

半导体封装 Download PDF

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CN209626199U
CN209626199U CN201821861839.4U CN201821861839U CN209626199U CN 209626199 U CN209626199 U CN 209626199U CN 201821861839 U CN201821861839 U CN 201821861839U CN 209626199 U CN209626199 U CN 209626199U
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wall
semiconductor packages
substrate
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molding
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谢有德
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Semiconductor Components Industries LLC
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Abstract

一种半导体封装，该半导体封装的实施方式可包括：衬底、电耦合至衬底的管芯、以及耦接至衬底壁的壁。该壁可围绕管芯的周边延伸。该壁可包括形成于该壁中的模塑围堤。该半导体封装还可包括玻璃盖，该玻璃盖耦接至壁和模塑围堤。模塑料可耦接到模塑围堤中并且跨越玻璃盖的厚度。

Description

半导体封装
技术领域
本文档的各方面整体涉及半导体封装，诸如用于图像传感器阵列的芯片尺寸封装。更具体的实施方式涉及互补金属氧化物半导体CMOS图像传感器 (CIS)、塑料无引线芯片载体(PLCC)和陶瓷无引线芯片载体(CLCC)。
背景技术
传统上，为了密封半导体封装，将干膜或树脂施加到玻璃盖。然后使用干膜或树脂将玻璃盖附接到衬底。该技术有助于控制玻璃倾斜并且有助于间隙高度的一致性。
实用新型内容
根据一实施方式，一种半导体封装包括：衬底；管芯，所述管芯电耦合至所述衬底；壁，所述壁耦接至所述衬底，所述壁围绕在所述管芯的周边延伸，所述壁包括形成于该壁中的模塑围堤；玻璃盖，所述玻璃盖耦接至所述壁和所述模塑围堤；和模塑料，所述模塑料耦接到所述模塑围堤中并且跨越所述玻璃盖的厚度。
半导体封装的实施方式可包括以下各项中的一项、全部或任一项：
该衬底可为印刷电路板、陶瓷材料或引线框架。
该壁可通过传递模塑、压缩模塑或注射模塑形成。
模塑料可为以下中的一者：粒状环氧树脂、树脂、环氧树脂、有机硅、丙烯酸、聚酰亚胺或它们的任何组合。
模塑料可形成气密密封。
半导体封装可为塑料无引线芯片载体(PLCC)、陶瓷无引线芯片载体(CLCC) 或者互补金属氧化物半导体(CMOS)图像传感器(CIS)。
半导体封装的实施方式可包括：衬底以及电耦合至衬底的一个或多个管芯。半导体封装还可包括壁，该壁耦接至衬底和玻璃盖。该壁可围绕管芯的周边延伸。金属层可跨越衬底的厚度、壁及玻璃盖的厚度耦接。金属层可形成一个或多个管芯的大体气密密封。
半导体封装的实施方式可包括以下各项中的一项、全部或任一项：
该衬底可为印刷电路板、陶瓷材料或引线框架。
金属层可包括镍、铜、铝、铬或它们的任何组合。
金属层可通过以下中的一者耦接至半导体封装：等离子溅射、化学气相沉积、电镀、化学镀或浸镀。
金属层可保护半导体封装免受电磁干扰(EMI)和静电放电(ESD)的影响。
半导体封装可为塑料无引线芯片载体(PLCC)、陶瓷无引线芯片载体 (CLCC)、或者互补金属氧化物半导体(CMOS)图像传感器(CIS)。
根据另一实施方式，一种半导体封装包括：衬底；一个或多个管芯，所述一个或多个管芯电耦合至所述衬底；壁，所述壁耦接至所述衬底和玻璃盖，所述壁围绕所述管芯的周边延伸；金属层，所述金属层跨越所述衬底的厚度、所述壁以及所述玻璃盖的厚度耦接。其中，所述金属层形成用于所述一个或多个管芯的大体气密密封。
对于本领域的普通技术人员而言，通过具体实施方式以及附图并通过权利要求书，上述以及其他方面、特征和优点将会显而易见。
附图说明
将在下文中结合附图来描述各实施方式，其中类似标号表示类似元件，并且：
图1是如本文所述的半导体封装的实施方式的剖视图；
图2A是两个或更多个壁与之耦接的衬底片材的实施方式的侧视图；
图2B是两个或更多个管芯与之耦接的衬底片材的实施方式的侧视图；
图2C是衬底片材的实施方式的侧视图，其中两个或更多个玻璃盖耦接至两个或更多个壁；
图2D是衬底片材的实施方式的侧视图，其中模塑料位于两个或更多个玻璃盖之间的模塑围堤中；
图2E是在衬底片材切单后半导体封装的实施方式的侧视图；
图3是半导体封装的实施方式的侧视图，其中金属层跨越半导体封装的衬底、壁和玻璃盖的厚度耦接；并且
图4A至图4B是用于将金属镀覆在半导体封装的侧壁上的方法的实施方式。
具体实施方式
本公开、其各方面以及实施方式并不限于本文所公开的具体部件、组装工序或方法元素。本领域已知的符合预期半导体封装的许多另外的部件、组装工序和/或方法元素将显而易见地能与本公开的特定实施方式一起使用。因此，例如，尽管本实用新型公开了具体实施方式，但是此类实施方式和实施部件可包括符合预期操作和方法的本领域已知用于此类半导体封装以及实施部件和方法的任何形状、尺寸、样式、类型、模型、版本、量度、浓度、材料、数量、方法元素、步骤等。
参见图1，示出了半导体封装2的实施方式的横截面。半导体封装包括管芯4，该管芯通过两个或更多个引线接合8来耦接至衬底6。在各种实施方式中，该管芯可通过不包括引线接合的其他方法来耦接至衬底，作为非限制性示例，这些方法诸如为球栅阵列(BGA)、接点栅格阵列(LGA)、焊球以及其他互连技术。作为非限制性示例，该管芯可为图像传感器芯片。在各种实施方式中，作为非限制性示例，该衬底可为印刷电路板、陶瓷材料、引线框架或本领域已知的其他合适材料。印刷电路板可由双马来酰亚胺-三嗪(BT)树脂、FR-4等级玻璃增强环氧树脂层压板、FR-5等级玻璃增强环氧树脂层压板以及它们的任何组合制成。
如图1所示，壁10耦接至衬底并且围绕管芯的周边延伸。作为非限制性示例，该壁可通过传递模塑、压缩模塑、注射模塑或在衬底上形成材料的其他方法来形成。该壁可通过模塑料与衬底之间的粘附特性来耦接至衬底。如图所示，壁10包括模塑围堤12，该模塑围堤填充有模塑料14。模塑料14将玻璃盖16 耦接至壁10的上表面。在各种实施方式中，模塑料14可在玻璃盖16与壁10 之间形成气密或大体气密密封。在各种实施方式中，模塑料可包括粒状树脂、粒状环氧树脂、环氧树脂、热固性树脂、凝胶弹性体、密封剂、灌封料、复合物、光学级材料、有机硅以及它们的任何组合。
在一些实施方式中，可对玻璃盖进行蚀刻、开槽或折边以增加壁与盖之间以及模塑料与盖之间的接合的强度。作为非限制性示例，可通过激光刻槽、片锯或类似技术蚀刻该盖。作为非限制性示例，玻璃的蚀刻可引起玻璃的边缘的横截面类似于底座、凸缘、斜接、斜面、双斜面、圆端、葱形边缘或从玻璃延伸或陷进玻璃中的任何形状。虽然玻璃的边缘的形状在玻璃的所有侧面上可相同，但在各种实施方式中，在玻璃的一个或多个侧面上可存在与玻璃的其他侧面不同的边缘形状。玻璃盖的边缘的成形还可用于在该盖由玻璃以外的材料制成时增强接合。
通过本文所公开的接合技术和结构而形成的气密密封可保护半导体封装不受水分侵入的影响，该水分侵入通常由用于模拟设备在潮湿环境中随时间推移的操作的高加速温度和湿度应力测试(HAST)引起。在典型塑料无引线芯片载体 (PLCC)和陶瓷无引线芯片载体(CLCC)中，HAST和温度湿度(TH)测试引起可靠性问题，因为水分最终渗透玻璃与围堤之间的树脂接合界面，从而将水分引入到半导体封装的气腔中。水分侵入引发其他封装可靠性问题，诸如电流泄漏和图像缺陷一直到灾难性故障，如玻璃盖在水分膨胀下从该壁崩裂时所出现的爆裂。在半导体封装2的本实施方式中，玻璃盖表面和壁上部上方的模塑料可充当水分侵入的屏障。
除了图像传感器之外，图1所示的半导体封装还可用于背照式传感器。本文所公开的方法和原理还可用于形成管芯堆叠式设备，在该设备的管芯边缘与像素阵列之间具有狭窄空间。作为非限制性示例，管芯堆叠式设备的示例可包括堆叠式图像传感器和一个或多个图像传感器处理器；堆叠式图像传感器、一个或多个图像传感器处理器和存储器；堆叠式图像传感器、一个或多个无源部件管芯和一个或多个图像传感器处理器、以及它们的任何组合。
参见图2A至图2E，示出了形成半导体封装的方法的实施方式。在图2A 中，示出了衬底片材18。两个或更多个壁20耦接至衬底片材18。壁20可通过环氧树脂或通过这些材料的粘附特性来耦接至衬底片材18。在其他实施方式中，这些壁可使用模塑工艺直接形成到衬底片材18上。如图2A所示，壁20 包括模塑围堤22，从而为这些壁的上表面赋予凹形/开槽结构。模塑围堤的凹形 /开槽结构可使用模塑工具形成。壁/模塑围堤可直接由环氧化合物制成，并且可通过传递模塑、压缩模塑、注射模塑或其他合适方法形成。在各种实施方式中，这些壁可由本文所公开的任何其他可模塑材料形成。
在其他实施方式中，模塑围堤的凹形/开槽结构可使用模塑以外的工艺形成。作为非限制性示例，凹形/开槽结构可使用切割、蚀刻、烧蚀、熔融或能够使得用于形成围堤的材料成形的另一种工艺来形成。在使用这些其他工艺的情况下，围堤的材料可不为聚合材料，但作为非限制性示例，可为复合物、金属、半导体或能够与玻璃盖接合的其他刚性材料。
参见图2B，三个管芯24通过每个管芯的两个引线接合26来以机械的方式和电的方式耦合至衬底18。在其他实施方式中，可在每个管芯上使用两个或更多个引线接合。在各种实施方式中，管芯可通过任何其他互连技术(诸如此前所述的那些)耦接至衬底。作为非限制性示例，两个或更多个管芯可耦接至每组壁之间的衬底。在各种实施方式中，管芯24可包括图像传感器阵列。在其他实施方式中，背照式传感器可用于该封装。在还其他实施方式中，如此前所提及，该方法可用于三维堆叠管芯技术。
参见图2C，三个玻璃盖28耦接至壁20。在各种实施方式中，两个或更多个玻璃盖可耦接在两个或更多个管芯24上方。从图2C中可以看出，玻璃盖28 不覆盖位于所述两个或更多个壁的顶表面中的模塑围堤/凹形表面/凹槽22。玻璃盖在壁中的沟槽的边缘处耦接至壁。玻璃盖可通过这些材料的粘附特性粘附到模塑料，或可采用粘合剂或其他接合材料。在各种实施方式中，这些盖可由本领域已知的允许光透过盖的其他透明、半透明材料或其他光学透射材料形成。这些盖的边缘可被成形为提高对模塑料的粘附力，诸如形成斜切边缘或如本文所公开的任何其他形状。还可通过激光切割或使用片锯向这些盖添加凹槽。这些凹槽可在该盖上形成底座状形状以有助于如本文所述的材料之间的更好粘附。
参见图2D，模塑料30被施加到两个或更多个壁20的模塑围堤22中。模塑料30跨越玻璃28的厚度延伸并且可将两个或更多个玻璃盖28牢固地耦接至两个或更多个壁20。模塑料30可在玻璃盖28与壁20之间形成气密或大体气密密封。在各种实施方式中，作为非限制性示例，模塑料可包括粒状树脂、粒状环氧树脂、树脂、环氧树脂、有机硅、丙烯酸、聚酰亚胺、它们的任何组合、或任何其他聚合或可流动材料。作为非限制性示例，可通过分配器、涂布机、模塑工艺或将液体材料分配到围堤中的另一种其他合适方法施加模塑料。在模塑后，接着在所述两个或更多个半导体封装之间的模塑围堤/沟槽22处对这些封装进行切单。可通过本领域已知的各种方法(包括锯切、水射流切割、激光切割等)对这些封装进行切单。
参见图2E，示出了切单的半导体封装32。作为非限制性示例，通过该方法形成的两个或更多个半导体封装可包括PLCC、CLCC、互补金属氧化物半导体(CMOS)图像传感器(CIS)、背照式传感器封装、三维堆叠封装或其他在内腔上方包括覆盖件的封装类型。
参见图3，示出了半导体封装34的另一个实施方式。半导体封装34的实施方式包括衬底36，该衬底具有与之电耦合的管芯38。在各种实施方式中，作为非限制性示例，该衬底可为印刷电路板、陶瓷材料、引线框架或本领域已知的其他合适材料。印刷电路板可由双马来酰亚胺-三嗪(BT)树脂、FR-4等级玻璃增强环氧树脂层压板、FR-5等级玻璃增强环氧树脂层压板以及本文所公开的任何其他材料制成。在各种实施方式中，超过一个管芯可耦接至衬底。在各种实施方式中，一个或多个管芯可以堆叠构型耦接。
如图3所示，管芯38通过两个或更多个引线接合40来以机械的方式和电的方式耦合至衬底36。在各种实施方式中，管芯可在不使用引线接合的情况下耦接至衬底，作为非限制性示例，诸如通过球栅阵列(BGA)或接点栅格阵列 (LGA)互连件耦接至衬底。如图所示，壁42耦接至衬底并耦接至玻璃盖44。在各种实施方式中，壁42围绕衬底36/管芯38的周边延伸。
如图3所示，金属层46跨越衬底36的厚度、壁42及玻璃盖44的厚度耦接。在其他实施方式中，该盖可包括玻璃以外的另一种透明或透光材料，这种材料可为本文所公开的任何材料。透明材料在各种实施方式中可为聚碳酸酯、塑料或本领域已知的其他合适材料。在一些实施方式中，金属层46可包括镍、铜、铝、铬、镍、钛、它们的任何组合、或稳定且低成本的任何其他合适金属。作为非限制性示例，金属层46可形成一个或多个管芯的气密密封。金属层可保护半导体封装34免受电磁干扰(EMI)和静电放电(ESD)的影响。
参见图4A至图4B，示出了用于形成半导体封装的方法的实施方式。参见图4A，提供了半导体封装48。如图所示，半导体封装48包括耦接至衬底的一个管芯。在其他实施方式中，超过一个管芯可耦接至衬底。在其他实施方式中，半导体封装48可包括一个或多个管芯50，该一个或多个管芯耦接至衬底52。作为非限制性示例，衬底可包括由本文所述的任何材料制成的印刷电路板。在其他实施方式中，衬底可包括陶瓷或类似材料。
如图4A所示，管芯通过两个引线接合54来以电和机械的方式耦合至衬底。在一些实施方式中，一个或多个管芯在封装中可呈堆叠构型。在各种实施方式中，一个或多个管芯可通过不涉及引线接合的方法来以电和机械的方式耦合至衬底，作为非限制性示例，这些方法诸如为球栅阵列、接点栅格阵列或本文所公开的任何其他互连类型。
如图4A所示，壁56围绕一个管芯50的周边延伸。该壁可耦接至衬底52 和玻璃盖58。如此前所述，盖58可由另一种合适的光学透明材料制成，这种材料可为本文所公开的任何材料。该壁可如此前所述的那样通过环氧树脂或其他类似材料耦接至衬底，或如此前所述的那样形成在衬底上。玻璃盖58可通过树脂、其他合适材料或通过这些结构的粘附特性耦接至壁56。
参见图4B，金属层60耦接至半导体封装48的壁。可执行C模式扫描声学显微术(CSAM)以在添加金属层之前测试封装的玻璃盖与壁之间的分层。可在施加金属层之前使用玻璃剪切方法测试玻璃对壁的接合力。在各种实施方式中，金属层60可跨越衬底52的厚度、壁56以及玻璃盖58的厚度耦接，从而形成气密密封。作为非限制性示例，可通过以下方法来施加金属层60：等离子溅射、化学气相沉积(CVD)、电镀、化学镀、浸镀或将金属沉积到大体平坦的表面上的任何方法。在各种实施方式中，在添加金属镀层以增加金属层的厚度之前，可使用化学气相沉积机在封装的各侧面上制作晶种金属。作为非限制性示例，该金属可包括以下中的一者：镍、铜、铝、铬、钛、它们的任何组合或另一种稳定金属。金属层的使用可类似地将玻璃接合到壁，并且在各种实施方式中，可形成封装的气密或大体气密密封。金属层还可用于保护半导体封装免受电磁干扰(EMI)和静电放电(ESD)的影响。
用于形成半导体封装的方法的实施方式可包括：提供衬底片材，将两个或更多个壁耦接至衬底片材。两个或更多个壁可位于衬底片材的两个或更多个管芯位置周围。两个或更多个壁可包括在其中的模塑围堤。该方法还可包括：在两个或更多个管芯位置处将两个或更多个管芯耦接至衬底，以及在两个或更多个管芯上方将两个或更多个玻璃盖耦接至两个或更多个壁。该方法可包括：将模塑料施加到两个或更多个壁的模塑围堤中，以及在模塑围堤处对两个或更多个半导体封装进行切单。模塑围堤可将两个或更多个玻璃盖牢固地耦接至两个或更多个壁。
在各种方法实施方式中，模塑料可跨越玻璃的厚度延伸。
衬底片材可包括印刷电路板、陶瓷材料或引线框架。
所述两个或更多个壁可通过以下中的一者形成：传递模塑、压缩模塑或它们的任何组合。
模塑料可包括树脂、环氧树脂、硅、丙烯酸、聚酰亚胺或它们的任何组合。
模塑料可形成气密密封。
模塑料可通过分配器或涂布机中的一者施加。
所述两个或更多个半导体封装可包括塑料无引线芯片载体(PLCC)、陶瓷无引线芯片载体(CLCC)和互补金属氧化物半导体(CMOS)图像传感器(CIS)。
模塑料可为树脂、环氧树脂、硅、丙烯酸、聚酰亚胺或它们的任何组合。
金属层可通过以下中的一者耦接至半导体封装：等离子溅射、化学气相沉积、电镀、化学镀或浸镀。
在以上描述中提到半导体封装的具体实施方式以及实施部件、子部件、方法和子方法的地方，应当显而易见的是，可在不脱离其实质的情况下作出多种修改，并且这些实施方式、实施部件、子部件、方法和子方法可应用于其他半导体封装。

Claims (10)

1.一种半导体封装，包括：
衬底；
管芯，所述管芯电耦合至所述衬底；
壁，所述壁耦接至所述衬底，所述壁围绕在所述管芯的周边延伸，所述壁包括形成于该壁中的模塑围堤；
玻璃盖，所述玻璃盖耦接至所述壁和所述模塑围堤；和
模塑料，所述模塑料耦接到所述模塑围堤中并且跨越所述玻璃盖的厚度。
2.根据权利要求1所述的半导体封装，其中，所述衬底为以下中的一者：印刷电路板、陶瓷材料和引线框架。
3.根据权利要求1所述的半导体封装，其中，所述壁通过以下中的一者形成：传递模塑、压缩模塑和注射模塑。
4.根据权利要求1所述的半导体封装，其中，所述模塑料形成气密密封。
5.根据权利要求1所述的半导体封装，其中，所述半导体封装为以下中的一者：塑料无引线芯片载体PLCC、陶瓷无引线芯片载体CLCC和互补金属氧化物半导体CMOS图像传感器CIS。
6.一种半导体封装，包括：
衬底；
一个或多个管芯，所述一个或多个管芯电耦合至所述衬底；
壁，所述壁耦接至所述衬底和玻璃盖，所述壁围绕所述管芯的周边延伸；
金属层，所述金属层跨越所述衬底的厚度、所述壁以及所述玻璃盖的厚度耦接；
其中，所述金属层形成用于所述一个或多个管芯的气密密封。
7.根据权利要求6所述的半导体封装，其中，所述衬底为以下中的一者：印刷电路板、陶瓷材料和引线框架。
8.根据权利要求6所述的半导体封装，其中，所述金属层包括以下中的一者：镍、铜、铝、铬。
9.根据权利要求6所述的半导体封装，其中，所述金属层保护所述半导体封装免受电磁干扰EMI和静电放电ESD的影响。
10.根据权利要求6所述的半导体封装，其中，所述半导体封装为以下中的一者：塑料无引线芯片载体PLCC、陶瓷无引线芯片载体CLCC和互补金属氧化物半导体CMOS图像传感器CIS。
CN201821861839.4U 2017-12-05 2018-11-12 半导体封装 Expired - Fee Related CN209626199U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035718A (zh) * 2019-12-09 2021-06-25 北京万应科技有限公司 盖板、芯片晶圆封装方法及芯片气密性封装方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11081413B2 (en) * 2018-02-23 2021-08-03 Advanced Semiconductor Engineering, Inc. Semiconductor package with inner and outer cavities
US20200036081A1 (en) * 2018-07-30 2020-01-30 Innolux Corporation Package structure and antenna device using the same
CN110767668B (zh) * 2019-12-30 2020-03-27 杭州美迪凯光电科技股份有限公司 含纳米级表面的clcc封装体盖板、封装体和摄像模组
TWI721837B (zh) * 2020-03-26 2021-03-11 勝麗國際股份有限公司 感測器封裝結構
US11869912B2 (en) * 2020-07-15 2024-01-09 Semiconductor Components Industries, Llc Method for defining a gap height within an image sensor package
KR20220031161A (ko) * 2020-09-04 2022-03-11 삼성전자주식회사 반도체 패키지

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4483896B2 (ja) * 2007-05-16 2010-06-16 ソニー株式会社 半導体装置及びその製造方法
EP2430887A4 (en) * 2009-05-14 2013-10-09 4233999 Canada Inc SYSTEM AND METHOD FOR PROVIDING HIGH RESOLUTION IMAGES USING MONOLITHIC LIGHT EMITTING DIODE ARRAYS
KR20140128415A (ko) * 2012-02-07 2014-11-05 가부시키가이샤 니콘 촬상 유닛 및 촬상 장치
WO2015041602A1 (en) * 2013-09-23 2015-03-26 Heptagon Micro Optics Pte. Ltd. Compact camera module arrangements that facilitate dam-and-fill and similar encapsulation techniques
US9721859B2 (en) * 2015-09-01 2017-08-01 Texas Instruments Incorporated Semi-hermetic semiconductor package
TWI627738B (zh) * 2016-07-12 2018-06-21 勝麗國際股份有限公司 感測器封裝結構
JP7086536B2 (ja) * 2017-07-26 2022-06-20 京セラ株式会社 電子素子実装用基板、電子装置および電子モジュール

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035718A (zh) * 2019-12-09 2021-06-25 北京万应科技有限公司 盖板、芯片晶圆封装方法及芯片气密性封装方法

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