CN106601629A - 保护片服贴于芯片感应面的芯片封装构造 - Google Patents

保护片服贴于芯片感应面的芯片封装构造 Download PDF

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Publication number
CN106601629A
CN106601629A CN201510666987.5A CN201510666987A CN106601629A CN 106601629 A CN106601629 A CN 106601629A CN 201510666987 A CN201510666987 A CN 201510666987A CN 106601629 A CN106601629 A CN 106601629A
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China
Prior art keywords
chip
substrate
crystal layer
sensitive surface
screening glass
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CN201510666987.5A
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CN106601629B (zh
Inventor
苗红燕
华毅
刘志凌
金若虚
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Li Cheng Technology (suzhou) Co Ltd
Powertech Technology Suzhou Ltd
Powertech Technology Inc
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Li Cheng Technology (suzhou) Co Ltd
Powertech Technology Inc
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Priority to CN201510666987.5A priority Critical patent/CN106601629B/zh
Priority to US15/160,711 priority patent/US20170110416A1/en
Publication of CN106601629A publication Critical patent/CN106601629A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
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    • G06V40/12—Fingerprints or palmprints
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    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
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Abstract

本发明公开一种保护片服贴于芯片感应面的芯片封装构造，包含一基板、一设置于基板上的主芯片、一覆盖主芯片的黏性保护片以及一密封主芯片的封装体。主芯片具有一远离基板的芯片感应面以及一电性连接至基板的连接端点。黏性保护片主要由一取放片与一黏晶层所组成，封装体完全密封黏晶层并且不覆盖取放片的外表面。黏性保护片以取放方式服贴地黏附于芯片感应面，以使黏晶层黏附于芯片感应面并维持固定的黏贴间隙，并且取放片的外表面平行于芯片感应面而不受到基板的水平误差影响，避免了感应芯片加装保护片的后感应失真的问题。

Description

保护片服贴于芯片感应面的芯片封装构造
技术领域
本发明有关于感应芯片封装领域，特别有关于一种保护片服贴于芯片感应面的芯片封装构造，可应用于指纹识别芯片的加盖封装产品。
背景技术
半导体芯片作为微电子装置的核心，依照功能的不同，主要区别以下几大类别：集成电路芯片(IC chip)、发光二极管芯片(LED chip)、感应芯片(sensor chip)、太阳能电池芯片(solar cell chip)与微机电芯片(MEMS chip)。其中，感应芯片又可进一步区分为指纹识别芯片、影像感应芯片、压力感应芯片等。不同功能的芯片则需要对应的封装构造，应符合保护芯片、传递芯片电性信号至外部的需求并且不影响芯片功能。
现有指纹识别芯片的封装构造中，芯片的感应表面必须为裸露在封装构造外，以供手指触压芯片感应表面。然而裸露的芯片感应表面易受污染或破坏，导致产品故障。
美国发明专利编号US 8,803,258 B2中，Gozzini等人揭示一种包括电容透镜的指纹识别器及其相关方法 (Finger sensor including capacitive lens and associated methods)，一种指纹识别器包含一安装基板、一承载于安装基板上并且具有电场极化指纹识别组件数组的集成电路芯片、以及一耦接安装基板与IC芯片的电连接件。另外，指纹识别装置包括被附接在指纹识别组件数组之上的保护板，该保护板定义为一供使用于电场极化指纹识别组件数组上的电容透镜(capacitive lens)。此一指纹识别装置还包括一邻近于安装基板与IC芯片且位在电连接件周围的密封材料。保护板在芯片短边的宽度必须较大，以连接焊料；保护板在芯片长边的长度必须较小，以避免压触打线连接芯片焊垫的焊线，因此保护板未能服贴地黏附于芯片感应面。通常加装保护板的方法均是先以一母片压贴至芯片上，以基板的水平面作为保护板母片的安装水平，当芯片与基板之间的黏着胶固化之后，芯片的安装水平误差会影响感应芯片与保护板之间的间隙，使得芯片感应灵敏度降低，故容易发生感应芯片加装保护片之后感应失真的问题。
发明内容
为了解决上述的问题，本发明的主要目的在于提供一种保护片服贴于芯片感应面的芯片封装构造，避免了感应芯片加装保护片之后易发生感应失真的问题，并提高制造良品率与生产效率。
本发明的次一目的在于提供一种保护片服贴于芯片感应面的芯片封装构造，当应用于指纹识别芯片与其它芯片的多芯片结构时，可符合芯片尺寸封装的要求，并且指纹识别芯片的底部不需要开空腔，封装方式简单，因此避免额外制作费用并维持了指纹识别芯片的本身结构强度。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。本发明提高一种保护片服贴于芯片感应面的芯片封装构造，包括一基板、一主芯片、一黏性保护片以及一封装体。该主芯片设置于该基板上，该主芯片具有一芯片感应面以及一连接端点，该芯片感应面相对远离该基板，该连接端点电性连接至该基板。该黏性保护片主要由一取放片与一第一黏晶层所组成，该取放片具有一内表面与一外表面，该第一黏晶层覆盖于该取放片的该内表面，该黏性保护片以取放方式服贴地黏附于该芯片感应面，以使该第一黏晶层黏附于该芯片感应面并维持固定的黏贴间隙，并且该取放片的该外表面平行于该芯片感应面而不受到该基板的水平误差影响。该封装体形成于该基板上，以密封该主芯片，该封装体具有一在该基板上的密封高度，其大于该主芯片的厚度且不超过该取放片的该外表面，以使该封装体完全密封该第一黏晶层并且不覆盖该取放片的该外表面。借此，该取放片的外表面与该主芯片的该芯片感应面两者平行度为良好，避免了感应芯片加装保护片之后感应失真的问题。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
在前述封装构造中，可另包括一第二黏晶层，形成于该主芯片与该基板之间，该第二黏晶层的覆盖面积可小于该第一黏晶层的覆盖面积，该主芯片可不考虑相对于该基板的水平度，如同一般IC芯片的安装方式将具有该芯片感应面的该主芯片安装在该基板上。
在前述封装构造中，可另包括至少一次芯片，设置于该基板上并且位于该主芯片与该基板之间，该第二黏晶层的厚度可大于该第一黏晶层的厚度，以使该第二黏晶层密封该次芯片，因此该主芯片可不服贴于该基板，该主芯片相对于该基板的水平偏差不影响该取放片的外表面与该主芯片的该芯片感应面两者平行度，避免了加装保护片与隐藏次芯片之后感应度失真的问题。
在前述封装构造中，还另包括至少一被动组件，设置于该基板上并且位于该主芯片与该基板之间，该第二黏晶层可更密封该被动组件，因此更多的小组件可嵌埋在该主芯片下方，整体封装构造的表面覆盖面积可进一步缩小。
在前述封装构造中，该第一黏晶层全面覆盖于该取放片的该内表面，并且该取放片的一第一尺寸较佳地大于该主芯片的一第二尺寸且小于该基板的一第三尺寸，以使该封装体局部包覆该取放片的周边，故该第一黏晶层被该封装体完全密封，以避免黏晶材料的外露。
在前述封装构造中，还另包括一金属盖，可罩合于该封装体，该金属盖较佳地具有一开孔，以显露该取放片的该外表面，因此可形成电路回路，使芯片指纹识别功能得以实现，另外具有静电保护功能，显露出该取放片的该外表面可供手指压触感应或是接受外界信息。
在前述封装构造中，还另包括一电路板，该基板与该金属盖可个别接合至该电路板，因此该金属盖的接合应力不直接作用于该封装体与该黏性保护片。
在前述封装构造中，该连接端点为一位于该芯片感应面的周边焊垫，并以一焊线连接该连接端点至该基板，该焊线在该主芯片上方的线弧部位较佳地嵌埋于该第一黏晶层中。因此，该第一黏晶层能紧密贴合该芯片感应面并且该连接端点的位置可不特殊的制作以形成于主芯片的凹陷区。
在前述封装构造中，该连接端点设于该主芯片相对于该芯片感应面的一下表面，该连接端点还包含至少一凸块，因可借由覆晶方式使得该主芯片经由导电性凸块电性连接至该基板，并且该第一黏晶层可更薄化设计。
在前述封装构造中，该芯片感应面包含一指纹识别区，且该第一黏晶层较佳地全面覆盖于该指纹识别区。因此，该第一黏晶层紧密贴合该指纹识别区，并加强感应灵敏度。
本发明具有的优点在于：
借由上述的技术手段，本发明利用该黏性保护片以取放方式服贴地黏附于该芯片感应面，以使该第一黏晶层黏附于该芯片感应面并维持固定的黏贴间隙，并且该取放片的该外表面平行于该芯片感应面而不受到该基板的水平误差影响等技术手段，避免了感应芯片加装保护片之后感应失真的问题，提高合格率与生产效率。
附图说明
图1：依据本发明的一模拟实施例，一种加装保护片的感应芯片封装构造的截面示意图。
图2：依据本发明的第一具体实施例，一种保护片服贴于芯片感应面的芯片封装构造的截面示意图。
图3A至图3I：依据本发明的一具体实施例，在制造上述保护片服贴于芯片感应面的芯片封装构造的各制程步骤中的组件截面示意图。
图4：依据本发明的第二具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造的截面示意图。
图5：依据本发明的第三具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造的截面示意图。
图6：依据本发明的第四具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造的截面示意图。
图7A至图7G：依据本发明的第四具体实施例，在制造上述保护片服贴于芯片感应面的芯片封装构造的各制程步骤中的组件截面示意图。
图8：依据本发明的第五具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造的截面示意图。
图9：依据本发明的第六具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造的截面示意图。
图10A至图10F：依据本发明的第六具体实施例，在制造上述保护片服贴于芯片感应面的芯片封装构造的各制程步骤中的组件截面示意图。
图11：依据本发明的第七具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造的截面示意图。
图中：
L1 取放片的第一尺寸；L2 主芯片的第二尺寸；L3 基板的第三尺寸；
10 切割装置；100 芯片封装构造；110 基板； 111 外接垫；
112 内接指； 120 主芯片；121 芯片感应面； 122 连接端点；
123 指纹识别区； 124 焊线；130 黏性保护片； 131 取放片；
132 第一黏晶层； 133 内表面；134 外表面；
140 封装体； 141 密封高度； 150 第二黏晶层 ；
160 次芯片； 161 第三黏晶层；162 焊线；
200 芯片封装构造；270 金属盖； 271 开孔；280 电路板； 281 接合垫；
300 芯片封装构造； 361 被动组件；400 芯片封装构造；
450 第二黏晶层； 500 芯片封装构造； 550 第二黏晶层；
570 金属盖； 571 开孔；580 电路板； 581 接合垫；
600 芯片封装构造；622 连接端点； 624 下表面；
700 芯片封装构造；770 金属盖； 771 开孔；780 电路板；
781 接合垫；800 感应芯片封装构造；810 基板； 811 外接垫；
820 主芯片； 821 芯片感应面；822 连接端点； 823 指纹识别区；824 焊线 825 晶背腔穴；830 保护片； 832 第一黏晶层；
840 封装体； 850 第二黏晶层；860 次芯片。
具体实施方式
下面结合具体实施例对本发明作进一步说明，以使本领域的技术人员可以更好的理解本发明并能予以实施，但所举实施例不作为对本发明的限定。
在本发明的模拟实施例中，尝试提供一种加装保护片的感应芯片封装构造800，举例说明于图1的截面示意图。该感应芯片封装构造800包含一基板810、一主芯片820、一保护片830以及一封装体840。该基板810为一线路载板并具有多个外接垫811，该多个外接垫811用以对外接合一电路板。在封装制程中，该基板810以多个构成于一母片的方式被提供。
多个该主芯片820设置于该基板810的母片上，该主芯片820可为指纹识别芯片。该主芯片820具有一芯片感应面821以及一连接端点822，该芯片感应面821可包含一指纹识别区823。该芯片感应面821相对远离该基板810，该连接端点822电性连接至该基板810。该芯片感应面821为感应外界信息的表面。该连接端点822可为连接线路的端点，其中该主芯片820有一凹陷缺口，该连接端点822设置于该缺口。并以一打线形成的焊线824连接该连接端点822至该基板810。
该保护片830以多个构成于一母片的方式贴附于复数个主芯片820上，该保护片830可为如玻璃的透明材质，一第一黏晶层832黏合该保护片830至该主芯片820的芯片感应面821并覆盖于该指纹识别区823。以模封方式，使该封装体840形成于该基板810上，以密封该主芯片820的周边与该焊线824。最后，使用单体化切割制程，同时切断该基板810的母片、该封装体840与该保护片830的母片，以制得如图1所示的感应芯片封装构造800，其中该封装体840未完全密封该第一黏晶层832。
由于该保护片830以水平于该基板810的方式被安装在该主芯片820上。当该主芯片820与该基板810之间存在着水平误差，使该保护片830与该芯片感应面821之间亦存在着水平误差，使得该第一黏晶层832黏附于该芯片感应面821无法维持固定的黏贴间隙，故加装该保护片830之后便产生了感应度失真的问题。
为了尽可能消弭该保护片830与该芯片感应面821之间的水平误差。该芯片封装构造800必须使用极薄且均厚的一第二黏晶层850，如芯片贴附材料(Die Attach Material, DAM)。该第二黏晶层850预先形成于该主芯片820并黏着该主芯片820与该基板810。
此外，当该芯片封装构造800在该主芯片820与该基板810之间需要安装至少一次芯片860时，例如ASIC半导体芯片，该主芯片820必须在晶圆等级先制作出一晶背腔穴825，以容纳该次芯片860。因此，要制作具有该晶背腔穴825与上述图案化第二黏晶层850的该主芯片820将会有困难度并产生高制造成本。
依据本发明的第一具体实施例，一种保护片服贴于芯片感应面的芯片封装构造100举例说明于图2的截面示意图以及图3A至3I的各制程步骤中的组件截面示意图。该芯片封装构造100包含一基板110、一主芯片120、一黏性保护片130以及一封装体140。
该基板110具有多个在其下表面的外接垫111以及一在其上表面的内接指112，该些外接垫111用以对外电性连接，该内接指112用以对封装内部芯片的电性连接。该基板110可为一线路载板，例如微型印刷电路板、软性电路板或陶瓷线路基板。该基板110的厚度约为200微米。
该主芯片120设置于该基板110上，该主芯片120可为半导体芯片，以指纹识别芯片为最佳，亦可为影像感应芯片或其它适用本发明相同封装的芯片。所称的主芯片表示该主芯片120为该芯片封装构造100中尺寸最大的芯片，或者是唯一的感应芯片。该主芯片120具有一芯片感应面121以及一连接端点122。该芯片感应面121为感应外界信息的芯片表面，该连接端点122为可沟通该芯片感应面121的电性端点，该芯片感应面121相对远离该基板，该连接端点122电性连接至该基板110。该主芯片120的厚度约为250微米。
该黏性保护片130主要由一取放片131与一第一黏晶层132所组成；换言之，该取放片131与该第一黏晶层132构成该黏性保护片130的大部分或全部。该取放片131可为不影响感应传导的均质硬性材料，例如玻璃、蓝宝石或微晶锆。该第一黏晶层132可为不影响感应传导的可固化均质黏着材料，例如未混杂间隔物的环氧树脂(epoxy without spacer)或是芯片贴附材料(Die Attach Material, DAM)。该第一黏晶层132的厚度小于该取放片131的厚度二分之一以上；具体地，该第一黏晶层132的厚度约为20微米，该取放片131的厚度约为200微米。该取放片131具有一内表面133与一外表面134，该第一黏晶层132覆盖于该取放片131的该内表面133，该第一黏晶层132具有一适当厚度以包覆内嵌其中的连接线。该黏性保护片130完全覆盖在该主芯片120的上方，该黏性保护片130的该外表面134的面积大于该主芯片120的该芯片感应面121的面积，但小于该基板110的上表面的面积。该黏性保护片130以取放方式服贴地黏附于该芯片感应面121，以使该第一黏晶层132黏附于该芯片感应面121并维持固定的黏贴间隙，即在安装该黏性保护片130于该主芯片120上之后，该第一黏晶层132在固化之前保持在一固定厚度(约20微米)，因此可以自动化机械操作该黏性保护片130的取放操作。并且，该取放片131的该外表面134平行于该芯片感应面121而不受到该基板110的水平误差影响。在此所称服贴地黏附指该芯片感应面121的全部被该黏性保护片130覆盖而沾附有该第一黏晶层132，并且该芯片感应面121与该取放片131的该外表面134为水平，使得该第一黏晶层132在固化后为一致的厚度(约20微米)。在本实施例中，当该连接端点122形成于该芯片感应面121，该第一黏晶层132更覆盖该连接端点122。
该封装体140形成于该基板110上，该封装体140可为用于密封该主芯片120周边的电绝缘性材料，以密封该主芯片120，例如模封环氧化合物(EMC)。该封装体140具有一在该基板110上的密封高度141，其大于该主芯片120的厚度且不超过该取放片131的该外表面134，以使该封装体140完全密封该第一黏晶层132并且不覆盖该取放片131的该外表面134。该密封高度141约为450-500微米。借此，该取放片131的该外表面134能紧密服贴于该芯片感应面121，避免了感应芯片加装黏性保护片130之后感应失真的问题。
更具体地，该芯片封装构造100还包含一第二黏晶层150，形成于该主芯片120与该基板110之间，该第二黏晶层150的覆盖面积可小于该第一黏晶层132的覆盖面积，该第二黏晶层150可为用于黏合半导体芯片的黏着物质，如环氧树脂或是包覆小芯片的包晶胶层(Film-On-Die adhesive, FOD)，所称的包晶胶层在厚度上大于覆线胶层，且厚度的控制准度低于覆线胶层，而在胶包覆效果上包晶胶层优于覆线胶层。该第二黏晶层150的厚度约为140微米。该主芯片120可不考虑相对于该基板110的水平度，如同一般IC芯片的安装方式将具有该芯片感应面121的该主芯片120安装在该基板110上。
在本实施例中，该芯片封装构造100另包含至少一次芯片160，该次芯片160黏合于该基板110上并且位于该主芯片120与该基板110之间，该第二黏晶层150的厚度可大于该第一黏晶层132的厚度，以使该第二黏晶层150密封该次芯片160。故该次芯片160能完全被该第二黏晶层150包覆密封。该次芯片160可为特殊应用模拟芯片(ASIC chip)，该次芯片160利用一第三黏晶层161黏附于该基板110并以至少一焊线162电性连接至该基板110，该焊线162可为打线连接的金属细线，如金线。该第二黏晶层150更密封该第三黏晶层161与该焊线162。因此，该主芯片120可不服贴于该基板110，该主芯片120相对于该基板110的水平偏差不影响该取放片131的外表面134与该主芯片120的该芯片感应面121两者平行度，避免了加装保护片与隐藏次芯片之后感应度失真的问题。
在本实施例中，该连接端点122为一位于该芯片感应面121的周边焊垫，并以一焊线124连接该连接端点122至该基板110的该内接指112。该焊线124可为金属传导线，如金线。在本实施例中，该焊线124在该主芯片120上方的线弧部位较佳地嵌埋于该第一黏晶层132中，因此，该第一黏晶层132能紧密贴合该芯片感应面121，并且该连接端点122的位置可不特殊的制作以形成于主芯片的凹陷区。
该芯片感应面121包含一指纹识别区123，该指纹识别区123包含用以接受外界信息的识别组件数组(图中未绘出)，且该第一黏晶层132较佳地全面覆盖于该指纹识别区123。因此，该第一黏晶层132紧密贴合该指纹识别区123，并加强感应灵敏度。
配合参阅图3A至图3I，以下进一步说明该芯片封装构造100的制造方法。如图3A所示，执行一基板110的提供步骤，固定该基板110于一工作平台上，该基板110具有该些外接垫111以及该内接指112在不同表面。之后，如图3B所示，执行一次芯片的安装作业，将该次芯片160以该第三黏晶层161黏合于该基板110上。之后，如图3C所示，打线形成该焊线162，使得该焊线162电性连接该次芯片160与该基板110。之后，如图3D所示，执行该主芯片120的安装作业，以该第二黏晶层150密封包覆该次芯片160与该焊线162并黏着该主芯片120至该基板110上，该主芯片120的该芯片感应面121包含该连接端点122与该指纹识别区123，该芯片感应面121远离该基板110，随后并使该第二黏晶层150为固化。之后，如图3E所示，打线形成该焊线124，并使该焊线124电性连接该主芯片120的该连接端点122与该基板110的该内接指112。之后，如图3F所示，执行一保护片取放作业，将该黏性保护片130顺从地贴附于该主芯片120上，该黏性保护片130包含有该取放片131与该第一黏晶层132，以该第一黏晶层132黏附于该芯片感应面121并维持固定的黏贴间隙，并且该焊线124在该主芯片120上方的线弧部位可嵌埋于该第一黏晶层132中。之后，如图3G所示，执行一模封步骤，使该封装体140形成于该基板110上，以密封该主芯片120与该第一黏晶层132，该封装体140具有一在该基板上的密封高度141，其大于该主芯片120的厚度且不超过该取放片131的该外表面134，以使该封装体140完全密封该第一黏晶层132并且不覆盖该取放片131的该外表面134。之后，进行一封装单体化分离步骤，如图3H所示，该芯片封装构造100的该基板110的下表面面向一雷射切割装置10，该雷射切割装置10切穿该基板110与该封装体140的部分厚度，再进一步切穿该封装体140，不会切到该取放片131与该第一黏晶层132，因此可降低切割应力，进而避免盖附于该主芯片120的硬质保护片的松动。图3I所示切割多个分离的该芯片封装构造100。在上述封装单体化分离步骤未切割到该黏性保护片130的该取放片131，因此填满该第一黏晶层132的黏贴间隙仍可维持固定且黏贴间隙不会有裂痕。
依据本发明的第二具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造200举例说明于图4的截面示意图。除了多了金属盖270与电路板280等主组件，该芯片封装构造200大致与第一体实施例的芯片封装构造100相同，其中对应于第一具体实施例相同名称与功能的组件以第一具体实施例的组件图号表示，并且不再赘述其细部相同结构。该芯片封装构造200包含一基板110、一主芯片120、一黏性保护片130以及一封装体140。
该主芯片120设置于该基板110上，该主芯片120可为指纹识别芯片，该基板110有多个外接垫111以及一内接指112。该主芯片120具有一芯片感应面121以及一连接端点122，该芯片感应面121相对远离该基板110，该连接端点122可利用该焊线124电性连接至该基板110。该黏性保护片130主要由一取放片131与一第一黏晶层132所组成，该取放片131具有一内表面133与一外表面134，该第一黏晶层132覆盖于该取放片131的该内表面133，该黏性保护片130以取放方式服贴地黏附于该芯片感应面121，以使该第一黏晶层132黏附于该芯片感应面121并维持固定的黏贴间隙，并且该取放片131的该外表面134平行于该芯片感应面121而不受到该基板110的水平误差影响。该焊线124在该主芯片120上方的线弧部位可嵌埋于该第一黏晶层132中。此外，该封装体140形成于该基板110上，以密封该主芯片120，该封装体140具有一在该基板110上的密封高度141，其大于该主芯片120的厚度且不超过该取放片131的该外表面134，以使该封装体140完全密封该第一黏晶层132并且不覆盖该取放片131的该外表面134。该芯片封装构造200另包含一第二黏晶层150，形成于该主芯片120与该基板110之间，该第二黏晶层150的覆盖面积可小于该第一黏晶层132的覆盖面积。至少一次芯片160黏合于该基板110上并且位于该主芯片120与该基板110之间，该第二黏晶层150的厚度可大于该第一黏晶层132的厚度，以使该第二黏晶层150密封该次芯片160。
在本实施例中，该芯片封装构造200另包含一金属盖270，可罩合于该封装体140，该金属盖270较佳地具有一开孔271，以显露该取放片131的该外表面134，故可形成电路回路，使芯片指纹识别功能得以实现，另外具有静电保护功能，并且由该开孔271显露出该取放片131的该外表面134可供手指压触感应或是接受外界信息。该芯片封装构造200另包含一电路板280，该基板110与该金属盖270可个别接合至该电路板280，故该金属盖270的接合应力不直接作用于该封装体140与该黏性保护片130。其中，该基板110的该些外接垫111可借由焊料接合至该电路板280的多个接合垫281。
该芯片感应面121包含一指纹识别区123，且该第一黏晶层132较佳地全面覆盖于该指纹识别区123。该指纹识别区123通过该黏性保护片130而对准在该金属盖270的该开孔271中。
依据本发明的第三具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造300举例说明于图5的截面示意图。除了多了被动组件361等主组件，该芯片封装构造300大致与第一体实施例的芯片封装构造100相同，其中对应于第一具体实施例相同名称与功能的组件以第一具体实施例的组件图号表示，并且不再赘述其细部相同结构。该芯片封装构造300包含一基板110、一主芯片120、一黏性保护片130以及一封装体140。该主芯片120设置于该基板110上，该主芯片120具有一芯片感应面121以及一连接端点122。一焊线124连接该连接端点122至该基板110的该内接指112。该黏性保护片130主要由一取放片131与一第一黏晶层132所组成，该黏性保护片130以取放方式服贴地黏附于该芯片感应面121，以使该第一黏晶层132黏附于该芯片感应面121并维持固定的黏贴间隙，并且该取放片131的该外表面134平行于该芯片感应面121而不受到该基板110的水平误差影响。该焊线124在该主芯片120上方的线弧部位较佳地嵌埋于该第一黏晶层132中。该封装体140形成于该基板110上，该封装体140具有一在该基板110上的密封高度141，其大于该主芯片120的厚度且不超过该取放片131的该外表面134，以使该封装体140完全密封该第一黏晶层132并且不覆盖该取放片131的该外表面134。此外，该芯片感应面121可包含一指纹识别区123，且该第一黏晶层132较佳地全面覆盖于该指纹识别区123。
该芯片封装构造300另包含一第二黏晶层150，形成于该主芯片120与该基板110之间，该第二黏晶层150的覆盖面积可小于该第一黏晶层132的覆盖面积。至少一次芯片160黏合于该基板110上并且位于该主芯片120与该基板110之间，该第二黏晶层150的厚度可大于该第一黏晶层132的厚度，以使该第二黏晶层150密封该次芯片160。该次芯片160利用一第三黏晶层161黏附于该基板110并以至少一焊线162电性连接至该基板110。该第二黏晶层150更密封该第三黏晶层161与该焊线162。在本实施例中，该芯片封装构造300另包含至少一被动组件361，其设置于该基板110上并且位于该主芯片120与该基板110之间，该第二黏晶层150可更密封该被动组件361。该被动组件361为该次芯片160用以电性连接至该基板110的小型保护组件，如电容、电感或电阻。更多比该主芯片120更小的组件可嵌埋在该主芯片120下方，因此整体封装构造的表面覆盖面积(footprint)可进一步缩小。
依据本发明的第四具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造400举例说明于图6的截面示意图以及图7A至图7G的各制程步骤中的组件截面示意图。除了由多芯片封装至单芯片封装的变化，该芯片封装构造400大致与第一体实施例的芯片封装构造100相同，其中对应于第一具体实施例相同名称与功能的组件以第一具体实施例的组件图号表示，并且不再赘述其细部相同结构。该芯片封装构造400包含一基板110、一设置于该基板110上的主芯片120、一以取放方式服贴地黏附于该主芯片120的黏性保护片130以及一形成于该基板110上的封装体140。该主芯片120的该芯片感应面121可包含一指纹识别区123，且该第一黏晶层132较佳地全面覆盖于该指纹识别区123。
在本实施例中，该芯片封装构造400可另包含一第二黏晶层450，形成于该主芯片120与该基板110之间，该第二黏晶层450的覆盖面积可小于该第一黏晶层132的覆盖面积。因该第二黏晶层450不需要包覆次芯片，使其厚度可降低，该第二黏晶层450可为用于单纯黏固芯片的材料，例如环氧树脂、芯片贴附膜（DAF）或是芯片贴附材料(Die Attach Material, DAM)。
在本实施例中，该第一黏晶层132全面覆盖于该取放片131的该内表面133，并且该取放片131的一第一尺寸L1较佳地大于该主芯片120的一第二尺寸L2且小于该基板110的一第三尺寸L3，以使该封装体140局部包覆该取放片131的周边，故该第一黏晶层132被该封装体140完全密封，以避免黏晶材料的外露。
配合参阅图7A至图7G，以下进一步说明该芯片封装构造400的制造方法。如图7A所示，首先，置放该基板110于作业平台，该基板110具有该些外接垫111以及该内接指112。之后，如图7B所示，将该主芯片120以该第二黏晶层450黏合于该基板110上，该主芯片120的该芯片感应面121包含该连接端点122与该指纹识别区123，该芯片感应面121远离该基板110，随后并使该第二黏晶层450为固化。之后，如图7C所示，打线形成该焊线124，使得该焊线124电性连接该主芯片120的该连接端点122与该基板110的该内接指112。之后，如图7D所示，执行一保护片取放作业，将该黏性保护片130顺从地贴附于该主芯片120上，该黏性保护片130包含有该取放片131与该第一黏晶层132，以该第一黏晶层132黏附于该芯片感应面121并维持固定的黏贴间隙，并且该焊线124在该主芯片120上方的线弧部位可嵌埋于该第一黏晶层132中。之后，如图7E所示，执行一模封步骤，使该封装体140形成于该基板110上，以密封该主芯片120与该第一黏晶层132。该封装体140具有一在该基板110上的密封高度141，其大于该主芯片120的厚度且不超过该取放片131的该外表面134，以使该封装体140完全密封该第一黏晶层132并且不覆盖该取放片131的该外表面134。如图7F所示，进行一封装单体化分离步骤，利用一雷射切割装置10可先切穿该基板110，再切穿该封装体140，最终构成单体化分离的芯片封装构造400（如图7G所示）。
依据本发明的第五具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造500举例说明于图8的截面示意图。除了由多芯片封装至单芯片封装的变化以及多了金属盖270与电路板280等主组件，该芯片封装构造500大致与第一体实施例的芯片封装构造100相同，其中对应于第一具体实施例相同名称与功能的组件以第一具体实施例的组件图号表示，并且不再赘述其细部相同结构。该芯片封装构造500为一基板110、一设置于该基板110上的主芯片120、一以取放方式服贴地黏附于该主芯片120的黏性保护片130以及一形成于该基板110上的封装体140。该芯片感应面121可包含一指纹识别区123，且该第一黏晶层132较佳地全面覆盖于该指纹识别区123。
该芯片封装构造500可另包含一第二黏晶层550，如芯片贴附材料(Die Attach Material, DAM)，形成于该主芯片120与该基板110之间，该第二黏晶层550的覆盖面积可小于该第一黏晶层132的覆盖面积。
在本实施例中，该芯片封装构造500可另包含一金属盖570，可罩合于该封装体140，该金属盖570较佳地具有一开孔571，以显露该取放片131的该外表面134。该芯片封装构造500可另包含一电路板580，该基板110与该金属盖270可个别接合至该电路板580，故该金属盖570的接合应力不直接作用于该封装体140与该黏性保护片130。
依据本发明的第六具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造600举例说明于图9的截面示意图以及图10A至图10F的各制程步骤中的组件截面示意图。除了由多芯片封装至单芯片封装以及主芯片打线连接至覆晶接合的变化，该芯片封装构造600大致与第一体实施例的芯片封装构造100相同，其中对应于第一具体实施例相同名称与功能的组件以第一具体实施例的组件图号表示，并且不再赘述其细部相同结构。该芯片封装构造600包含一基板110、一设置于该基板110上的主芯片120、一以取放方式服贴地黏附于该主芯片120的黏性保护片130以及一形成于该基板110上的封装体140。该主芯片120的该芯片感应面121可包含一指纹识别区123，且该第一黏晶层132较佳地全面覆盖于该指纹识别区123。
该主芯片120具有一芯片感应面121以及多个连接端点622，该芯片感应面121相对远离该基板，该多个连接端点622电性连接至该基板110。该黏性保护片130主要由一取放片131与一第一黏晶层132所组成，该取放片131具有一内表面133与一外表面134，该第一黏晶层132覆盖于该取放片131的该内表面133。该封装体140具有一在该基板110上的密封高度141，其大于该主芯片120的厚度且不超过该取放片131的该外表面134，以使该封装体140完全密封该第一黏晶层132并且不覆盖该取放片131的该外表面134。
在本实施例中，该多个连接端点622设于该主芯片120相对于该芯片感应面121的一下表面624，该多个连接端点622可包含至少一凸块，故可借由覆晶方式使得该主芯片120经由导电性凸块电性连接至该基板110，并且该第一黏晶层132可更薄化设计。
配合参阅图10A至图10F，以下进一步说明该芯片封装构造600的制造方法。如图10图所示，首先，固定该基板110于一工作平台上，该基板110具有该些外接垫111。如第10B图所示，之后，执行一覆晶接合作业，将该主芯片120接合于该基板110上，其利用位在该主芯片120的下表面624的该连接端点622连接于该基板110，该主芯片120的该芯片感应面121包含该指纹识别区123，可利用硅穿孔或晶侧线路连接位在不同表面的该指纹识别区123与该连接端点122，该芯片感应面121远离该基板110。如图10C所示，之后，执行一保护片取放作业，将该黏性保护片130顺从地贴附于该主芯片120上，该黏性保护片130包含有该取放片131与该第一黏晶层132。如图10D所示，之后，以模封方式将该封装体140形成于该基板110上，以密封该主芯片120与该第一黏晶层132，该封装体140具有一在该基板上的密封高度141，其大于该主芯片120的厚度且不超过该取放片131的该外表面134，以使该封装体140完全密封该第一黏晶层132并且不覆盖该取放片131的该外表面134。如图10E所示，最后进行一封装单体化分离步骤，利用一雷射切割装置10可先切入该基板110再进一步切穿该封装体140，最终构成多个单体化分离的芯片封装构造600（如图10F所示）。
依据本发明的第七具体实施例，另一种保护片服贴于芯片感应面的芯片封装构造700举例说明于图11的截面示意图，除了多了金属盖770与电路板780等主组件，该芯片封装构造700大致与第六体实施例的芯片封装构造600相同，其中对应于第一具体实施例相同名称与功能的组件以第一具体实施例的组件图号表示，并且不再赘述其细部相同结构。。一种保护片服贴于芯片感应面的芯片封装构造700包含一基板110、一设置于该基板110上的主芯片120、一以取放方式服贴地黏附于该主芯片120的黏性保护片130以及一形成于该基板110上的封装体140。
该主芯片120设置于该基板110上，该主芯片120具有一芯片感应面121以及多个连接端点622在不同表面。该芯片感应面121相对远离该基板，该多个连接端点622可为凸块，利用覆晶接合方式电性连接至该基板110。该黏性保护片130主要由一取放片131与一第一黏晶层132所组成。该黏性保护片130以取放方式服贴地黏附于该芯片感应面121，以使该第一黏晶层132黏附于该芯片感应面121并维持固定的黏贴间隙，并且该取放片131的该外表面134平行于该芯片感应面121而不受到该基板110的水平误差影响。该芯片感应面121包含一指纹识别区123，且该第一黏晶层132较佳地全面覆盖于该指纹识别区123。该封装体140具有一在该基板110上的密封高度141，其大于该主芯片120的厚度且不超过该取放片131的该外表面134，以使该封装体140完全密封该第一黏晶层132并且不覆盖该取放片131的该外表面134。
在本实施例中，该芯片封装构造700可另包含一金属盖770，可罩合于该封装体140，该金属盖770较佳地具有一开孔771，以显露该取放片131的该外表面134。该芯片封装构造700可另包含一电路板780，该基板110与该金属盖770可个别接合至该电路板780，故该金属盖770的接合应力不直接作用于该封装体140与该黏性保护片130。该指纹识别区123通过该黏性保护片130对准于该开孔771中。
综上所述，本发明的第一至第七具体实施例揭示一种保护片服贴于芯片感应面的芯片封装构造，是为了改善加装保护片而导致保护片与主芯片之间的水平度服贴不完整的问题，并且主芯片不需要特殊制作侧边缺口与晶背腔穴等构造，故可降低制作成本。整体芯片封装构造中或可整合次芯片、被动组件、金属盖与电路板，主芯片的电性连接方法除了打线连接，亦可覆晶接合。
以上所述实施例仅是为充分说明本发明而所举的较佳的实施例，本发明的保护范围不限于此。本技术领域的技术人员在本发明基础上所作的等同替代或变换，均在本发明的保护范围之内。本发明的保护范围以权利要求书为准。

Claims (10)

1.一种保护片服贴于芯片感应面的芯片封装构造，其特征在于，包括：
一基板；
一主芯片，设置于该基板上，该主芯片具有一芯片感应面以及一连接端点，该芯片感应面相对远离该基板，该连接端点电性连接至该基板；
一黏性保护片，主要由一取放片与一第一黏晶层所组成，该取放片具有一内表面与一外表面，该第一黏晶层覆盖于该取放片的该内表面，该黏性保护片以取放方式服贴地黏附于该芯片感应面，以使该第一黏晶层黏附于该芯片感应面并维持固定的黏贴间隙，并且该取放片的该外表面平行于该芯片感应面而不受到该基板的水平误差影响；以及
一封装体，形成于该基板上，以密封该主芯片，该封装体具有一在该基板上的密封高度，其大于该主芯片的厚度且不超过该取放片的该外表面，以使该封装体完全密封该第一黏晶层并且不覆盖该取放片的该外表面。
2.根据权利要求1所述的保护片服贴于芯片感应面的芯片封装构造，其特征在于，还包括一第二黏晶层，形成于该主芯片与该基板之间，该第二黏晶层的覆盖面积小于该第一黏晶层的覆盖面积。
3.根据权利要求2所述的保护片服贴于芯片感应面的芯片封装构造，其特征在于，还包括至少一次芯片，设置于该基板上并且位于该主芯片与该基板之间，该第二黏晶层的厚度大于该第一黏晶层的厚度，以使该第二黏晶层密封该次芯片。
4.根据权利要求3所述的保护片服贴于芯片感应面的芯片封装构造，其特征在于，还包括至少一被动组件，设置于该基板上并且位于该主芯片与该基板之间，该第二黏晶层密封该被动组件。
5.根据权利要求1所述的保护片服贴于芯片感应面的芯片封装构造，其特征在于，其中该第一黏晶层全面覆盖于该取放片的该内表面，并且该取放片的一第一尺寸大于该主芯片的一第二尺寸且小于该基板的一第三尺寸，以使该封装体局部包覆该取放片的周边。
6.根据权利要求1所述的保护片服贴于芯片感应面的芯片封装构造，其特征在于，还包括一金属盖，罩合于该封装体，该金属盖具有一开孔，以显露该取放片的该外表面。
7.根据权利要求6所述的保护片服贴于芯片感应面的芯片封装构造，其特征在于，还包括一电路板，该基板与该金属盖个别接合至该电路板。
8.根据权利要求1所述的保护片服贴于芯片感应面的芯片封装构造，其特征在于，其中该连接端点为一位于该芯片感应面的周边焊垫，并以一焊线连接该连接端点至该基板，该焊线在该主芯片上方的线弧部位嵌埋于该第一黏晶层中。
9.根据权利要求1所述的保护片服贴于芯片感应面的芯片封装构造，其特征在于，其中该连接端点设于该主芯片相对于该芯片感应面的一下表面，该连接端点包含至少一凸块。
10.根据权利要求1至9中任一项所述的保护片服贴于芯片感应面的芯片封装构造，其特征在于，其中该芯片感应面包含一指纹识别区，且该第一黏晶层全面覆盖于该指纹识别区。
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