CN209593406U - A kind of novel operational amplification circuit suitable for 12 pipeline ADCs - Google Patents
A kind of novel operational amplification circuit suitable for 12 pipeline ADCs Download PDFInfo
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- CN209593406U CN209593406U CN201822179875.9U CN201822179875U CN209593406U CN 209593406 U CN209593406 U CN 209593406U CN 201822179875 U CN201822179875 U CN 201822179875U CN 209593406 U CN209593406 U CN 209593406U
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Abstract
The utility model discloses one kind to be suitable for 12 pipeline ADC (Analog-to-Digital Converter, analog-digital converter) novel operational amplification circuit in circuit, including PMOS tube M1, PMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupled capacitor Cin1, coupled capacitor Cin2, load capacitance CL1, load capacitance CL2, current source Ib, input voltage vin+, input voltage vin-, common-mode voltage Vcm, output voltage Vo+, output voltage Vo-, first switch s1, second switch s2, third switch s3, 4th switch s4, 5th switch s5, 6th opens Close s6, the 7th switch s7, the 8th switch s8, the 9th switch s9, the tenth switch s10, the 11st switch s11 and the 12nd switch s12.It by the charged state and working condition of ON-OFF control circuit, improves work efficiency, the circuit structure being mutually coupled using two kinds, is reducing power consumption, improve common mode inhibition capacity and power supply rejection ability while saving chip area, improved to noise is reduced.
Description
Technical field
The utility model relates to one kind to be suitable for 12 pipeline ADCs (Analog-to-Digital Converter, moulds
Number converter) in novel operational amplification circuit.Belong to analogue layout and field of integrated system.
Background technique
Pipeline ADC can provide very high sampling rate, therefore the promotion in market between resolution ratio 6 to 12
Under, it is widely used in mobile communcations system, the fields such as portable device and test equipment.The main trend of pipeline ADC design
It is to reduce power consumption and reduce chip area, and important composition module of the operational amplifier as pipeline ADC, it is desirable that operation amplifier
Device has low noise, and the performances such as low-power consumption whiles will also keep the characteristics such as the linearity, and the performance of operational amplifier is in certain journey
The performance of pipeline ADC is determined on degree, therefore the design of operational amplifier is particularly important.
Summary of the invention
The purpose of this utility model is that guaranteeing pipeline ADC for the operational amplification circuit design in pipeline ADC
The power consumption that pipeline ADC is reduced while stability, reduces chip area, reduces noise.It thus provides a kind of by opening
Close the holosymmetric novel operational amplification circuit of control work.
The above-mentioned purpose of the utility model is mainly to be realized by scheme below:
A kind of basic framework of 12 pipeline ADCs is as shown in Figure 1, it is characterized by comprising pipeline stages circuits
(101), the first level production line internal circuit (102), delay and calibration circuit (103), novel operational amplification circuit (104),
In:
Pipeline stages circuit (101): it is made of five pipeline ADC circuits cascadings, the pipeline ADC that the first order is 3.5
Circuit uses the circuit structure that SHA_Less is kept without sampling, compared to the circuit structure for having sampling to keep SHA, is realizing phase
While with performance, lower power consumption 20% or so, and eliminate the latter because the introduced noise of self structure etc. is non-linear
Factor influences.Second and third, 1.5 circuits of level Four use Op-amp sharing structure, function can be reduced while improving speed
Consumption.One 3 quick flashing Flash type adc circuits are finally cascaded again, and the output of every level-one all connects the input of next stage；First
Level production line internal circuit (102): being the frame diagram of SHA_Less circuit, and input signal vin1 is directly accessed sub- grade ADC electricity
In road and add circuit, sub- grade adc circuit converts digital signal Dout for the analog signal of input and accesses following delay
In calibration circuit (103), while the output of sub- grade adc circuit is also connected to the input of sub- grade DAC circuit, sub- grade DAC circuit
The digital signal Dout of access is again converted to analog signal vdac, then is subtracted each other with input signal vin1 before, is obtained
Surplus passes through amplifier again and amplifies to obtain vout, is finally linked into again in the circuit of next stage, the input vin2 as next stage
Continue to execute same work；
Delay and calibration circuit (103): the error coded that prime exports is calibrated by digital error correction algorithm, finally
Digit after being calibrated is exactly 12 precision of entire pipeline ADC；
Novel operational amplification circuit (104): the surplus after input signal vin1 is subtracted each other with analog quantity vdac amplifies,
Obtained output voltage vout is sent into lower pipeline stage as the input vin2 of next stage.
The above-mentioned novel operational amplification circuit (104) being previously mentioned can reduce capacitor using the capacitance structure being mutually coupled
Size, to reduce chip area, the characteristic gradually to be failed using capacitor reduces the nonlinear distortion of operational amplifier circuit, thus
Reach and increase powerful effect, certain common mode inhibition capacity can be also provided.
The above-mentioned novel operational amplification circuit (104) being previously mentioned is guaranteeing electricity using the ohmic load structure being mutually coupled
So that amplifier is significantly larger than the output impedance under common mode mode in the output impedance under differential mode while the symmetry of road, has
Very high common-mode rejection ratio CMRR and power supply rejection ratio PSRR, to have the function that reduce noise.
The above-mentioned novel operational amplification circuit (104) being previously mentioned as shown in Fig. 2, include PMOS tube M1, PMOS tube M2,
PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupled capacitor Cin1, coupled capacitor
Cin2, load capacitance CL1, load capacitance CL2, current source Ib, input voltage vin+, input voltage vin-, common-mode voltage Vcm,
Output voltage Vo+, output voltage Vo-, first switch s1, second switch s2, third switch s3, the 4th switch s4, the 5th switch
S5, the 6th switch s6, the 7th switch s7, the 8th switch s8, the 9th switch s9, the tenth switch s10, the 11st switch s11 and
12nd switch s12.
The above-mentioned novel operational amplification circuit (104) being previously mentioned includes that two clocks mutually control two working conditions respectively,
Clock phase Φ 1 and clock phase Φ 2, wherein clock phase Φ 1 control switch s1 to switch s6 closure, switch s7 to switch s12 are disconnected
It opens；Clock phase Φ 2 control switch s1 to switch s6 is disconnected, switch s7 to switch s12 closure.
Wherein, when clock phase Φ 1, as shown in figure 3, include PMOS tube M1, PMOS tube M2, two coupled capacitor Cin1 and
Cin2, two load capacitance CL1 and CL2, common-mode voltage Vcm, wherein the grid of PMOS tube M1 and the grid of PMOS tube M2, leakage
Pole and one end of current source Ib are connected, and source electrode connects VDD, and drain electrode is connected in the upper pole of two coupled capacitors Cin1 and Cin2 respectively
On plate, the bottom crown of two coupled capacitors Cin1 and Cin2 all connect ground, and the source electrode of PMOS tube M2 is connected with VDD, two load electricity
The top crown for holding CL1 and CL2 is connected with common-mode voltage Vcm respectively, and even, the other end of current source is even for bottom crown；Clock phase
When Φ 2, as shown in figure 4, including PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupling
Close capacitor Cin1, coupled capacitor Cin2, load capacitance CL1, load capacitance CL2, input voltage vin+, input voltage vin-is defeated
Voltage Vo+ out, output voltage Vo-, wherein the grid of PMOS tube M3 is connected with Vin+, the upper pole of source electrode and coupled capacitor Cin2
Plate is connected, and drain the top crown with load capacitance CL1 respectively, output voltage Vo-, the drain and gate of NMOS tube M7, NMOS tube
The grid of the drain electrode of M5 and NMOS tube M6 are connected, and the grid of PMOS tube M4 is connected with output voltage Vin-, source electrode with couple electricity
The top crown for holding Cin1 is connected, the drain electrode top crown with load capacitance CL2 respectively, output voltage Vo+, the drain electrode of NMOS tube M8 and
The grid of grid, the drain electrode of NMOS tube M6 and NMOS tube M5 are connected, the bottom crown of coupled capacitor Cin1 respectively with NMOS tube M7,
The source electrode of NMOS tube M5 is connected, and respectively with NMOS tube M6, the source electrode of NMOS tube M8 is connected the bottom crown of coupled capacitor Cin2.
Compared with prior art, the technical solution of the utility model has the advantages that
This utility model mainly from the working efficiency for increasing operational amplifier, reduces chip area, reduces the side such as noise
Face research, for working efficiency, using ON-OFF control circuit work structuring, can first charge when operational amplifier does not work, work
Capacitor directly powers to operational amplifier when making, and improves operating rate, while reducing amplifier using the attenuation characteristic of capacitor
It is non-linear caused by distortion, and then improve working efficiency, use is mutually coupled capacitance structure and can reduce the area of chip,
Simultaneously in terms of noise, use is mutually coupled ohmic load structure, increase while can significantly increasing output impedance
Common-mode rejection ratio and power supply rejection ratio, to reduce noise.
Detailed description of the invention
Fig. 1 be the utility model proposes 12 pipeline ADCs of one kind frame diagram；
Fig. 2 is a kind of novel operational amplification circuit (104) structural representation suitable for 12 pipeline ADCs of the utility model
Figure；
Fig. 3 is a kind of novel operational amplification circuit (104) suitable for 12 pipeline ADCs of the utility model in clock phase
Structural schematic diagram when Φ 1；
Fig. 4 is a kind of novel operational amplification circuit (104) suitable for 12 pipeline ADCs of the utility model in clock phase
Structural schematic diagram when Φ 2；
Specific embodiment
In order to further introduce the particular content of the utility model, the architectural characteristic and circuit different clocks of circuit
The working condition of phase is specifically described in detail the utility model in conjunction with attached drawing.
The utility model provides a kind of frame diagram of 12 pipeline ADCs, as shown in Figure 1, including pipeline stages electricity
Road (101), the first level production line internal circuit (102), delay and calibration circuit (103), novel operational amplification circuit
(104), here in order to realize reduction chip area, reduction power consumption the purpose of improving work efficiency, reduce noise, is proposed a kind of new
Type operational amplification circuit (104), as shown in Fig. 2, including PMOS tube M1, PMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube
M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupled capacitor Cin1, coupled capacitor Cin2, load capacitance CL1, load capacitance
CL2, current source Ib, input voltage vin+, input voltage vin-, common-mode voltage Vcm, output voltage Vo+, output voltage Vo-,
First switch s1, second switch s2, third switch s3, the 4th switch s4, the 5th switch s5, the 6th switch s6, the 7th switch s7,
8th switch s8, the 9th switch s9, the tenth switch s10, the 11st switch s11 and the 12nd switch s12.
As shown in Fig. 2, novel operational amplification circuit (104) is mutual using using while being mutually coupled condenser network structure
The resistance of coupling does the circuit structure loaded.The capacitance structure being wherein mutually coupled can reduce capacitor size, to reduce core
Piece area, the characteristic gradually to be failed using capacitor reduce the nonlinear distortion of operational amplifier circuit, increase powerful work to reach
With can also provide certain common mode inhibition capacity；The ohmic load structure being mutually coupled makes while guaranteeing circuit symmetry
Amplifier is significantly larger than the output impedance under common mode mode in the output impedance under differential mode, significantly increases common mode inhibition
Ability and power supply rejection ability, to have the function that reduce noise.
There are two state, charged state and working conditions for novel operational amplification circuit (104), wherein charged state is corresponding
Clock phase Φ 1, clock phase Φ 1 control switch s1 to switch s6 closure, switch s7 to switch s12 are disconnected, if Fig. 3 is shown, packet
Include PMOS tube M1, PMOS tube M2, two coupled capacitor Cin1 and Cin2, two load capacitance CL1 and CL2, common-mode voltage Vcm,
Wherein, one end of the grid of the grid of PMOS tube M1 and PMOS tube M2, drain electrode and current source Ib are connected, and source electrode connects VDD, leakage
Pole is connected in respectively on the top crown of two coupled capacitors Cin1 and Cin2, and the bottom crown of two coupled capacitors Cin1 and Cin2 all connect
The source electrode on ground, PMOS tube M2 is connected with VDD, the top crown of two load capacitances CL1 and CL2 respectively with common-mode voltage Vcm phase
Even, even, the other end of current source is even for bottom crown；Working condition corresponds to clock phase Φ 2, and 2 control switch s1 of clock phase Φ is arrived
Switch s6 is disconnected, switch s7 to switch s12 closure, as shown in figure 4, including PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS
Pipe M6, NMOS tube M7, NMOS tube M8, coupled capacitor Cin1, coupled capacitor Cin2, load capacitance CL1, load capacitance CL2 are defeated
Enter voltage Vin+, input voltage vin-, output voltage Vo+, output voltage Vo-, wherein the grid of PMOS tube M3 and Vin+ phase
Even, source electrode is connected with the top crown of coupled capacitor Cin2, and drain the top crown with load capacitance CL1 respectively, output voltage Vo-,
The grid of the drain and gate of NMOS tube M7, the drain electrode of NMOS tube M5 and NMOS tube M6 are connected, the grid of PMOS tube M4 with it is defeated
Voltage Vin- is connected out, and source electrode is connected with the top crown of coupled capacitor Cin1, and drain the top crown with load capacitance CL2 respectively,
Output voltage Vo+, the drain and gate of NMOS tube M8, the drain electrode of NMOS tube M6 and the grid of NMOS tube M5 are connected, coupling electricity
Hold the bottom crown of Cin1 respectively with NMOS tube M7, the source electrode of NMOS tube M5 is connected, the bottom crown of coupled capacitor Cin2 respectively with
The source electrode of NMOS tube M6, NMOS tube M8 are connected.It is in summary the specific embodiment of the utility model, the original of the utility model
Reason is described among above explanation.The protection scope of the utility model is not limited solely to this.This professional domain it is any
The simple structure change that designer makes within the scope of the disclosure of the utility model, belongs within this utility model.
Therefore, the protection scope of the utility model should be subject to the range of claims.
Claims (5)
1. a kind of novel operational amplification circuit (104) suitable for 12 pipeline ADCs, it is characterised in that: including PMOS tube
M1, PMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupled capacitor
Cin1, coupled capacitor Cin2, load capacitance CL1, load capacitance CL2, current source Ib, input voltage vin+, input voltage vin-,
Common-mode voltage Vcm, output voltage Vo+, output voltage Vo-, first switch s1, second switch s2, third switch s3, the 4th switch
S4, the 5th switch s5, the 6th switch s6, the 7th switch s7, the 8th switch s8, the 9th switch s9, the tenth switch s10, the 11st
Switch s11 and the 12nd switch s12.
2. novel operational amplification circuit (104) according to claim 1, it is characterised in that: the condenser network being mutually coupled
Structure includes PMOS tube M1, coupled capacitor Cin1, coupled capacitor Cin2, first switch s1, second switch s2, the 5th switch s5,
6th switch s6, wherein the both ends of first switch s1 and second switch s2 are connected in the drain electrode and coupled capacitor of PMOS tube M1 respectively
The both ends of Cin1, the top crown of coupled capacitor Cin2, the 5th switch s5 and the 6th switch s6 be connected in respectively and coupled capacitor
Cin1, the bottom crown of coupled capacitor Cin2.
3. novel operational amplification circuit (104) according to claim 1, it is characterised in that: the resistance being mutually coupled is born
The circuit structure of load includes PMOS tube M3, and PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, the 7th opens
Close s7, the 8th switch s8, the 9th switch s9, the tenth switch s10, wherein PMOS tube M3, PMOS tube M4 as Differential Input pipe,
The source electrode of PMOS tube M3 is connected in one end of the 7th switch s7, and grid is connected with Vin+, drain electrode respectively with the drain electrode of NMOS tube M7 and
Grid, the drain electrode of NMOS tube M5 and the grid of NMOS tube M6 are connected, and the source electrode of PMOS tube M4 is connected in one end of the 8th switch s8,
Grid is connected with output voltage Vin-, the drain and gate of drain electrode difference NMOS tube M8, the drain electrode and NMOS tube of NMOS tube M6
The grid of M5 is connected;The source electrode of PMOS tube M5 is connected in one end of the 9th switch s9, and the source electrode of PMOS tube M7 is connected in the 9th switch s9
The other end, the source electrode of PMOS tube M6 is connected in one end of the tenth switch s10, and the source electrode of PMOS tube M8 is connected in the tenth switch s10's
The other end.
4. novel operational amplification circuit (104) according to claim 1, it is characterised in that: at 1 corresponding circuits of clock phase Φ
In charged state, clock phase Φ 1 controls first switch s1 and is closed to the 6th switch s6, the 7th switch s7 to the 12nd switch s12
It disconnects, including PMOS tube M1, PMOS tube M2, two coupled capacitor Cin1 and Cin2, two load capacitances CL1 and CL2, common mode electricity
Press Vcm, wherein one end of the grid of PMOS tube M1 and the grid of PMOS tube M2, drain electrode and current source Ib are connected, and source electrode connects
VDD, drain electrode are connected in respectively on the top crown of two coupled capacitors Cin1 and Cin2, the lower pole of two coupled capacitors Cin1 and Cin2
Plate all connects ground, and the source electrode of PMOS tube M2 is connected with VDD, the top crown of two load capacitances CL1 and CL2 respectively with common-mode voltage
Vcm is connected, and even, the other end of current source is even for bottom crown.
5. novel operational amplification circuit (104) according to claim 1, it is characterised in that: at 2 corresponding circuits of clock phase Φ
In magnifying state, clock phase Φ 2 control switch s1 to switch s6 is disconnected, switch s7 to switch s12 closure, including PMOS tube M3,
PMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, coupled capacitor Cin1, coupled capacitor Cin2, load electricity
Hold CL1, load capacitance CL2, input voltage vin+, input voltage vin-, output voltage Vo+, output voltage Vo-, wherein PMOS
The grid of pipe M3 is connected with Vin+, and source electrode is connected with the top crown of coupled capacitor Cin2, drains upper with load capacitance CL1 respectively
Pole plate, output voltage Vo-, the drain and gate of NMOS tube M7, the drain electrode of NMOS tube M5 and the grid of NMOS tube M6 are connected,
The grid of PMOS tube M4 is connected with output voltage Vin-, and source electrode is connected with the top crown of coupled capacitor Cin1, drain electrode respectively with it is negative
Carry the top crown of capacitor CL2, output voltage Vo+, the drain and gate of NMOS tube M8, the drain electrode of NMOS tube M6 and NMOS tube M5
Grid be connected, respectively with NMOS tube M7, the source electrode of NMOS tube M5 is connected the bottom crown of coupled capacitor Cin1, coupled capacitor
Respectively with NMOS tube M6, the source electrode of NMOS tube M8 is connected the bottom crown of Cin2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822179875.9U CN209593406U (en) | 2018-12-25 | 2018-12-25 | A kind of novel operational amplification circuit suitable for 12 pipeline ADCs |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822179875.9U CN209593406U (en) | 2018-12-25 | 2018-12-25 | A kind of novel operational amplification circuit suitable for 12 pipeline ADCs |
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| Publication Number | Publication Date |
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| CN209593406U true CN209593406U (en) | 2019-11-05 |
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|---|---|---|---|
| CN201822179875.9U Expired - Fee Related CN209593406U (en) | 2018-12-25 | 2018-12-25 | A kind of novel operational amplification circuit suitable for 12 pipeline ADCs |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109560816A (en) * | 2018-12-25 | 2019-04-02 | 哈尔滨理工大学 | A kind of improved operational amplification circuit suitable for 12 low-power consumption assembly line ADC |
-
2018
- 2018-12-25 CN CN201822179875.9U patent/CN209593406U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109560816A (en) * | 2018-12-25 | 2019-04-02 | 哈尔滨理工大学 | A kind of improved operational amplification circuit suitable for 12 low-power consumption assembly line ADC |
| CN109560816B (en) * | 2018-12-25 | 2024-04-19 | 哈尔滨理工大学 | Improved operational amplifier circuit suitable for 12-bit low-power-consumption pipelined ADC |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20191105 Termination date: 20201225 |