CN102291116B - Turnover type sampling hold circuit - Google Patents
Turnover type sampling hold circuit Download PDFInfo
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- CN102291116B CN102291116B CN2011101479414A CN201110147941A CN102291116B CN 102291116 B CN102291116 B CN 102291116B CN 2011101479414 A CN2011101479414 A CN 2011101479414A CN 201110147941 A CN201110147941 A CN 201110147941A CN 102291116 B CN102291116 B CN 102291116B
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Abstract
The invention discloses a turnover type sampling hold circuit, which relates to an integrated circuit technology. The circuit comprises a first switch bootstrap circuit, a first sampling switch tube, a second switch bootstrap circuit, a second sampling switch tube, an amplifier and a first load capacitive circuit and a second load capacitive circuit, and is characterized in that: the first switchbootstrap circuit and the second switch bootstrap circuit have the same structure; the first switch bootstrap circuit comprises a charge compensation circuit; and the charge compensation circuit comprises a first capacitor and a second NMOS (N-channel Metal Oxide Semiconductor) transistor which form a loop. Through the circuit, the nonlinearity introduced by a sampling switch is greatly reduced, input bandwidth is improved, meanwhile, the power consumption of the entire sampling hold circuit is reduced.
Description
Technical field
The present invention relates to integrated circuit technique.
Background technology
The convertible sampling hold circuit of prior art is shown in Fig. 1 (a), and Fig. 1 (b) is its control clock.Its course of work is as follows: in the sampling phase, namely Ф 1 is high level, when Ф 2 is low level, and switch S 1 closure, input signal is sampled on the capacitor C S, and the sample/hold amplifier input is shorted to Vcm, and as virtually, output is short circuit also.Keeping phase, switch S 1 is turn-offed, the S2 closure, and Ф 1 ' is low level than Ф 1 early jump, forms the sole plate and samples to reduce the switch feedthrough, and amplifier is connected into closed loop, and the signal on the collected CS is set up at load capacitance CL before.Finished the discrete sampling to continuous signal thus.This circuit is applicable to the high-speed, high precision A/D converter.
In the convertible sampling hold circuit of tradition, input sample switch S 1 is because the non-linear and bulk effect of its equivalent resistance with introducing very big distortion, can limit the input signal bandwidth greatly.So incoming frequency is limited in the 100MHz.In addition, owing to be the closed-loop structure of capacitive form, amplifier need possess higher bandwidth and gain to satisfy the requirement of high-speed, high precision, and the power consumption that its consumption of inevitable requirement is very big is to realize less settling time like this.
Summary of the invention
Technical problem to be solved by this invention is, a kind of new sampling hold circuit is provided, and sampling switch is introduced non-linearly reduces greatly, and the input bandwidth is improved, and has reduced the power consumption of whole sampling hold circuit simultaneously.
Convertible sampling hold circuit, comprise the first switch boostrap circuit, the first sampling switch pipe, second switch boostrap circuit, the second sampling switch pipe, amplifier and the first load capacitance circuit, the second load capacitance circuit, it is characterized in that, the described first switch boostrap circuit is identical with second switch boostrap circuit structure, the first switch boostrap circuit comprises charge compensating circuit, and described charge compensating circuit comprises first electric capacity and the 2nd NMOS pipe that forms the loop.
The described first switch boostrap circuit comprises:
The one NMOS pipe, its grid connects second control signal, and drain electrode connects the drain electrode of a PMOS pipe, source ground; The one PMOS pipe, its grid connects second control signal, and source electrode connects the source electrode of the 3rd NMOS pipe; First electric capacity, the drain electrode of a termination the one PMOS pipe, an end ground connection; The 2nd NMOS pipe, its grid connects the source electrode of a PMOS pipe, drain electrode and source ground; The 3rd NMOS pipe, its grid connects second control signal, and drain electrode connects high level, and source electrode connects the grid of the 2nd PMOS pipe; The 2nd PMOS pipe, its grid connects second control signal, and drain electrode connects the drain and gate of the 4th NMOS pipe, and source electrode connects the source electrode of the 6th NMOS pipe; The 3rd PMOS pipe, its grid meets drain electrode and output end vo ut, and source electrode connects the source electrode of the 6th NMOS pipe; Drain electrode connects the drain electrode of the 5th NMOS pipe; The 4th NMOS pipe, its source ground, grid connect the grid of the 5th NMOS pipe; The 5th NMOS pipe, its source ground; The 6th NMOS pipe, its grid connects first control signal, and drain electrode connects current source; First switching device, a termination output end vo ut, a termination input Vin; Output end vo ut connects the grid of sampling switch pipe.
Further, the sampling switch pipe is the NMOS pipe, the source electrode of the first sampling switch pipe connects the first load capacitance circuit by first buffer circuit, the output of first buffer circuit also connects the substrate terminal of the first sampling switch pipe by the second switch device, the substrate terminal of the first sampling switch pipe is by the 3rd switching device ground connection; The source electrode of the second sampling switch pipe connects the second load capacitance circuit by second buffer circuit, the output of second buffer circuit also connects the substrate terminal of the second sampling switch pipe by the 4th switching device, the substrate terminal of the second sampling switch pipe is by the 5th switching device ground connection; Control termination first control signal of second switch device and the 4th switching device, control termination second control signal of the 3rd switching device and the 5th switching device.
The described first load capacitance circuit comprises: second electric capacity, and an end ground connection, an end connects the positivity output by the 8th switch device, and the output of first buffer circuit connects the positivity output by the 6th switching device and the 8th switch device; The 3rd electric capacity, an end ground connection, an end connects the positivity output by the 9th switching device, and the output of first buffer circuit closes device by minion and the 9th switching device connects the positivity output; Control termination the 3rd control signal of the 6th switching device and the 9th switching device, minion is closed control termination the 4th control signal of device and the 8th switch device;
The described second load capacitance circuit comprises: the 4th electric capacity, and an end ground connection, an end connects the negativity output by the 11 switching device, and the output of second buffer circuit connects the negativity output by the tenth switching device and the 11 switching device; The 5th electric capacity, an end ground connection, an end closes device by twelvemo and connects the negativity output, and the output of second buffer circuit closes device by twelvemo and the 13 switching device connects the negativity output; Control termination the 3rd control signal of the tenth switching device and the 13 switching device, the 11 switching device and twelvemo are closed control termination the 4th control signal of device.
The invention has the beneficial effects as follows, by precharge, substrate electric potential handoff technique and the charge compensation formula switch boostrap circuit that adopts a kind of novelty, make non-linear that sampling switch is introduced reduce greatly, the input bandwidth is improved, and has reduced the power consumption of whole sampling hold circuit simultaneously.From Fig. 5, Fig. 6 and table 1 as can be seen, after having adopted technology of the present invention, sampling hold circuit is under sample rate 100Msps, total harmonic distortion when 305.5MHz＜-70dB, SFDR and SNDR reach 77dB and 67.8dB respectively, so it can be changed the signal of the highest 305.5MHz, possesses the higher sampling ability of owing.Simultaneously, owing to adopted the precharge technology to make power consumption be reduced, total power consumption only is 47mW.
Description of drawings
Fig. 1 is the schematic diagram of prior art, (a) is electrical block diagram, (b) is control clock schematic diagram.
Fig. 2 (a) is the switch boostrap circuit figure of prior art, the charge compensating circuit figure that Fig. 2 (b) proposes for the present invention.
Fig. 3 is for adopting and do not adopt the bootstrapped switch control voltage schematic diagram of charge compensation.
The convertible sampling hold circuit schematic diagram that Fig. 4 proposes for the present invention: (a) be electrical block diagram, (b) be control clock schematic diagram.
Fig. 5 is the total harmonic distortion curve chart that records.
The output signal spectrum figure that Fig. 6 records when being incoming frequency 305.5MHz.
Embodiment
Referring to Fig. 2～4.
Convertible sampling hold circuit of the present invention, comprise the first switch boostrap circuit 101, the first sampling switch pipe S11, second switch boostrap circuit 102, the second sampling switch pipe S12, amplifier and the first load capacitance circuit, the second load capacitance circuit, it is characterized in that, the described first switch boostrap circuit is identical with second switch boostrap circuit structure, the first switch boostrap circuit 101 comprises charge compensating circuit, and described charge compensating circuit comprises first capacitor C 1 and the 2nd NMOS pipe N20 that forms the loop.
The described first switch boostrap circuit comprises:
The one NMOS manages N10, and its grid meets the second control signal Ф 2, and drain electrode connects the drain electrode of PMOS pipe P10, source ground;
The one PMOS manages P10, and its grid meets the second control signal Ф 2, and source electrode connects the source electrode of the 3rd NMOS pipe N30;
The drain electrode of first capacitor C, 1, one termination the one PMOS pipe P10, an end ground connection;
The 2nd NMOS manages N20, and its grid connects the source electrode of PMOS pipe P10, drain electrode and source ground;
The 3rd NMOS manages N30, and its grid meets the second control signal Ф 2, and drain electrode connects high level, and source electrode connects the grid of the 2nd PMOS pipe P20;
The 2nd PMOS manages P20, and its grid meets the second control signal Ф 2, and drain electrode connects the drain and gate of the 4th NMOS pipe N40, and source electrode connects the source electrode of the 6th NMOS pipe N60;
The 3rd PMOS manages P30, and its grid meets drain electrode and output end vo ut, and source electrode connects the source electrode of the 6th NMOS pipe N60; Drain electrode connects the drain electrode of the 5th NMOS pipe;
The 4th NMOS manages N40, and its source ground, grid connect the grid of the 5th NMOS pipe N50;
The 5th NMOS manages N50, its source ground;
The 6th NMOS manages N60, and its grid meets the first control signal Ф 1, and drain electrode connects current source;
The first switching device S10, a termination output end vo ut, a termination input Vin;
Output end vo ut connects the grid of sampling switch pipe.
The sampling switch pipe is the NMOS pipe, the source electrode of the first sampling switch pipe S11 connects the first load capacitance circuit by first buffer circuit 71, the output of first buffer circuit 71 also connects the substrate terminal of the first sampling switch pipe S11 by second switch device K2, the substrate terminal of the first sampling switch pipe S11 is by the 3rd switching device K3 ground connection;
The source electrode of the second sampling switch pipe S12 connects the second load capacitance circuit by second buffer circuit 72, the output of second buffer circuit 72 also connects the substrate terminal of the second sampling switch pipe S12 by the 4th switching device K4, the substrate terminal of the second sampling switch pipe S12 is by the 5th switching device K5 ground connection;
The control termination first control signal Ф, 1, the three switching device K3 of second switch device K2 and the 4th switching device K4 and the control termination second control signal Ф 2 of the 5th switching device K5.
The described first load capacitance circuit comprises:
Second capacitor C, 2, one end ground connection, an end connects the positivity output by the 8th switch device K8, and the output of first buffer circuit 71 connects the positivity output by the 6th switching device K6 and the 8th switch device K8;
The 3rd capacitor C 3, one end ground connection, an end connects the positivity output by the 9th switching device K9, and the output of first buffer circuit 71 closes device K7 by minion and the 9th switching device K9 connects the positivity output;
Control termination the 3rd control signal Ф 1 ', the minion of the 6th switching device K6 and the 9th switching device K9 is closed control termination the 4th control signal Ф 2 ' of device K7 and the 8th switch device K8;
The described second load capacitance circuit comprises:
The 4th capacitor C 4, one end ground connection, an end connects the negativity output by the 11 switching device K11, and the output of second buffer circuit 72 connects the negativity output by the tenth switching device K10 and the 11 switching device K11;
The 5th capacitor C 5, one end ground connection, an end closes device K12 by twelvemo and connects the negativity output, and the output of second buffer circuit 72 closes device K12 by twelvemo and the 13 switching device K13 connects the negativity output;
Control termination the 3rd control signal Ф 1 ' of the tenth switching device K10 and the 13 switching device K13, the 11 switching device K11 and twelvemo are closed control termination the 4th control signal Ф 2 ' of device K12.
Below be principle Analysis:
For nonlinear switching resistance, generally be to adopt the switch boostrap circuit to make the gate source voltage Vgs of nmos switch keep constant, thereby guarantee the constant of impedance.Shown in Fig. 2 (a), Ф 1 and Ф 2 are complementary clocks, and when Ф 1 was high level, bootstrap capacitor Cboot was charged to supply voltage VDD, and when being high, the gate source voltage Vgs of sampling switch Msw is constant to be VDD at Ф 2.But because the electric charge of bootstrap capacitor Cboot and sampling switch Msw is shared, make that Vgs can not be constant, under high frequency, will influence whole conversion accuracy.
The present invention proposes a kind of additional charge compensating circuit, it has compensated because sampling switch is shared the loss of charge that causes, shown in Fig. 2 (b).When low, Ф 2 be high at Ф 1, and first capacitor C 1 is discharged into ground (the C1 size is the same with Cboot) by NMOS pipe N10, and the 2nd NMOS manages that N20 is charged to VDD(N20 and the Msw size is just the same); When Ф 1 is high, when Ф 2 is low, first capacitor C 1 and the 2nd NMOS pipe N20 short circuit carry out electric charge to be shared, make that the electric charge on the 2nd NMOS pipe N20 just in time is the quantity of electric charge that Cboot goes up loss, the signal that this moment, the 2nd NMOS managed on the N20 is managed the buffer that N50, the 6th NMOS pipe N60 forms through managing P30, the 4th NMOS pipe N40, the 5th NMOS by the 2nd PMOS pipe P20, the 3rd PMOS, output on the sampling switch pipe Msw grid, carry out charge compensation.Fig. 3 is the control voltage of bootstrapped switch under employing and the situation that does not adopt charge compensating circuit.Can see, adopted above-mentioned compensating circuit after, the bootstrapped switch signal is compensated, make Msw the gate source voltage near ideal reach constant.
Another causes the nonlinear factor of hindrance is the bulk effect of input sample switching tube.It makes the threshold voltage of switching tube change with input signal, if should directly link to each other with the source by the pipe substrate, the non-linear of big junction capacitance contribution of introducing will be more serious.The present invention proposes a kind of in conjunction with substrate electric potential switching and precharge technology, as shown in Figure 4.Can see, at the sampling phase time, Ф 1 is high, and Ф 2 is low, the output of the substrate order position gain buffer (buf) of the first sampling switch pipe S11, because buf input, output potential equate, so at this moment the first sampling switch pipe S11 substrate electric potential and input join, the first sampling switch pipe S11 does not have bulk effect, and buf also makes substrate and signal input part obtain isolating, simultaneously, input signal carries out precharge by load capacitance second capacitor C 2 of buf; Keeping phase, Ф 1 is low, Ф 2 is high, the substrate ground connection of the first sampling switch pipe S11, buf carries out precharge to another load capacitance the 3rd capacitor C 3, inserted as the sampling hold circuit load by precharge second capacitor C 2 before, make amplifier require to reduce greatly settling time, thereby saved power consumption.
Adopt the effect after the above-mentioned new technology:
By to test result (print is based on the dark N trap of 0.18 μ m CMOS technology) Fig. 5, Fig. 6 of actual print and table 1 as can be seen, after having adopted above-mentioned new technology, sampling hold circuit is under sample rate 100Msps, total harmonic distortion when 305.5MHz＜-70dB, SFDR and SNDR reach 77dB and 67.8dB respectively, so it can be changed the signal of the highest 305.5MHz, possesses the higher sampling ability of owing.Simultaneously, owing to adopted the precharge technology to make power consumption be reduced, total power consumption only is 47mW.
Table 1
Claims (3)
1. convertible sampling hold circuit, comprise the first switch boostrap circuit (101), the first sampling switch pipe (S11), second switch boostrap circuit (102), the second sampling switch pipe (S12), amplifier and the first load capacitance circuit, the second load capacitance circuit, it is characterized in that, the described first switch boostrap circuit is identical with second switch boostrap circuit structure, the first switch boostrap circuit (101) comprises charge compensating circuit, and described charge compensating circuit comprises first electric capacity (C1) and the 2nd NMOS pipe (N20) that forms the loop;
The described first switch boostrap circuit comprises:
The one NMOS manages (N10), and its grid connects second control signal (Ф 2), and drain electrode connects the drain electrode of PMOS pipe (P10), source ground;
The one PMOS manages (P10), and its grid connects second control signal (Ф 2), and source electrode connects the source electrode of the 3rd NMOS pipe (N30);
First electric capacity (C1), the drain electrode of a termination the one PMOS pipe (P10), an end ground connection;
The 2nd NMOS manages (N20), and its grid connects the source electrode of PMOS pipe (P10), drain electrode and source ground;
The 3rd NMOS manages (N30), and its grid connects second control signal (Ф 2), and drain electrode connects high level, and source electrode connects the grid of the 2nd PMOS pipe (P20);
The 2nd PMOS manages (P20), and its grid connects second control signal (Ф 2), and drain electrode connects the drain and gate of the 4th NMOS pipe (N40), and source electrode connects the source electrode of the 6th NMOS pipe (N60);
The 3rd PMOS manages (P30), and its grid meets drain electrode and output end vo ut, and source electrode connects the source electrode of the 6th NMOS pipe (N60); Drain electrode connects the drain electrode of the 5th NMOS pipe;
The 4th NMOS manages (N40), and its source ground, grid connect the grid of the 5th NMOS pipe (N50);
The 5th NMOS manages (N50), its source ground;
The 6th NMOS manages (N60), and its grid connects first control signal (Ф 1), and drain electrode connects current source;
First switching device (S10), a termination output end vo ut, a termination input Vin;
Output end vo ut connects the grid of sampling switch pipe.
2. convertible sampling hold circuit as claimed in claim 1, it is characterized in that, the sampling switch pipe is the NMOS pipe, the source electrode of the first sampling switch pipe (S11) connects the first load capacitance circuit by first buffer circuit (71), the output of first buffer circuit (71) also connects the substrate terminal of the first sampling switch pipe (S11) by second switch device (K2), the substrate terminal of the first sampling switch pipe (S11) is by the 3rd switching device (K3) ground connection;
The source electrode of the second sampling switch pipe (S12) connects the second load capacitance circuit by second buffer circuit (72), the output of second buffer circuit (72) also connects the substrate terminal of the second sampling switch pipe (S12) by the 4th switching device (K4), the substrate terminal of the second sampling switch pipe (S12) is by the 5th switching device (K5) ground connection;
Control termination first control signal (Ф 1) of second switch device (K2) and the 4th switching device (K4), control termination second control signal (Ф 2) of the 3rd switching device (K3) and the 5th switching device (K5).
3. convertible sampling hold circuit as claimed in claim 2 is characterized in that, the described first load capacitance circuit comprises:
Second electric capacity (C2), an end ground connection, an end connects the positivity output by the 8th switch device (K8), and the output of first buffer circuit (71) connects the positivity output by the 6th switching device (K6) and the 8th switch device (K8);
The 3rd electric capacity (C3), an end ground connection, an end connects the positivity output by the 9th switching device (K9), and the output of first buffer circuit (71) closes device (K7) by minion and the 9th switching device (K9) connects the positivity output;
Control termination the 3rd control signal (Ф 1 ') of the 6th switching device (K6) and the 9th switching device (K9), minion is closed control termination the 4th control signal (Ф 2 ') of device (K7) and the 8th switch device (K8);
The described second load capacitance circuit comprises:
The 4th electric capacity (C4), an end ground connection, an end connects the negativity output by the 11 switching device (K11), and the output of second buffer circuit (72) connects the negativity output by the tenth switching device (K10) and the 11 switching device (K11);
The 5th electric capacity (C5), an end ground connection, an end closes device (K12) by twelvemo and connects the negativity output, and the output of second buffer circuit (72) closes device (K12) by twelvemo and the 13 switching device (K13) connects the negativity output;
Control termination the 3rd control signal (Ф 1 ') of the tenth switching device (K10) and the 13 switching device (K13), the 11 switching device (K11) and twelvemo are closed control termination the 4th control signal (Ф 2 ') of device (K12).
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011101479414A CN102291116B (en) | 2011-06-02 | 2011-06-02 | Turnover type sampling hold circuit |
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| CN2011101479414A CN102291116B (en) | 2011-06-02 | 2011-06-02 | Turnover type sampling hold circuit |
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| CN102291116A CN102291116A (en) | 2011-12-21 |
| CN102291116B true CN102291116B (en) | 2013-09-04 |
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| US10037814B2 (en) * | 2015-09-11 | 2018-07-31 | Texas Instruments Incorporated | Track and hold with active charge cancellation |
| CN105680841B (en) * | 2015-12-29 | 2018-05-08 | 龙迅半导体（合肥）股份有限公司 | Switch module and its control method |
| CN109346123B (en) * | 2018-10-24 | 2021-08-20 | 上海华力微电子有限公司 | External high-voltage switching circuit of test port |
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| CN101577545B (en) * | 2008-05-07 | 2011-08-17 | 中国科学院电子学研究所 | Dual bootstrap and voltage compensation technology-based A/D converter sampling switch |
| CN101789776B (en) * | 2009-01-23 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Sampling switching circuit |
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Address after: No. 2201 and 2301, floor 22-23, building 1, No. 1800, middle section of Yizhou Avenue, high tech Zone, China (Sichuan) pilot Free Trade Zone, Chengdu, Sichuan 610041 Patentee after: Chengdu Hua Microelectronics Technology Co.,Ltd. Address before: 610000 block D, hi tech Industrial Park, No. 11, Gaopeng Avenue, hi tech Zone, Chengdu, Sichuan Patentee before: CHENGDU SINO MICROELECTRONICS TECHNOLOGY Co.,Ltd. |