CN209170344U - A successive approximation ADC structure to improve linearity - Google Patents
A successive approximation ADC structure to improve linearity Download PDFInfo
- Publication number
- CN209170344U CN209170344U CN201822120446.4U CN201822120446U CN209170344U CN 209170344 U CN209170344 U CN 209170344U CN 201822120446 U CN201822120446 U CN 201822120446U CN 209170344 U CN209170344 U CN 209170344U
- Authority
- CN
- China
- Prior art keywords
- tube
- gate
- drain
- circuit
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005070 sampling Methods 0.000 claims abstract description 9
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 238000010845 search algorithm Methods 0.000 claims abstract description 3
- 230000003068 static effect Effects 0.000 claims abstract 2
- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
本实用新型公开了一种提升线性度的逐次逼近性ADC结构，包括采样保持电路(103)，改进的基准电路(101)，DAC电路(100)，改进的比较器电路(102)，逻辑控制(104)，通过将模拟信号电平信息采样后保持在采样电容上并输出给后端电路。之后通过电容阵列和开关阵列，完成二进制搜索算法。DAC的基准电压是一个具有温度补偿的高精度的带隙基准源。比较器利用带前置放大器的锁存比较器，能获得比较好的整体噪声失调特性，拥有远小于静态比较器的功耗。逻辑部分采用异步SAR控制逻辑电路，避免外部高速时钟，降低了时钟电路的功耗和噪声干扰。该实用新型与普通的ADC电路相比具有拥有着很大的区别，改进后的电路功耗、线性度等特性得到了很大的改良。
The utility model discloses a successive approximation ADC structure for improving linearity, comprising a sampling and holding circuit (103), an improved reference circuit (101), a DAC circuit (100), an improved comparator circuit (102), and a logic control circuit (102). (104), after sampling the analog signal level information, hold it on the sampling capacitor and output it to the back-end circuit. Afterwards, the binary search algorithm is completed through the capacitor array and the switch array. The reference voltage of the DAC is a high precision bandgap reference with temperature compensation. The comparator utilizes a latching comparator with a preamplifier, which achieves better overall noise offset characteristics and consumes far less power than a static comparator. The logic part adopts asynchronous SAR control logic circuit to avoid external high-speed clock and reduce the power consumption and noise interference of the clock circuit. Compared with the ordinary ADC circuit, the utility model has a great difference, and the improved circuit power consumption, linearity and other characteristics have been greatly improved.
Description
技术领域technical field
本实用新型涉及一种提升线性度的逐次逼近性ADC结构，包括采样保持电路(103)，改进的基准电路(101)，DAC电路(100)，改进的比较器电路(102)，逻辑控制(104)，属于模拟集成电路设计与集成系统领域。The utility model relates to a successive approximation ADC structure for improving linearity, comprising a sampling and holding circuit (103), an improved reference circuit (101), a DAC circuit (100), an improved comparator circuit (102), a logic control circuit (103), and a logic control circuit (102). 104), which belongs to the field of analog integrated circuit design and integrated system.
背景技术Background technique
进入现代科技以来，模拟集成电路设计已经成为人们日常生活中的重要组成部分。在集成电路工艺水平不断地增高之时，提升线性度和降低功耗等性能是要实现的，为了使产品更优秀，更能适应市场的新要求，集成电路设计者们普遍认为降低功耗和提升线性度是一种用来提高电路整体水平的方法，而且对电路的只有微小的影响。同时由于目前设计师们对电路的功能以及准确性的有着更高的要求，所以电路的线性度提升就显得特别重要。Since entering modern technology, analog integrated circuit design has become an important part of people's daily life. When the level of integrated circuit technology continues to increase, performance such as improving linearity and reducing power consumption must be realized. In order to make products better and more adaptable to the new requirements of the market, integrated circuit designers generally believe that reducing power consumption and reducing power consumption Improving linearity is a method used to improve the overall level of a circuit with only minor effects on the circuit. At the same time, because designers have higher requirements on the function and accuracy of the circuit, the linearity improvement of the circuit is particularly important.
实用新型内容Utility model content
本实用新型的目的在与克服现有技术的不足，提供了一种提升线性度的逐次逼近性ADC结构，在原有的基础上同时提升了电路的线性度，并且采用了带隙电压基准作为DAC的输入电压，使得电路的线性范围变大。The purpose of the utility model is to overcome the deficiencies of the prior art, and to provide a successive approximation ADC structure that improves linearity, improves the linearity of the circuit on the basis of the original, and adopts a bandgap voltage reference as a DAC The input voltage increases the linear range of the circuit.
本实用新型的上述目的主要是通过以下的方案实现的：The above-mentioned purpose of the present utility model is mainly realized through the following scheme:
一种提升线性度的逐次逼近性ADC结构，其特征在于：包括采样保持电路(103)，改进的基准电路(101)，DAC电路(100)，改进的比较器电路(102)，逻辑控制(104)，其中：A successive approximation ADC structure for improving linearity is characterized in that: comprising a sample and hold circuit (103), an improved reference circuit (101), a DAC circuit (100), an improved comparator circuit (102), a logic control (103) 104), where:
采样保持电路(103)：保持阶段，开关闭合，开关断开。采样阶段，开关断开，开关闭合。采样并保持模拟输入信号，然后将保持的值发送给改进的比较器电路(102)的一端；Sample and hold circuit (103): in the hold phase, the switch is closed and the switch is opened. During the sampling phase, the switch is opened and the switch is closed. sampling and holding the analog input signal, then sending the held value to one end of the improved comparator circuit (102);
改进的基准电路(101)：产生一个具有温度补偿的高精度的带隙基准电流源，发送给DAC电路(100)；Improved reference circuit (101): generating a high-precision bandgap reference current source with temperature compensation, and sending it to the DAC circuit (100);
改进的比较器电路(102)：产生1或者0，将比较的值发送给逻辑控制(104)，之后进行数字输出；Improved comparator circuit (102): generate 1 or 0, send the compared value to logic control (104), and then perform digital output;
DAC电路(100)：通过电容阵列和开关阵列，完成二进制搜索算法，将计算的值发送给改进的比较器电路(102)的另一端；DAC circuit (100): completes the binary search algorithm through the capacitor array and the switch array, and sends the calculated value to the other end of the improved comparator circuit (102);
改进的比较器电路(102)：通过预放大结构和锁存器结构，利用第一级预放大可以很好地抑制锁存比较器的噪声，获得比较好的整体噪声失调特性，通过比较输出1或者0，将比较的值发送给逻辑控制(104)，之后进行数字输出；The improved comparator circuit (102): through the pre-amplification structure and the latch structure, the noise of the latch comparator can be well suppressed by using the first-stage pre-amplification, and a better overall noise offset characteristic can be obtained. By comparing the output 1 or 0, send the compared value to logic control (104), and then perform digital output;
逻辑控制(104) ：通过异步SAR控制逻辑电路进行最终的模数转换。Logic Control (104): The final analog-to-digital conversion is performed by an asynchronous SAR control logic circuit.
在上述的一种提升线性度的逐次逼近性ADC结构中，所述改进的基准电路(101)采用了曲率补偿，忽略了VBE的高阶项对带隙电路的影响。In the above-mentioned successive approximation ADC structure with improved linearity, the improved reference circuit (101) adopts curvature compensation, ignoring the influence of the high-order term of VBE on the bandgap circuit.
在上述的一种提升线性度的逐次逼近性ADC结构中，所述改进的比较器电路(102)采用了引入电阻的前置线性差分对结构，提升了线性输入范围。In the above-mentioned successive approximation ADC structure for improving linearity, the improved comparator circuit (102) adopts a pre-linear differential pair structure that introduces resistance, which improves the linear input range.
在上述的一种提升线性度的逐次逼近性ADC结构中，所述的改进的基准电路(101)包括PMOS管M1、PMOS管M2、PMOS管M5、电阻R1、电阻R5、电阻R6、电阻R7、电阻R8、电阻R10、BJT管M19、BJT管M20、PMOS管M4、BJT管M21、电阻R3、电阻R4、PMOS管M3；In the above-mentioned successive approximation ADC structure for improving linearity, the improved reference circuit (101) includes a PMOS transistor M1, a PMOS transistor M2, a PMOS transistor M5, a resistor R1, a resistor R5, a resistor R6, and a resistor R7 , resistor R8, resistor R10, BJT tube M19, BJT tube M20, PMOS tube M4, BJT tube M21, resistor R3, resistor R4, PMOS tube M3;
PMOS管M1源极接电源，栅极与PMOS管M2、M5栅极相连，漏极与电阻R10一端相连，M2源极与电源相连，漏极与电阻R8一端相连，PMOS管M5源极与电源相连，漏极与电阻R6一端相连，电阻R1一端与R7另一端相连，另一端与地相连，电阻R5一端与R8另一端相连，另一端与地相连，电阻R6另一端与地相连，电阻R10另一端与电阻R7相连，BJT管M19基极与地相连，集电极与地相连，发射极与R7另一端相连，BJT管M20基极与地相连，集电极与地相连，发射极与R8另一端相连，PMOS管M4源极接电源，栅极与PMOS管M1栅极相连，漏极与BJT管M21发射极相连，BJT管M21基极与地相连，集电极与地相连，电阻R3一端与PMOS管M12栅极相连，电阻R4一端与PMOS管M13栅极相连，PMOS管M3源极接电源，栅极与M1栅极相连，漏极与BJT管M20发射极相连。The source of the PMOS tube M1 is connected to the power supply, the gate is connected to the gates of the PMOS tubes M2 and M5, the drain is connected to one end of the resistor R10, the source of M2 is connected to the power supply, the drain is connected to one end of the resistor R8, and the source of the PMOS tube M5 is connected to the power supply Connected, the drain is connected to one end of resistor R6, one end of resistor R1 is connected to the other end of R7, the other end is connected to ground, one end of resistor R5 is connected to the other end of R8, the other end is connected to ground, the other end of resistor R6 is connected to ground, the other end of resistor R10 The other end is connected to resistor R7, the base of BJT tube M19 is connected to ground, the collector is connected to ground, the emitter is connected to the other end of R7, the base of BJT tube M20 is connected to ground, the collector is connected to ground, and the emitter is connected to R8. One end is connected, the source of the PMOS tube M4 is connected to the power supply, the gate is connected to the gate of the PMOS tube M1, the drain is connected to the emitter of the BJT tube M21, the base of the BJT tube M21 is connected to the ground, the collector is connected to the ground, and one end of the resistor R3 is connected to The gate of the PMOS tube M12 is connected to the gate, one end of the resistor R4 is connected to the gate of the PMOS tube M13, the source of the PMOS tube M3 is connected to the power supply, the gate is connected to the gate of M1, and the drain is connected to the emitter of the BJT tube M20.
在上述的一种提升线性度的逐次逼近性ADC结构中，所述的改进的比较器电路(102)包括PMOS管MA1、PMOS管MA2、PMOS管MA7、PMOS管MA8、PMOS管MA13、PMOS管MA14、NMOS管MA3、NMOS管MA4、NMOS管MA5、NMOS管MA6、NMOS管MA9、NMOS管MA10、NMOS管MA11、NMOS管MA12、电阻R1；In the above-mentioned successive approximation ADC structure for improving linearity, the improved comparator circuit (102) includes a PMOS transistor MA1, a PMOS transistor MA2, a PMOS transistor MA7, a PMOS transistor MA8, a PMOS transistor MA13, a PMOS transistor MA14, NMOS tube MA3, NMOS tube MA4, NMOS tube MA5, NMOS tube MA6, NMOS tube MA9, NMOS tube MA10, NMOS tube MA11, NMOS tube MA12, resistor R1;
PMOS管MA1源极接电源，栅极与PMOS管MA2栅极相连，漏极与NMOS管MA3漏极相连，PMOS管MA2源极接电源，栅极与时钟相连，漏极与NMOS管MA4漏极相连，NMOS管MA3栅极与输入相连，源极与NMOS管MA5漏极相连，NMOS管MA4栅极与输入相连，源极与NMOS管MA6漏极相连，电阻R1，一端与NMOS管MA3源极相连，另一端与NMOS管MA4源极相连，NMOS管MA5栅极与时钟相连，源极与地相连，NMOS管MA6栅极与时钟相连，源极与地相连，PMOS管MA7源极接电源，栅极与NMOS管MA10栅极相连，漏极与PMOS管MA13源极相连，PMOS管MA8源极接电源，栅极与NMOS管MA11栅极相连，漏极与PMOS管MA14源极相连，PMOS管MA13栅极与NMOS管MA4漏极相连，漏极与NMOS管MA11栅极相连，PMOS管MA14栅极与NMOS管MA3漏极相连，漏极与NMOS管MA10栅极相连，NMOS管MA10漏极与PMOS管MA13漏极相连，源极与地相连，NMOS管MA11漏极与PMOS管MA14漏极相连，源极与地相连，NMOS管MA9栅极与时钟相连，漏极与NMOS管MA10漏极相连，源极与地相连，NMOS管MA12栅极与时钟相连，漏极与NMOS管MA11漏极相连，源极与地相连。The source of the PMOS tube MA1 is connected to the power supply, the gate is connected to the gate of the PMOS tube MA2, the drain is connected to the drain of the NMOS tube MA3, the source of the PMOS tube MA2 is connected to the power supply, the gate is connected to the clock, and the drain is connected to the drain of the NMOS tube MA4 Connected, the gate of the NMOS tube MA3 is connected to the input, the source is connected to the drain of the NMOS tube MA5, the gate of the NMOS tube MA4 is connected to the input, the source is connected to the drain of the NMOS tube MA6, and one end of the resistor R1 is connected to the source of the NMOS tube MA3 The other end is connected to the source of the NMOS tube MA4, the gate of the NMOS tube MA5 is connected to the clock, the source is connected to the ground, the gate of the NMOS tube MA6 is connected to the clock, the source is connected to the ground, the source of the PMOS tube MA7 is connected to the power supply, The gate is connected to the gate of the NMOS tube MA10, the drain is connected to the source of the PMOS tube MA13, the source of the PMOS tube MA8 is connected to the power supply, the gate is connected to the gate of the NMOS tube MA11, the drain is connected to the source of the PMOS tube MA14, and the PMOS tube The gate of MA13 is connected to the drain of the NMOS tube MA4, the drain is connected to the gate of the NMOS tube MA11, the gate of the PMOS tube MA14 is connected to the drain of the NMOS tube MA3, the drain is connected to the gate of the NMOS tube MA10, and the drain of the NMOS tube MA10 is connected to The drain of the PMOS transistor MA13 is connected to the drain, the source is connected to the ground, the drain of the NMOS transistor MA11 is connected to the drain of the PMOS transistor MA14, the source is connected to the ground, the gate of the NMOS transistor MA9 is connected to the clock, and the drain is connected to the drain of the NMOS transistor MA10 , the source is connected to the ground, the gate of the NMOS tube MA12 is connected to the clock, the drain is connected to the drain of the NMOS tube MA11, and the source is connected to the ground.
与现有技术相比，本实用新型的技术方案具有以下有益效果：Compared with the prior art, the technical scheme of the present utility model has the following beneficial effects:
本实用新型分别从提高带隙基准源的曲率补偿与提升比较器的线性度出发，分析出了模数转换器的特性以及线性度度和曲率补偿所需要的电路结构。针对了目前的电路结构使用了采样保持电路(103)，改进的基准电路(101)，DAC电路(100)，改进的比较器电路(102)，逻辑控制(104)，利用了VBE的高阶项系数与电阻提升线性度的特性，设计出了一种提升线性度的逐次逼近性ADC结构。模数转换器电路线性度不够，DAC基准曲率补偿不够等问题。The utility model analyzes the characteristics of the analog-to-digital converter and the circuit structure required for the linearity and the curvature compensation respectively starting from improving the curvature compensation of the bandgap reference source and improving the linearity of the comparator. Aiming at the current circuit structure, a sample and hold circuit (103), an improved reference circuit (101), a DAC circuit (100), an improved comparator circuit (102), and a logic control ( 104 ) are used. The characteristic of order term coefficient and resistance to improve the linearity, a successive approximation ADC structure is designed to improve the linearity. The linearity of the analog-to-digital converter circuit is not enough, and the DAC reference curvature compensation is not enough.
附图说明Description of drawings
图1为本实用新型一种提升线性度的逐次逼近性ADC结构示意图；1 is a schematic structural diagram of a successive approximation ADC for improving linearity of the present invention;
图2为本实用新型改进的基准电路的示意图；Fig. 2 is the schematic diagram of the reference circuit improved by the utility model;
图3为本实用新型改进的比较器电路的示意图。FIG. 3 is a schematic diagram of the improved comparator circuit of the present invention.
具体实施方式Detailed ways
为了进一步的介绍本实用新型的具体内容，电路的结构特性，以及解决现有的电路线性度不够，基准曲率补偿不够等问题。具体结合附图对本实用新型进行详述：In order to further introduce the specific content of the present utility model, the structural characteristics of the circuit, and solve the problems of insufficient linearity and insufficient reference curvature compensation of the existing circuit. The utility model is described in detail in conjunction with the accompanying drawings:
本实用新型提供了一种提升线性度的逐次逼近性ADC结构，用于解决电路线性度和曲率补偿的问题。如图1为本实用新型一种提升线性度的逐次逼近性ADC结构示意图，包括采样保持电路(103)，改进的基准电路(101)，DAC电路(100)，改进的比较器电路(102)，逻辑控制(104)。The utility model provides a successive approximation ADC structure with improved linearity, which is used for solving the problems of circuit linearity and curvature compensation. FIG. 1 is a schematic structural diagram of a successive approximation ADC for improving linearity of the present invention, including a sample and hold circuit (103), an improved reference circuit (101), a DAC circuit (100), and an improved comparator circuit (102) , logic control (104).
改进的基准电路(101)，用来产生一个正常工作的基准电压，传输利用改变的电压值所产生的正温度系数电压，得到具有正温度系数的补偿电流与器件本身所具有负温度系数的补偿电流，利用两个相加的值对产生的带隙电流进行温度补偿，与其他曲率补偿相比简化了电路结构，减少了可能导致输出电流产生温度漂移的可能。The improved reference circuit (101) is used to generate a normal working reference voltage, transmit the positive temperature coefficient voltage generated by using the changed voltage value, and obtain the compensation current with a positive temperature coefficient and the compensation of the negative temperature coefficient of the device itself Compared with other curvature compensations, the circuit structure is simplified and the possibility of temperature drift that may cause the output current is reduced.
改进比较器电路(102)，通过提高比较器的工作速率，采用正反馈再生结构来提高比较器工作速率上限，加入电阻提升线性输入范围，从而得到线性度更高的数据。By improving the comparator circuit (102), the operating rate of the comparator is increased, a positive feedback regeneration structure is used to increase the upper limit of the operating rate of the comparator, and a resistor is added to improve the linear input range, thereby obtaining data with higher linearity.
图2为本实用新型改进的基准电路结构的示意图，由图可知改进的基准电路(101)包括PMOS管M1、PMOS管M2、PMOS管M5、电阻R1、电阻R5、电阻R6、电阻R7、电阻R8、电阻R10、BJT管M19、BJT管M20、PMOS管M4、BJT管M21、电阻R3、电阻R4、PMOS管M3；2 is a schematic diagram of the improved reference circuit structure of the present utility model. It can be seen from the figure that the improved reference circuit (101) includes a PMOS tube M1, a PMOS tube M2, a PMOS tube M5, a resistor R1, a resistor R5, a resistor R6, a resistor R7, a resistor R8, resistor R10, BJT tube M19, BJT tube M20, PMOS tube M4, BJT tube M21, resistor R3, resistor R4, PMOS tube M3;
PMOS管M1源极接电源，栅极与PMOS管M2、M5栅极相连，漏极与电阻R10一端相连，M2源极与电源相连，漏极与电阻R8一端相连，PMOS管M5源极与电源相连，漏极与电阻R6一端相连，电阻R1一端与R7另一端相连，另一端与地相连，电阻R5一端与R8另一端相连，另一端与地相连，电阻R6另一端与地相连，电阻R10另一端与电阻R7相连，BJT管M19基极与地相连，集电极与地相连，发射极与R7另一端相连，BJT管M20基极与地相连，集电极与地相连，发射极与R8另一端相连，PMOS管M4源极接电源，栅极与PMOS管M1栅极相连，漏极与BJT管M21发射极相连，BJT管M21基极与地相连，集电极与地相连，电阻R3一端与PMOS管M12栅极相连，电阻R4一端与PMOS管M13栅极相连，PMOS管M3源极接电源，栅极与M1栅极相连，漏极与BJT管M20发射极相连。The source of the PMOS tube M1 is connected to the power supply, the gate is connected to the gates of the PMOS tubes M2 and M5, the drain is connected to one end of the resistor R10, the source of M2 is connected to the power supply, the drain is connected to one end of the resistor R8, and the source of the PMOS tube M5 is connected to the power supply Connected, the drain is connected to one end of resistor R6, one end of resistor R1 is connected to the other end of R7, the other end is connected to ground, one end of resistor R5 is connected to the other end of R8, the other end is connected to ground, the other end of resistor R6 is connected to ground, the other end of resistor R10 The other end is connected to resistor R7, the base of BJT tube M19 is connected to ground, the collector is connected to ground, the emitter is connected to the other end of R7, the base of BJT tube M20 is connected to ground, the collector is connected to ground, and the emitter is connected to R8. One end is connected, the source of the PMOS tube M4 is connected to the power supply, the gate is connected to the gate of the PMOS tube M1, the drain is connected to the emitter of the BJT tube M21, the base of the BJT tube M21 is connected to the ground, the collector is connected to the ground, and one end of the resistor R3 is connected to The gate of the PMOS tube M12 is connected to the gate, one end of the resistor R4 is connected to the gate of the PMOS tube M13, the source of the PMOS tube M3 is connected to the power supply, the gate is connected to the gate of M1, and the drain is connected to the emitter of the BJT tube M20.
图3为本实用新型改进的比较器电路结构的示意图，由图可知改进的比较器电路(102)包括PMOS管MA1、PMOS管MA2、PMOS管MA7、PMOS管MA8、PMOS管MA13、PMOS管MA14、NMOS管MA3、NMOS管MA4、NMOS管MA5、NMOS管MA6、NMOS管MA9、NMOS管MA10、NMOS管MA11、NMOS管MA12、电阻R1；3 is a schematic diagram of the improved comparator circuit structure of the present invention. It can be seen from the figure that the improved comparator circuit (102) includes a PMOS tube MA1, a PMOS tube MA2, a PMOS tube MA7, a PMOS tube MA8, a PMOS tube MA13, and a PMOS tube MA14 , NMOS tube MA3, NMOS tube MA4, NMOS tube MA5, NMOS tube MA6, NMOS tube MA9, NMOS tube MA10, NMOS tube MA11, NMOS tube MA12, resistor R1;
PMOS管MA1源极接电源，栅极与PMOS管MA2栅极相连，漏极与NMOS管MA3漏极相连，PMOS管MA2源极接电源，栅极与时钟相连，漏极与NMOS管MA4漏极相连，NMOS管MA3栅极与输入相连，源极与NMOS管MA5漏极相连，NMOS管MA4栅极与输入相连，源极与NMOS管MA6漏极相连，电阻R1，一端与NMOS管MA3源极相连，另一端与NMOS管MA4源极相连，NMOS管MA5栅极与时钟相连，源极与地相连，NMOS管MA6栅极与时钟相连，源极与地相连，PMOS管MA7源极接电源，栅极与NMOS管MA10栅极相连，漏极与PMOS管MA13源极相连，PMOS管MA8源极接电源，栅极与NMOS管MA11栅极相连，漏极与PMOS管MA14源极相连，PMOS管MA13栅极与NMOS管MA4漏极相连，漏极与NMOS管MA11栅极相连，PMOS管MA14栅极与NMOS管MA3漏极相连，漏极与NMOS管MA10栅极相连，NMOS管MA10漏极与PMOS管MA13漏极相连，源极与地相连，NMOS管MA11漏极与PMOS管MA14漏极相连，源极与地相连，NMOS管MA9栅极与时钟相连，漏极与NMOS管MA10漏极相连，源极与地相连，NMOS管MA12栅极与时钟相连，漏极与NMOS管MA11漏极相连，源极与地相连。The source of the PMOS tube MA1 is connected to the power supply, the gate is connected to the gate of the PMOS tube MA2, the drain is connected to the drain of the NMOS tube MA3, the source of the PMOS tube MA2 is connected to the power supply, the gate is connected to the clock, and the drain is connected to the drain of the NMOS tube MA4 Connected, the gate of the NMOS tube MA3 is connected to the input, the source is connected to the drain of the NMOS tube MA5, the gate of the NMOS tube MA4 is connected to the input, the source is connected to the drain of the NMOS tube MA6, and one end of the resistor R1 is connected to the source of the NMOS tube MA3 The other end is connected to the source of the NMOS tube MA4, the gate of the NMOS tube MA5 is connected to the clock, the source is connected to the ground, the gate of the NMOS tube MA6 is connected to the clock, the source is connected to the ground, the source of the PMOS tube MA7 is connected to the power supply, The gate is connected to the gate of the NMOS tube MA10, the drain is connected to the source of the PMOS tube MA13, the source of the PMOS tube MA8 is connected to the power supply, the gate is connected to the gate of the NMOS tube MA11, the drain is connected to the source of the PMOS tube MA14, and the PMOS tube The gate of MA13 is connected to the drain of the NMOS tube MA4, the drain is connected to the gate of the NMOS tube MA11, the gate of the PMOS tube MA14 is connected to the drain of the NMOS tube MA3, the drain is connected to the gate of the NMOS tube MA10, and the drain of the NMOS tube MA10 is connected to The drain of the PMOS transistor MA13 is connected to the drain, the source is connected to the ground, the drain of the NMOS transistor MA11 is connected to the drain of the PMOS transistor MA14, the source is connected to the ground, the gate of the NMOS transistor MA9 is connected to the clock, and the drain is connected to the drain of the NMOS transistor MA10 , the source is connected to the ground, the gate of the NMOS tube MA12 is connected to the clock, the drain is connected to the drain of the NMOS tube MA11, and the source is connected to the ground.
综上所述为本实用新型的具体实施方案，本实用新型的原理已叙述在以上的说明之中，本实用新型的保护范围不仅仅局限于此，本专业领域的任何设计人员在本实用新型的披露范围内做出的简单的结构变化，均属于本次实用新型之内，因此，本实用新型的保护范围应以权利要求书的范围为准。To sum up, the above are the specific embodiments of the present utility model, the principle of the present utility model has been described in the above description, the protection scope of the present utility model is not limited to this, any designer in the field of the present utility model The simple structural changes made within the disclosure scope of the present invention all belong to the present utility model. Therefore, the protection scope of the present utility model should be based on the scope of the claims.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822120446.4U CN209170344U (en) | 2018-12-18 | 2018-12-18 | A successive approximation ADC structure to improve linearity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822120446.4U CN209170344U (en) | 2018-12-18 | 2018-12-18 | A successive approximation ADC structure to improve linearity |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209170344U true CN209170344U (en) | 2019-07-26 |
Family
ID=67344178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822120446.4U Expired - Fee Related CN209170344U (en) | 2018-12-18 | 2018-12-18 | A successive approximation ADC structure to improve linearity |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209170344U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115842554A (en) * | 2023-02-21 | 2023-03-24 | 深圳市南方硅谷半导体股份有限公司 | Successive approximation type analog-to-digital converter |
| CN116614135A (en) * | 2023-05-18 | 2023-08-18 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Dynamic comparator suitable for synchronous sequential SAR ADC and control method |
-
2018
- 2018-12-18 CN CN201822120446.4U patent/CN209170344U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115842554A (en) * | 2023-02-21 | 2023-03-24 | 深圳市南方硅谷半导体股份有限公司 | Successive approximation type analog-to-digital converter |
| CN116614135A (en) * | 2023-05-18 | 2023-08-18 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Dynamic comparator suitable for synchronous sequential SAR ADC and control method |
| CN116614135B (en) * | 2023-05-18 | 2024-04-09 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Dynamic comparator suitable for synchronous sequential SAR ADC and control method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Chen et al. | A 0.7-V 0.6-$\mu\text {W} $100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction | |
| CN105306059B (en) | Successive approximation analog-to-digital converter device | |
| CN110311680A (en) | Anti-PVT Fluctuation Adaptive SAR ADC Circuit and Estimation Method for Low Vref Input | |
| Li et al. | A 7-bit 900-MS/s 2-then-3-bit/cycle SAR ADC with background offset calibration | |
| CN111654288A (en) | A two-stage full dynamic comparator for SAR ADC and its working method | |
| CN101924540B (en) | Differential time domain comparator circuit | |
| Harpe et al. | A 0.8-mW 5-bit 250-MS/s time-interleaved asynchronous digital slope ADC | |
| CN107453756B (en) | Front-end calibration method for pipeline ADC | |
| CN209170344U (en) | A successive approximation ADC structure to improve linearity | |
| CN106330184A (en) | A Current Steering DAC Based on Dynamic Error Correction Technology | |
| CN110401447B (en) | An Op-ampless MDAC Time Domain ADC Structure | |
| CN102832939A (en) | ADC (Analog to Digital Converter) | |
| Al Smadi | Design and implementation of double base integer encoder of term metrical to direct binary | |
| CN106953638B (en) | Correction circuit for input parasitic capacitance of comparator | |
| Park et al. | A 12-bit 125-MS/s 2.5-bit/cycle SAR-based pipeline ADC employing a self-biased gain boosting amplifier | |
| Gupta et al. | Implementation of low supply rail-to-rail differential voltage comparator on flexible hardware for a flash adc | |
| CN110266310B (en) | Time domain comparator capable of automatically adjusting power consumption | |
| Fani et al. | A 1-V 5-bit 0.5 GS/s time-based flash ADC in 0.18 µm CMOS technology | |
| Yu et al. | An energy‐efficient switching scheme based on distributing most significant bit capacitors for successive approximation register analog‐to‐digital converter | |
| CN110190853B (en) | First-order modulator based on static pre-amplifier integrator | |
| Wu et al. | A 7 bit 800MS/S SAR ADC with background offset calibration | |
| Firouzkouhi et al. | A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch | |
| Khoshakhlagh et al. | An efficient threshold voltage generation for SAR ADCs | |
| Song et al. | A 14 bit 10 MS/s TI SAR ADC with neural network calibration | |
| Singh et al. | Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190726 Termination date: 20191218 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |