CN209170344U - A kind of Approach by inchmeal ADC structure promoting the linearity - Google Patents
A kind of Approach by inchmeal ADC structure promoting the linearity Download PDFInfo
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- CN209170344U CN209170344U CN201822120446.4U CN201822120446U CN209170344U CN 209170344 U CN209170344 U CN 209170344U CN 201822120446 U CN201822120446 U CN 201822120446U CN 209170344 U CN209170344 U CN 209170344U
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Abstract
The utility model discloses a kind of Approach by inchmeal ADC structures for promoting the linearity, including sampling hold circuit (103), improved reference circuit (101), DAC circuit (100), improved comparator circuit (102), logic control (104), by will be maintained on sampling capacitance and export to back-end circuit after analog signal level intelligence sample.Later by capacitor array and switch arrays, binary search algorithm is completed.The reference voltage of DAC is the high-precision band gap reference with temperature-compensating.Comparator utilizes the latched comparator with preamplifier, can obtain relatively good overall noise Misalignment Characteristics, possess the power consumption much smaller than static comparison device.Logical gate uses asynchronous SAR control logic circuit, avoids external high-frequency clock, reduces the power consumption and noise jamming of clock circuit.The utility model has compared with common adc circuit possesses very big difference, and the characteristics such as improved circuit power consumption, the linearity have obtained very big improvement.
Description
Technical field
The utility model relates to a kind of Approach by inchmeal ADC structures for promoting the linearity, including sampling hold circuit
(103), improved reference circuit (101), DAC circuit (100), improved comparator circuit (102), logic control (104) belong to
In analogue layout and field of integrated system.
Background technique
Since modern science and technology, analogue layout has become the important composition portion in people's daily life
Point.When integrated circuit technology level constantly increases, promoting the linearity and reducing the performances such as power consumption will be realized, in order to
Keep product more excellent, is suitable for the new demand in market, IC designers, which generally believe, to reduce power consumption and promoted linear
Degree is a kind of method for improving circuit integral level, and the only small influence to circuit.Simultaneously because setting at present
Meter teachers have higher requirement to the function of circuit and accuracy, so the linearity promotion of circuit just seems especially heavy
It wants.
Utility model content
The purpose of this utility model with overcome the deficiencies of the prior art and provide it is a kind of promoted the linearity Approach by inchmeal
Property ADC structure, improve the linearity of circuit simultaneously on the basis of original, and use bandgap reference voltage as DAC
Input voltage so that the range of linearity of circuit becomes larger.
The above-mentioned purpose of the utility model is mainly to be realized by scheme below:
A kind of Approach by inchmeal ADC structure promoting the linearity, it is characterised in that: including sampling hold circuit (103), change
Into reference circuit (101), DAC circuit (100), improved comparator circuit (102), logic control (104), in which:
Sampling hold circuit (103): being kept for the stage, closed the switch, and switch disconnects.Sample phase, switch disconnect, and switch closes
It closes.Analog input signal is sampled and kept, then the value of holding is sent to one end of improved comparator circuit (102)；
Improved reference circuit (101): the high-precision band gap current reference with temperature-compensating is generated, is sent
Give DAC circuit (100)；
Improved comparator circuit (102): generate 1 or 0, the value compared is sent to logic control (104), it is laggard
Row numeral output；
DAC circuit (100): by capacitor array and switch arrays, binary search algorithm is completed, the value of calculating is sent
To the other end of improved comparator circuit (102)；
Improved comparator circuit (102):, can be with using first order pre-amplification by pre-amplification structure and latch structure
The noise for inhibiting latched comparator well, obtains relatively good overall noise Misalignment Characteristics, will by comparing output 1 or 0
The value compared is sent to logic control (104), carries out numeral output later；
Logic control (104): final analog-to-digital conversion is carried out by asynchronous SAR control logic circuit.
In a kind of Approach by inchmeal ADC structure of above-mentioned promotion linearity, the improved reference circuit (101) is adopted
With curvature compensation, V is had ignoredBEInfluence of the higher order term to band-gap circuit.
In a kind of Approach by inchmeal ADC structure of above-mentioned promotion linearity, the improved comparator circuit (102)
Using the front linear differential pair structure for introducing resistance, linear input range is improved.
In a kind of Approach by inchmeal ADC structure of above-mentioned promotion linearity, the improved reference circuit (101)
Including PMOS tube M1, PMOS tube M2, PMOS tube M5, resistance R1, resistance R5, resistance R6, resistance R7, resistance R8, resistance R10, BJT
Pipe M19, BJT pipe M20, PMOS tube M4, BJT pipe M21, resistance R3, resistance R4, PMOS tube M3；
PMOS tube M1 source electrode connects power supply, and grid is connected with PMOS tube M2, M5 grid, and drain electrode is connected with the one end resistance R10, M2
Source electrode is connected with power supply, and drain electrode is connected with the one end resistance R8, and PMOS tube M5 source electrode is connected with power supply, drain electrode and the one end resistance R6 phase
Even, the one end resistance R1 is connected with the R7 other end, and the other end is connected to the ground, and the one end resistance R5 is connected with the R8 other end, the other end and
Ground is connected, and the resistance R6 other end is connected to the ground, and the resistance R10 other end is connected with resistance R7, and BJT pipe M19 base stage is connected to the ground, collection
Electrode is connected to the ground, and emitter is connected with the R7 other end, and BJT pipe M20 base stage is connected to the ground, and collector is connected to the ground, emitter
It is connected with the R8 other end, PMOS tube M4 source electrode connects power supply, and grid is connected with PMOS tube M1 grid, drain electrode and BJT pipe M21 emitter
It is connected, BJT pipe M21 base stage is connected to the ground, and collector is connected to the ground, and the one end resistance R3 is connected with PMOS tube M12 grid, resistance R4
One end is connected with PMOS tube M13 grid, and PMOS tube M3 source electrode connects power supply, and grid is connected with M1 grid, and drain electrode is sent out with BJT pipe M20
Emitter-base bandgap grading is connected.
In a kind of Approach by inchmeal ADC structure of above-mentioned promotion linearity, the improved comparator circuit
It (102) include PMOS tube MA1, PMOS tube MA2, PMOS tube MA7, PMOS tube MA8, PMOS tube MA13, PMOS tube MA14, NMOS tube
MA3, NMOS tube MA4, NMOS tube MA5, NMOS tube MA6, NMOS tube MA9, NMOS tube MA10, NMOS tube MA11, NMOS tube MA12,
Resistance R1；
PMOS tube MA1 source electrode connects power supply, and grid is connected with PMOS tube MA2 grid, and drain electrode is connected with NMOS tube MA3 drain electrode,
PMOS tube MA2 source electrode connects power supply, and grid is connected with clock, drain electrode with NMOS tube MA4 drain is connected, NMOS tube MA3 grid with it is defeated
Enter connected, source electrode and NMOS tube MA5 drain electrode are connected, and NMOS tube MA4 grid is connected with inputting, source electrode and NMOS tube MA6 drain electrode phase
Even, resistance R1, one end is connected with NMOS tube MA3 source electrode, and the other end is connected with NMOS tube MA4 source electrode, NMOS tube MA5 grid and when
Clock is connected, and source electrode is connected to the ground, and NMOS tube MA6 grid is connected with clock, and source electrode is connected to the ground, and PMOS tube MA7 source electrode connects power supply,
Grid is connected with NMOS tube MA10 grid, and drain electrode is connected with PMOS tube MA13 source electrode, and PMOS tube MA8 source electrode connects power supply, grid and
NMOS tube MA11 grid is connected, and drain electrode is connected with PMOS tube MA14 source electrode, PMOS tube MA13 grid and NMOS tube MA4 drain electrode phase
Even, drain electrode is connected with NMOS tube MA11 grid, and PMOS tube MA14 grid is connected with NMOS tube MA3 drain electrode, drain electrode and NMOS tube
MA10 grid be connected, NMOS tube MA10 drain electrode with PMOS tube MA13 drain electrode is connected, source electrode is connected to the ground, NMOS tube MA11 drain and
PMOS tube MA14 drain electrode is connected, and source electrode is connected to the ground, and NMOS tube MA9 grid is connected with clock, and drain electrode drains with NMOS tube MA10
It is connected, source electrode is connected to the ground, and NMOS tube MA12 grid is connected with clock, and drain electrode is connected with NMOS tube MA11 drain electrode, source electrode and ground
It is connected.
Compared with prior art, the technical solution of the utility model has the advantages that
The utility model is respectively from the linearity of the curvature compensation and promotion comparator that improve band gap reference, analysis
Gone out analog-digital converter characteristic and linearity degree and curvature compensation required for circuit structure.It has been directed to current circuit knot
Structure has used sampling hold circuit (103), improved reference circuit (101), DAC circuit (100), improved comparator circuit
(102), logic control (104), are utilized VBEHigh-order term coefficient and resistance promoted the linearity characteristic, have devised one kind and mention
Rise the Approach by inchmeal ADC structure of the linearity.The analog-digital converter circuit linearity is inadequate, and DAC benchmark curvature compensation not enough etc. is asked
Topic.
Detailed description of the invention
Fig. 1 is a kind of Approach by inchmeal ADC structural schematic diagram for promoting the linearity of the utility model；
Fig. 2 is the schematic diagram of the improved reference circuit of the utility model；
Fig. 3 is the schematic diagram of the improved comparator circuit of the utility model.
Specific embodiment
In order to further introduce the particular content of the utility model, the architectural characteristic of circuit, and the existing electricity of solution
The problems such as linear degree is inadequate, and benchmark curvature compensation is inadequate.Specifically the utility model is described in detail in conjunction with attached drawing:
The utility model provides a kind of Approach by inchmeal ADC structure for promoting the linearity, for solving circuit linearity degree
And the problem of curvature compensation.If Fig. 1 is a kind of Approach by inchmeal ADC structural schematic diagram for promoting the linearity of the utility model, packet
It includes sampling hold circuit (103), improved reference circuit (101), DAC circuit (100), improved comparator circuit (102) is patrolled
Collect control (104).
Improved reference circuit (101), for generating the reference voltage of a normal work, transmission utilizes the voltage changed
Positive temperature coefficient voltage, obtains the compensation electric current with positive temperature coefficient and the had negative temperature system of device itself caused by being worth
Several compensation electric currents, the value being added using two carries out temperature-compensating to the bandgap current of generation, compared with other curvature compensations
Circuit structure is simplified, reduces and may cause the possibility that output electric current generates temperature drift.
It improves comparator circuit (102), by improving the operating rate of comparator, is improved using positive feedback revived structure
The comparator operating rate upper limit is added resistance and promotes linear input range, to obtain the higher data of the linearity.
Fig. 2 is the schematic diagram of the improved reference circuit structure of the utility model, as seen from the figure improved reference circuit (101)
Including PMOS tube M1, PMOS tube M2, PMOS tube M5, resistance R1, resistance R5, resistance R6, resistance R7, resistance R8, resistance R10, BJT
Pipe M19, BJT pipe M20, PMOS tube M4, BJT pipe M21, resistance R3, resistance R4, PMOS tube M3；
PMOS tube M1 source electrode connects power supply, and grid is connected with PMOS tube M2, M5 grid, and drain electrode is connected with the one end resistance R10, M2
Source electrode is connected with power supply, and drain electrode is connected with the one end resistance R8, and PMOS tube M5 source electrode is connected with power supply, drain electrode and the one end resistance R6 phase
Even, the one end resistance R1 is connected with the R7 other end, and the other end is connected to the ground, and the one end resistance R5 is connected with the R8 other end, the other end and
Ground is connected, and the resistance R6 other end is connected to the ground, and the resistance R10 other end is connected with resistance R7, and BJT pipe M19 base stage is connected to the ground, collection
Electrode is connected to the ground, and emitter is connected with the R7 other end, and BJT pipe M20 base stage is connected to the ground, and collector is connected to the ground, emitter
It is connected with the R8 other end, PMOS tube M4 source electrode connects power supply, and grid is connected with PMOS tube M1 grid, drain electrode and BJT pipe M21 emitter
It is connected, BJT pipe M21 base stage is connected to the ground, and collector is connected to the ground, and the one end resistance R3 is connected with PMOS tube M12 grid, resistance R4
One end is connected with PMOS tube M13 grid, and PMOS tube M3 source electrode connects power supply, and grid is connected with M1 grid, and drain electrode is sent out with BJT pipe M20
Emitter-base bandgap grading is connected.
Fig. 3 is the schematic diagram of the improved comparator circuit structure of the utility model, as seen from the figure improved comparator circuit
It (102) include PMOS tube MA1, PMOS tube MA2, PMOS tube MA7, PMOS tube MA8, PMOS tube MA13, PMOS tube MA14, NMOS tube
MA3, NMOS tube MA4, NMOS tube MA5, NMOS tube MA6, NMOS tube MA9, NMOS tube MA10, NMOS tube MA11, NMOS tube MA12,
Resistance R1；
PMOS tube MA1 source electrode connects power supply, and grid is connected with PMOS tube MA2 grid, and drain electrode is connected with NMOS tube MA3 drain electrode,
PMOS tube MA2 source electrode connects power supply, and grid is connected with clock, drain electrode with NMOS tube MA4 drain is connected, NMOS tube MA3 grid with it is defeated
Enter connected, source electrode and NMOS tube MA5 drain electrode are connected, and NMOS tube MA4 grid is connected with inputting, source electrode and NMOS tube MA6 drain electrode phase
Even, resistance R1, one end is connected with NMOS tube MA3 source electrode, and the other end is connected with NMOS tube MA4 source electrode, NMOS tube MA5 grid and when
Clock is connected, and source electrode is connected to the ground, and NMOS tube MA6 grid is connected with clock, and source electrode is connected to the ground, and PMOS tube MA7 source electrode connects power supply,
Grid is connected with NMOS tube MA10 grid, and drain electrode is connected with PMOS tube MA13 source electrode, and PMOS tube MA8 source electrode connects power supply, grid and
NMOS tube MA11 grid is connected, and drain electrode is connected with PMOS tube MA14 source electrode, PMOS tube MA13 grid and NMOS tube MA4 drain electrode phase
Even, drain electrode is connected with NMOS tube MA11 grid, and PMOS tube MA14 grid is connected with NMOS tube MA3 drain electrode, drain electrode and NMOS tube
MA10 grid be connected, NMOS tube MA10 drain electrode with PMOS tube MA13 drain electrode is connected, source electrode is connected to the ground, NMOS tube MA11 drain and
PMOS tube MA14 drain electrode is connected, and source electrode is connected to the ground, and NMOS tube MA9 grid is connected with clock, and drain electrode drains with NMOS tube MA10
It is connected, source electrode is connected to the ground, and NMOS tube MA12 grid is connected with clock, and drain electrode is connected with NMOS tube MA11 drain electrode, source electrode and ground
It is connected.
It is in summary the specific embodiment of the utility model, the principles of the present invention are described in above explanation
Among, the protection scope of the utility model is not limited solely to this, and any designer of this professional domain is in the utility model
Disclosure within the scope of the simple structure change made, belong within this utility model, therefore, the protection of the utility model
Range should be subject to the range of claims.
Claims (8)
1. a kind of Approach by inchmeal ADC structure for promoting the linearity, it is characterised in that: including sampling hold circuit (103), improve
Reference circuit (101), DAC circuit (100), improved comparator circuit (102), logic control (104), in which:
Sampling hold circuit (103): being kept for the stage, closed the switch, and switch disconnects；Sample phase, switch are disconnected, are closed the switch；
Analog input signal is sampled and kept, then the value of holding is sent to one end of improved comparator circuit (102)；
Improved reference circuit (101): the high-precision band gap current reference with temperature-compensating is generated, is sent to
DAC circuit (100)；
Improved comparator circuit (102): 1 or 0 is generated, the value compared is sent to logic control (104), is counted later
Word output；
DAC circuit (100): by capacitor array and switch arrays, binary search algorithm is completed, the value of calculating is sent to and is changed
Into comparator circuit (102) the other end；
Improved comparator circuit (102):, can be fine using first order pre-amplification by pre-amplification structure and latch structure
Ground inhibits the noise of latched comparator, obtains relatively good overall noise Misalignment Characteristics, by comparing output 1 or 0, will compare
Value be sent to logic control (104), carry out numeral output later；
Logic control (104): final analog-to-digital conversion is carried out by asynchronous SAR control logic circuit.
2. a kind of Approach by inchmeal ADC structure for promoting the linearity according to claim 1, it is characterised in that: described to adopt
Sample holding circuit (103) is Bootstrap formula switch, keeps stage bootstrap capacitor both ends to connect power supply and ground respectively, sample phase is certainly
Lift the grid and source electrode of capacitance connection transistor；Since the charge in bootstrap capacitor is constant, so the voltage at bootstrap capacitor both ends
Always it is supply voltage, realizes grid voltage and immobilize, reduce the nonlinear change of conducting resistance, improves the line of sample circuit
Property degree.
3. a kind of Approach by inchmeal ADC structure for promoting the linearity according to claim 1, it is characterised in that: the DAC
Circuit (100) uses the capacitive DAC of fully differential, inhibits substrate noise and power supply noise, avoids the generation of common-mode noise, can be with
It is effectively prevented from quiescent dissipation and dynamic power consumption.
4. a kind of Approach by inchmeal ADC structure for promoting the linearity according to claim 1, it is characterised in that: described to change
Into reference circuit (101) use curvature compensation band-gap circuit structure, generate a temperature independent reference voltage.
5. a kind of Approach by inchmeal ADC structure for promoting the linearity according to claim 1, it is characterised in that: described to change
Into comparator circuit (102) use the latched comparator with preamplifier, pass through improve differential pair introduce resistance, modify line
Property range promoted the linearity.
6. a kind of Approach by inchmeal ADC structure for promoting the linearity according to claim 1, it is characterised in that: described to patrol
It collects control (104) and uses asynchronous SAR control logic circuit, the power consumption of clock circuit can be reduced to avoid external high-frequency clock
And noise jamming；Shift control and data lock can be met simultaneously by increasing transistor on data latch unit circuit base
It deposits.
7. a kind of Approach by inchmeal ADC structure of the promotion linearity described according to claim 1 ~ one of 6, it is characterised in that:
The improved reference circuit (101) include PMOS tube M1, PMOS tube M2, PMOS tube M5, resistance R1, resistance R5, resistance R6,
Resistance R7, resistance R8, resistance R10, BJT pipe M19, BJT pipe M20, PMOS tube M4, BJT pipe M21, resistance R3, resistance R4, PMOS
Pipe M3；
Wherein PMOS tube M1 source electrode connects power supply, and grid is connected with PMOS tube M2, M5 grid, and drain electrode is connected with the one end resistance R10, M2
Source electrode is connected with power supply, and drain electrode is connected with the one end resistance R8, and PMOS tube M5 source electrode is connected with power supply, drain electrode and the one end resistance R6 phase
Even, the one end resistance R1 is connected with the R7 other end, and the other end is connected to the ground, and the one end resistance R5 is connected with the R8 other end, the other end and
Ground is connected, and the resistance R6 other end is connected to the ground, and the resistance R10 other end is connected with resistance R7, and BJT pipe M19 base stage is connected to the ground, collection
Electrode is connected to the ground, and emitter is connected with the R7 other end, and BJT pipe M20 base stage is connected to the ground, and collector is connected to the ground, emitter
It is connected with the R8 other end, PMOS tube M4 source electrode connects power supply, and grid is connected with PMOS tube M1 grid, drain electrode and BJT pipe M21 emitter
It is connected, BJT pipe M21 base stage is connected to the ground, and collector is connected to the ground, and the one end resistance R3 is connected with PMOS tube M12 grid, resistance R4
One end is connected with PMOS tube M13 grid, and PMOS tube M3 source electrode connects power supply, and grid is connected with M1 grid, and drain electrode is sent out with BJT pipe M20
Emitter-base bandgap grading is connected.
8. a kind of Approach by inchmeal ADC structure of the promotion linearity described according to claim 1 ~ one of 6, it is characterised in that:
The improved comparator circuit (102) includes PMOS tube MA1, PMOS tube MA2, PMOS tube MA7, PMOS tube MA8, PMOS tube
MA13, PMOS tube MA14, NMOS tube MA3, NMOS tube MA4, NMOS tube MA5, NMOS tube MA6, NMOS tube MA9, NMOS tube MA10,
NMOS tube MA11, NMOS tube MA12, resistance R1；
Wherein PMOS tube MA1 source electrode connects power supply, and grid is connected with PMOS tube MA2 grid, and drain electrode is connected with NMOS tube MA3 drain electrode,
PMOS tube MA2 source electrode connects power supply, and grid is connected with clock, drain electrode with NMOS tube MA4 drain is connected, NMOS tube MA3 grid with it is defeated
Enter connected, source electrode and NMOS tube MA5 drain electrode are connected, and NMOS tube MA4 grid is connected with inputting, source electrode and NMOS tube MA6 drain electrode phase
Even, resistance R1, one end is connected with NMOS tube MA3 source electrode, and the other end is connected with NMOS tube MA4 source electrode, NMOS tube MA5 grid and when
Clock is connected, and source electrode is connected to the ground, and NMOS tube MA6 grid is connected with clock, and source electrode is connected to the ground, and PMOS tube MA7 source electrode connects power supply,
Grid is connected with NMOS tube MA10 grid, and drain electrode is connected with PMOS tube MA13 source electrode, and PMOS tube MA8 source electrode connects power supply, grid and
NMOS tube MA11 grid is connected, and drain electrode is connected with PMOS tube MA14 source electrode, PMOS tube MA13 grid and NMOS tube MA4 drain electrode phase
Even, drain electrode is connected with NMOS tube MA11 grid, and PMOS tube MA14 grid is connected with NMOS tube MA3 drain electrode, drain electrode and NMOS tube
MA10 grid be connected, NMOS tube MA10 drain electrode with PMOS tube MA13 drain electrode is connected, source electrode is connected to the ground, NMOS tube MA11 drain and
PMOS tube MA14 drain electrode is connected, and source electrode is connected to the ground, and NMOS tube MA9 grid is connected with clock, and drain electrode drains with NMOS tube MA10
It is connected, source electrode is connected to the ground, and NMOS tube MA12 grid is connected with clock, and drain electrode is connected with NMOS tube MA11 drain electrode, source electrode and ground
It is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822120446.4U CN209170344U (en) | 2018-12-18 | 2018-12-18 | A kind of Approach by inchmeal ADC structure promoting the linearity |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822120446.4U CN209170344U (en) | 2018-12-18 | 2018-12-18 | A kind of Approach by inchmeal ADC structure promoting the linearity |
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| Publication Number | Publication Date |
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| CN209170344U true CN209170344U (en) | 2019-07-26 |
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| CN201822120446.4U Expired - Fee Related CN209170344U (en) | 2018-12-18 | 2018-12-18 | A kind of Approach by inchmeal ADC structure promoting the linearity |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115842554A (en) * | 2023-02-21 | 2023-03-24 | 深圳市南方硅谷半导体股份有限公司 | Successive approximation type analog-to-digital converter |
| CN116614135A (en) * | 2023-05-18 | 2023-08-18 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Dynamic comparator suitable for synchronous sequential SAR ADC and control method |
-
2018
- 2018-12-18 CN CN201822120446.4U patent/CN209170344U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115842554A (en) * | 2023-02-21 | 2023-03-24 | 深圳市南方硅谷半导体股份有限公司 | Successive approximation type analog-to-digital converter |
| CN116614135A (en) * | 2023-05-18 | 2023-08-18 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Dynamic comparator suitable for synchronous sequential SAR ADC and control method |
| CN116614135B (en) * | 2023-05-18 | 2024-04-09 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Dynamic comparator suitable for synchronous sequential SAR ADC and control method |
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Granted publication date: 20190726 Termination date: 20191218 |