CN209515654U - SOT dual chip lead frame structure and SOT dual chip lead frame assembly - Google Patents
SOT dual chip lead frame structure and SOT dual chip lead frame assembly Download PDFInfo
- Publication number
- CN209515654U CN209515654U CN201920306034.1U CN201920306034U CN209515654U CN 209515654 U CN209515654 U CN 209515654U CN 201920306034 U CN201920306034 U CN 201920306034U CN 209515654 U CN209515654 U CN 209515654U
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- Prior art keywords
- sot
- lead frame
- dual chip
- chip lead
- frame structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model is suitable for technical field of electronic products, provide SOT dual chip lead frame structure and SOT dual chip lead frame assembly, including interior pin, outer pin and the island Liang Geji, Ji Dao and interior pin are respectively positioned in a quadrangle, and the island Liang Geji is located at one group of diagonal angle of the quadrangle, 2 interior pins are arranged with along the horizontal edge of the quadrangle by each base island, each Ji Dao is electrically connected two interior pins, the quantity of outer pin is 6, and each outer pin is separately connected an interior pin or Ji Dao.The SOT dual chip lead frame structure, with 6 effective outer pins, the island Liang Geji, it is applicable to the chip that encapsulation two is respectively necessary for 3 leading-out terminals, the product (double N pipes, double P pipe or N+P multiple tube) of especially two metal-oxide-semiconductor cores, overall volume is smaller, can meet the needs of electronic product is for small size after encapsulation, it can satisfy the demand after encapsulating for thermal diffusivity and internal resistance, manufacture relatively simple, advantage of lower cost.
Description
Technical field
The utility model belongs to technical field of electronic products, and in particular to a kind of SOT dual chip lead frame structure and
SOT dual chip lead frame assembly.
Background technique
Chip package is a kind of technology for being packaged the plastics of integrated circuit insulation or ceramic material, not only acts as peace
It puts, fix, sealing, protecting the effect of chip and increased thermal conductivity energy, but also being to link up the chip interior world and external circuit
Bridge.
It is a kind of currently used small-sized patch that small outline transistor, which encapsulates (SOT, Small Outline Transistor),
Chip package.Metal-oxide-semiconductor is a kind of discrete device very common at present, for opposite IC, since its unique switching characteristic has
There is irreplaceable advantage, is widely used in consumer, portable electronic product.For now, single tube MOS chip and double
The application range of pipe MOS chip is wider more more flexible than Multi-core.Single die MOSFET has Gate, Source, Drain tri-
A electrode, dual-die MOSFET then have 2 Gate, 2 Source, 2 Drain totally 6 electrodes, and encapsulation at least needs 6
Terminal, selectable packing forms have SOT23-6, SOP8 etc..SOP8 package cooling is more preferable, but encapsulation volume is big, internal resistance
It is larger, there are 2 terminals to slattern for encapsulating dual-tube MOS then, and packaging cost is high；SOT23-6 thermal diffusivity, internal resistance and volume
It is all more moderate, but be used to encapsulate subminiature dual-tube MOS chip (long side be no more than 0.5mm) then volume has occupied greatly one
A bit, seem especially sensitive today in portable electronic product for volume and be less suitable for.
Utility model content
The purpose of the utility model is to overcome the above-mentioned dual-tube MOS of microminiature in the prior art chip-packaging structure volume is big
And the deficiency that cost is excessively high, provide a kind of SOT dual chip lead frame structure.
The utility model is realized in this way: a kind of SOT dual chip lead frame structure comprising interior pin, outer pin
And two Ji Dao for chip, wherein the Ji Dao and the interior pin are respectively positioned in a quadrangle, and two
The Ji Dao is located at one group of diagonal angle of the quadrangle, and the quantity of the interior pin is 4, by each base island along
The horizontal edge of the quadrangle is arranged with 2 interior pins, and each Ji Dao is electrically connected two interior pins, described outer
The quantity of pin is 6, and the inner end of each outer pin is separately connected an interior pin or the Ji Dao.
As a preferred embodiment of the utility model, the distance between the interior pin and the adjacent interior pin are big
In equal to 0.125mm.
As a preferred embodiment of the utility model, the interior pin is greater than with adjacent the distance between the Ji Dao
Equal to 0.125mm.
As a preferred embodiment of the utility model, the outer pin is with adjacent the distance between the outer pin
0.15mm。
As a preferred embodiment of the utility model, the length of the Ji Dao is 0.7mm, and the width of the Ji Dao is
0.49mm。
The utility model additionally provides a kind of SOT dual chip lead frame assembly comprising substrate and multiple as above-mentioned
The SOT dual chip lead frame structure.
As a preferred embodiment of the utility model, multiple SOT dual chip lead frame structure are arranged in matrix form
Column setting is on the substrate.
As a preferred embodiment of the utility model, multiple SOT dual chip lead frame structure are set in 6 rows arrangement
It sets on the substrate.
As a preferred embodiment of the utility model, the length of the substrate is 215.6mm, and the width of the substrate is
28.08mm。
As a preferred embodiment of the utility model, the quantity of the SOT dual chip lead frame structure is 336.
A kind of SOT dual chip lead frame structure provided by the utility model, compared with the existing technology, having 6 has
The outer pin of effect, the island Liang Geji are applicable to the chip that encapsulation two is respectively necessary for 3 leading-out terminals, especially two metal-oxide-semiconductors
The product (double N pipes, double P pipe or N+P multiple tube, long side are no more than 0.5mm) of core, overall volume is smaller, can meet after encapsulation
Electronic product can satisfy the demand after encapsulating for thermal diffusivity and internal resistance for the demand of small size, manufacture more
Simply, advantage of lower cost.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is this
Some embodiments of utility model, for those of ordinary skill in the art, without creative efforts, also
Other drawings may be obtained according to these drawings without any creative labor.
Following drawings are only intended to schematically illustrate and explain the present invention, does not limit the model of the utility model
It encloses.
Fig. 1 is the structural schematic diagram of SOT dual chip lead frame structure provided by the embodiment of the utility model；
Fig. 2 is the structural schematic diagram of SOT dual chip lead frame assembly provided by the embodiment of the utility model；
Part drawing reference numeral explanation:
100, SOT dual chip lead frame structure；
110, Ji Dao；120, interior pin；130, outer pin；
200, SOT dual chip lead frame assembly；
210, substrate.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
Embodiment
Referring to Fig. 1, present embodiments providing a kind of SOT dual chip lead frame structure 100 comprising interior pin 120,
Outer pin 130 and two base islands 110 for chip, wherein base island 110 and interior pin 120 are respectively positioned on one or four sides
In shape A, and the island Liang Geji 110 is located at one group of diagonal angle of quadrangle A, and the quantity of interior pin 120 is 4, Mei Geji
2 interior pins 120 are arranged with along the horizontal edge of quadrangle A by island 110, each base island 110 is electrically connected two interior pins
120 (being electrically connected as shown in Figure 1, can be realized by conducting wire), the quantity of outer pin 130 is 6, the inner end of each outer pin 130
It is separately connected an interior pin 120 or base island 110.
Among the above, specifically, the SOT dual chip lead frame structure 100, there are 6 effective outer pins 130, two
The island Ge Ji 110 is applicable to the chip that encapsulation two is respectively necessary for 3 leading-out terminals, the product of especially two metal-oxide-semiconductor cores
(double N pipes, double P pipe or N+P multiple tube, long side are no more than 0.5mm), overall volume is smaller, and electronic product can be met after encapsulation
For the demand of small size, the demand after encapsulating for thermal diffusivity and internal resistance can satisfy, manufacture relatively simple, cost
It is relatively low.
As a preferred embodiment of the utility model, the distance between interior pin 120 and adjacent interior pin 120 B are big
In equal to 0.125mm.
As a preferred embodiment of the utility model, the distance between interior pin 120 and adjacent base island 110 C are greater than
Equal to 0.125mm.
As a preferred embodiment of the utility model, the distance between outer pin 130 and adjacent outer pin 130 D are
0.15mm。
As a preferred embodiment of the utility model, the length on base island 110 is 0.7mm, and the width on base island 110 is
0.49mm。
Among the above, specifically, passing through the distance between pin 120 and adjacent interior pin 120 B and interior in being rationally arranged
The size of the distance between pin 120 and adjacent base island 110 C, it is ensured that punching production SOT dual chip lead frame structure
The durability (being not less than 0.125mm) of punch-pin, production when both ensure that the punching press SOT dual chip lead frame structure 100 when 100
Safety (gap is wider, and punch-pin is less susceptible to break), and between promoted pins of products pressure difference have obvious effects on.
Referring to Fig. 2, the present embodiment additionally provides a kind of SOT dual chip lead frame assembly 200 comprising substrate 210
And it is multiple such as above-mentioned SOT dual chip lead frame structure 100.
Specifically, rewinding structure, single SOT dual chip lead frame knot can be used in SOT dual chip lead frame assembly 200
The whole length and width of structure 100 and unit step distance adjustment are approached to conventional 6 row's SOT-23 frames, to share cutting mold, save frame
Put up this.
Also, the SOT dual chip lead frame assembly 200 has the complete of aforementioned middle SOT dual chip lead frame structure 100
Portion's function and effect, specifically refer to aforementioned, and this will not be repeated here.
As a preferred embodiment of the utility model, multiple SOT dual chip lead frame structure 100 are in matrix arrangement
Setting is over the substrate 210.
As a preferred embodiment of the utility model, multiple SOT dual chip lead frame structure 100 are set in 6 rows arrangement
It sets over the substrate 210.
As a preferred embodiment of the utility model, the length of substrate 210 is 215.6mm, and the width of substrate 210 is
28.08mm。
As a preferred embodiment of the utility model, the quantity of SOT dual chip lead frame structure 100 is 336.
Among the above, specifically, the SOT dual chip lead frame assembly 200 is divided into single by using high density designs
After frame, the element number on the substrate of one piece of 215.6*28.08mm2 reaches 336 (0.055/mm2), frame utilization rate
It is high.
A kind of SOT dual chip lead frame structure provided by the embodiment of the utility model has compared with the existing technology
6 effective outer pins, the island Liang Geji are applicable to the chips that encapsulation two is respectively necessary for 3 leading-out terminals, and especially two
The product (double N pipes, double P pipe or N+P multiple tube, long side are no more than 0.5mm) of metal-oxide-semiconductor core, overall volume is smaller, can after encapsulation
Meet the needs of electronic product is for small size, can satisfy the demand after encapsulating for thermal diffusivity and internal resistance, manufactures
It is relatively simple, advantage of lower cost.
Among the above, it is to be understood that unless otherwise defined, the technical term or scientific term that the utility model uses
It should be the ordinary meaning that the personage in the utility model fields with general technical ability is understood.It is used in the utility model
" first ", " second " and similar word be not offered as any sequence, quantity or importance, and be used only to distinguish not
Same component part.Equally, "one", the similar word such as " one " or "the" do not indicate that quantity limits yet, but indicates exist
At least one.The similar word such as " comprising " or "comprising", which means to occur element or object before the word, to be covered and appears in
The element of the word presented hereinafter perhaps object and its equivalent and be not excluded for other elements or object." connection " or " connected "
It is not limited to physics or mechanical connection etc. similar word, but may include electrical connection, either directly
Or it is indirect."upper", "lower", "left", "right" etc. are only used for indicating relative positional relationship, when the absolute position for being described object
After setting change, then the relative positional relationship may also correspondingly change.
There is the following to need to illustrate simultaneously:
(1) unless otherwise defined, in the embodiments of the present invention and attached drawing, same label represents same meaning.
(2) in the utility model embodiment attached drawing, the structure being related to the utility model embodiment is related only to, other
Structure, which can refer to, to be commonly designed.
(3) for clarity, in the attached drawing for describing the embodiments of the present invention, the thickness quilt in layer or region
Amplification.It is appreciated that when the element of such as layer, film, region or substrate etc is referred to as being located at "above" or "below" another element,
The element " direct " can be located at "above" or "below" another element, or may exist intermediary element.
(4) in the absence of conflict, the feature in the same embodiment of the utility model and different embodiment can phase
Mutually combination.
The above is only the preferred embodiments of the present utility model only, is not intended to limit the utility model, all practical at this
Made any modification, equivalent replacement or improvement etc., should be included in the guarantor of the utility model within novel spirit and principle
Within the scope of shield.
Claims (10)
1.SOT dual chip lead frame structure, which is characterized in that be used for chip including interior pin, outer pin and two
Ji Dao, wherein the Ji Dao and the interior pin are respectively positioned in a quadrangle, and two Ji Dao be located at this four
One group of diagonal angle of side shape, the quantity of the interior pin are 4, are arranged with by each base island along the horizontal edge of the quadrangle
2 interior pins, each Ji Dao are electrically connected two interior pins, and the quantity of the outer pin is 6, each
The inner end of the outer pin is separately connected an interior pin or the Ji Dao.
2. SOT dual chip lead frame structure as described in claim 1, which is characterized in that the interior pin and adjacent institute
The distance between interior pin is stated more than or equal to 0.125mm.
3. SOT dual chip lead frame structure as described in claim 1, which is characterized in that the interior pin and adjacent institute
The distance between island Shu Ji is more than or equal to 0.125mm.
4. SOT dual chip lead frame structure as described in claim 1, which is characterized in that the outer pin and adjacent institute
Stating the distance between outer pin is 0.15mm.
5. SOT dual chip lead frame structure as described in claim 1, which is characterized in that the length of the Ji Dao is
The width of 0.7mm, the Ji Dao are 0.49mm.
6.SOT dual chip lead frame assembly, which is characterized in that including substrate and multiple SOT as claimed in claims 1-5
Dual chip lead frame structure.
7. SOT dual chip lead frame assembly as claimed in claim 6, which is characterized in that multiple SOT dual chip leads
Frame structure is arranged on the substrate in matrix arrangement.
8. SOT dual chip lead frame assembly as claimed in claim 7, which is characterized in that multiple SOT dual chip leads
Frame structure is arranged on the substrate in 6 rows.
9. SOT dual chip lead frame assembly as claimed in claim 8, which is characterized in that the length of the substrate is
215.6mm, the width of the substrate are 28.08mm.
10. SOT dual chip lead frame assembly as claimed in claim 8, which is characterized in that the SOT dual chip lead frame
The quantity of frame structure is 336.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920306034.1U CN209515654U (en) | 2019-03-11 | 2019-03-11 | SOT dual chip lead frame structure and SOT dual chip lead frame assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920306034.1U CN209515654U (en) | 2019-03-11 | 2019-03-11 | SOT dual chip lead frame structure and SOT dual chip lead frame assembly |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209515654U true CN209515654U (en) | 2019-10-18 |
Family
ID=68205171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920306034.1U Active CN209515654U (en) | 2019-03-11 | 2019-03-11 | SOT dual chip lead frame structure and SOT dual chip lead frame assembly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209515654U (en) |
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2019
- 2019-03-11 CN CN201920306034.1U patent/CN209515654U/en active Active
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 518000 The whole building on the first floor of the factory building of Xinhao Second Industrial Zone, Xintian Community, Fuhai Street, Baoan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Xinzhantong Electronics Co., Ltd. Address before: 518000 the whole building on the first floor of building B1 in Xinhao second industrial zone, Qiaotou community, Fuhai street, Bao'an District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN XINZHANTONG ELECTRONICS CO.,LTD. |
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| CP03 | Change of name, title or address |