CN209313820U - 应用于fpga的双环路锁相环模拟核心电路及锁相环 - Google Patents
应用于fpga的双环路锁相环模拟核心电路及锁相环 Download PDFInfo
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CN109547017A (zh) * | 2018-12-29 | 2019-03-29 | 西安智多晶微电子有限公司 | 一种应用于fpga的双环路锁相环模拟核心电路及锁相环 |
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CN109547017A (zh) * | 2018-12-29 | 2019-03-29 | 西安智多晶微电子有限公司 | 一种应用于fpga的双环路锁相环模拟核心电路及锁相环 |
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Denomination of utility model: Dual loop PLL analog core circuit and PLL applied to FPGA Effective date of registration: 20220329 Granted publication date: 20190827 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2022610000115 |
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Date of cancellation: 20230328 Granted publication date: 20190827 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2022610000115 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Dual loop phase-locked loop simulation core circuit and phase-locked loop applied to FPGA Effective date of registration: 20230331 Granted publication date: 20190827 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2023610000233 |