CN208767292U - Sot-89/223-2l引线框架及两脚结构 - Google Patents

Sot-89/223-2l引线框架及两脚结构 Download PDF

Info

Publication number
CN208767292U
CN208767292U CN201821523626.0U CN201821523626U CN208767292U CN 208767292 U CN208767292 U CN 208767292U CN 201821523626 U CN201821523626 U CN 201821523626U CN 208767292 U CN208767292 U CN 208767292U
Authority
CN
China
Prior art keywords
plastic
lead frame
foot
sealed body
sot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201821523626.0U
Other languages
English (en)
Inventor
徐洋
严巧成
管钱健
龚天宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JIANGSU JIEJIE MICROELECTRONICS CO Ltd
Original Assignee
JIANGSU JIEJIE MICROELECTRONICS CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JIANGSU JIEJIE MICROELECTRONICS CO Ltd filed Critical JIANGSU JIEJIE MICROELECTRONICS CO Ltd
Priority to CN201821523626.0U priority Critical patent/CN208767292U/zh
Application granted granted Critical
Publication of CN208767292U publication Critical patent/CN208767292U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本实用新型公开了SOT‑89/223‑2L引线框架及两脚结构，包括塑封体（1），塑封体（1）内设引线框架（11），塑封体（1）一侧引出散热片（2），塑封体（1）另一侧引出左引线脚（3）、右引线脚（4）和中间引线脚（5）；所述中间引线脚（5）为内埋式。两脚产品中间引线脚处无露铜点，散热片与中脚采取塑封线处切断式结构设计的切筋实现方法，使器件在工作时≥1500V电压无打火或短路现象，从而提高了器件的可靠性。

Description

SOT-89/223-2L引线框架及两脚结构
技术领域
本实用新型涉及封装的技术领域，具体涉及SOT-89/223-2L引线框架及两脚结构产品，包括6排、8排、12排等多排结构。
背景技术
现有的SOT-89/223-2L产品，包括塑封体、散热片、左引线脚、右引线脚、中间引线脚，中间引线脚与左右引线脚长度一致，通过切筋时切断中间脚，余留0.5-1.0mm长度的中间脚，余留中间脚与左右脚的距离较小，器件在工作时因≥1500V电压产生打火或短路现象，从而发生早期电路失效。
实用新型内容
为了解决以上技术问题，本实用新型提供SOT-89/223-2L引线框架及两脚结构，包括塑封体，塑封体内设引线框架，塑封体一侧引出散热片，塑封体另一侧引出左引线脚、右引线脚和中间引线脚；所述中间引线脚为内埋式。
本实用新型塑封模具同时兼容SOT-89/223-3L产品，减少了塑封模具及设备的投入。SOT-89/223-2L产品中脚处无露铜点，脚距扩大为两倍，器件在工作时≥1500V电压无打火或短路现象，从而提高了器件的可靠性。
本实用新型改变了传统的三脚切断实现两脚封装的方式，实现两脚封装结构，且中脚不外露，增加了左右两脚之间的绝缘距离，拓宽了器件的应用范围。
附图说明
图1是本实用新型的引线框架结构示意图。
图2是SOT-89/223-3L内部结构图。
图3是打胶去除工艺中脚原理图。
图4是SOT-89/223-3L产品结构图。
图5是SOT-89/223-2L中脚外露的产品结构图。
图6是SOT-89/223-2L无中脚的产品结构图。
图中，1. 塑封体，2. 散热片，3. 左引线脚，4. 右引线脚，5. 中间引线脚，6. 焊锡，7. 芯片，8. 铜线，9. 凸模刀件，10. 凹模刀件，11.引线框架。
具体实施方式
本实用新型提供了SOT-89/223-2L引线框架及两脚结构的实现方法，通过特殊的框架结构设计，在塑封时塑封模具可以兼容SOT-89/223-3L和SOT-89/223-2L两种结构的产品，塑封后SOT-89/223-2L产品的中间引线脚完全包封在塑封体内，在打胶时通过模具切除框架上起塑封封堵作用的中间引线脚，SOT-89/223-2L产品中间引线脚处留下0.1mm长度的模塑料，将器件的引线脚距扩大为两倍，提高了器件的可靠性。
如图1所示，SOT-89/223-2L引线框架及两脚结构，包括塑封体1，塑封体1内设引线框架11，塑封体1一侧引出散热片2，塑封体1另一侧引出左引线脚3、右引线脚4和中间引线脚5。中间引线脚5在左引线脚3和右引线脚4的中间，中间引线脚5可切断。
SOT-89/223-2L引线框架及两脚结构的制备方法，包括以下步骤：
步骤1：如图2所示，将芯片7焊接到引线框架上：设置粘片机温度为350-380℃。氢氮气按比例混合，氢气比例为10-25%，余下为氮气。高温焊锡丝Pb92.5Sn5Ag2.5。当引线框架11传送到点锡位置时，在氢氮气保护的状态下，通过写锡的方式在芯片装载区域划上厚度为20-60um的正方形焊锡6，将芯片7吸装到引线框架11的焊接区域，并冷却到室温。
步骤2：将芯片7的电极通过铜线8连接到引线框架11的对应左引线脚3和右引线脚4上：设置球焊机焊接区导轨温度200-250℃。将氢氮按比例混合，氢气比例为5-10%，余下为氮气。装有芯片7的引线框架11传送到焊接区域，在氢氮气保护的状态下，铜线8烧球后焊接在芯片7表面电极上，超声方式将铜线8的另一端焊接在引线框架11的对应左引线脚3和右引线脚4上。
步骤3：将焊锡完成的引线框架11用模塑料包封起来：设置排片机温度170-185℃，模具温度165-175℃。然后将包封后的引线框架11排到排片机上预热，再将预热后的引线框架11通过上料架放到塑封模具上，放入模塑料，合模注塑并完成固化后取出产品。
步骤4：将塑封后的流道从引线框架11上去除：将塑封后的引线框架11放入去流道机内，去除模塑料的流道，形成产品。
步骤5：后固化：将去除流道后的产品放入温度为175±5℃的烘箱内进行固化，时间12小时。
步骤6：将后固化的产品放入打胶机去除残留浇口，并去除中间引线脚；打胶模具中间引线脚处凹模刀件支撑产品部分，凸模刀件设计成渐进式斜面刀口，先将中间引线脚靠近塑封体部分沿框架断口推离产品塑封体分型面，然后从引线框架11的外边框处切断中间引线脚5，并对切断处打胶。
步骤7：打胶完成的产品进行电镀、切筋、测试、包装。

Claims (1)

1.SOT-89/223-2L引线框架及两脚结构，其特征在于：包括塑封体（1），塑封体（1）内设引线框架（11），塑封体（1）一侧引出散热片（2），塑封体（1）另一侧引出左引线脚（3）、右引线脚（4）和中间引线脚（5）；所述中间引线脚（5）为内埋式。
CN201821523626.0U 2018-09-18 2018-09-18 Sot-89/223-2l引线框架及两脚结构 Active CN208767292U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201821523626.0U CN208767292U (zh) 2018-09-18 2018-09-18 Sot-89/223-2l引线框架及两脚结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201821523626.0U CN208767292U (zh) 2018-09-18 2018-09-18 Sot-89/223-2l引线框架及两脚结构

Publications (1)

Publication Number Publication Date
CN208767292U true CN208767292U (zh) 2019-04-19

Family

ID=66136843

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201821523626.0U Active CN208767292U (zh) 2018-09-18 2018-09-18 Sot-89/223-2l引线框架及两脚结构

Country Status (1)

Country Link
CN (1) CN208767292U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109003957A (zh) * 2018-09-18 2018-12-14 江苏捷捷微电子股份有限公司 Sot-89/223-2l引线框架及两脚结构的制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109003957A (zh) * 2018-09-18 2018-12-14 江苏捷捷微电子股份有限公司 Sot-89/223-2l引线框架及两脚结构的制备方法

Similar Documents

Publication Publication Date Title
JP5562874B2 (ja) 半導体装置の製造方法
CN102074541B (zh) 一种无载体无引脚栅格阵列ic芯片封装件及其生产方法
CN103824834B (zh) 一种具有改进型封装结构的半导体器件及其制造方法
CN208767292U (zh) Sot-89/223-2l引线框架及两脚结构
CN105895539B (zh) 芯片倒装封装中间结构和倒装封装结构及倒装封装方法
CN102151389A (zh) 高尔夫球的制造方法和由此制成的高尔夫球
CN104752386B (zh) 高可靠性sop封装引线框架及封装件生产方法
CN109003957A (zh) Sot-89/223-2l引线框架及两脚结构的制备方法
CN109545769A (zh) 硅芯片封装引线框架及其封装方法
CN107275045B (zh) 一种电感的制作方法、及其塑封材料的制备方法
CN109256368B (zh) Sot23-x引线框架及其封装方法
CN203674202U (zh) 一种高可靠性sop封装引线框架
CN209534055U (zh) 一种转注成型ic封装模具的流道结构
CN109860127A (zh) 一种芯片封装体及其封装工艺
CN106449517B (zh) 一种堆叠式单基岛sip封装工艺
CN102856216B (zh) 一种方形扁平无引脚封装焊片的方法
CN101764114A (zh) 一种倒装式封装结构及其制作方法
CN203312417U (zh) 一种塑封动力电池均衡模块
CN210245483U (zh) 大功率灌胶工艺贴片tvs二极管
CN106099310B (zh) 一体式包胶成型的汽车天线底座及其生产工艺
CN109599346B (zh) 一种智能功率模组加工工艺及功率模组
CN205319144U (zh) 一种封装芯片的结构
CN207265046U (zh) 一种具有嵌入式pin针的dip封装结构
CN201752001U (zh) 整流二极管
CN207753004U (zh) 一种双基岛sop芯片封装结构

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
CP02 Change in the address of a patent holder

Address after: No.3000 Qiantangjiang Road, Qidong Economic Development Zone, Nantong City, Jiangsu Province

Patentee after: JIANGSU JIEJIE MICROELECTRONICS Co.,Ltd.

Address before: 226200, No. 8, Xinglong Road, Qidong science and Technology Pioneer Park, Nantong, Jiangsu

Patentee before: JIANGSU JIEJIE MICROELECTRONICS Co.,Ltd.

CP02 Change in the address of a patent holder