CN208608197U - 层叠封装结构 - Google Patents

层叠封装结构 Download PDF

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CN208608197U
CN208608197U CN201821531050.2U CN201821531050U CN208608197U CN 208608197 U CN208608197 U CN 208608197U CN 201821531050 U CN201821531050 U CN 201821531050U CN 208608197 U CN208608197 U CN 208608197U
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chipset
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朱耀明
江子标
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Shenzhen Ambrose Power Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Wire Bonding (AREA)

Abstract

本实用新型公开了一种层叠封装结构，包括基板，基板的顶端面上附着有内置芯片互联结构的塑封体；芯片互联结构包括第一芯片组，第一芯片组包括多个水平芯片，最底层水平芯片粘接于基板顶端面上，其他水平芯片以阶梯式逐次层叠在下层水平芯片上，且上层水平芯片与下层水平芯片之间通过金属引线电连接，最底层水平芯片与基板上电连接；第一芯片组中的所有金属引线通过倾斜设置在第一芯片组阶梯面上的绝缘胶层固定；绝缘胶层的倾斜顶端面上设置有第二芯片组，第二芯片组包括多个倾斜芯片，各倾斜芯片与基板上之间分别通过独立的金属引线连接。本实用新型工艺简单、集成度高，在保证了芯片质量稳定可靠的基础上，提高了特定空间内芯片的保有量。

Description

层叠封装结构
技术领域
本实用新型涉及导体芯片封装技术领域，特别是一种封装结构。
背景技术
随着电子工程的发展，人们对于集成电路（Integrated Circuit，简称IC）芯片小型化、轻量化及功能化的需求日渐增加，从最开始的单一组件的开发阶段，逐渐进入到了集结多个组件的系统开发阶段，与此同时在产品高效能及外观轻薄的要求下，不同功能的芯片开始迈向整合的阶段，因此封装技术的不断发展和突破，成为推动整合的力量之一。
层叠芯片是指将多个半导体芯片整合在单一的封装结构中，可以提高电子部件的密度，使电子部件之间的信号传输更快，该种封装体不仅可减少多个芯片使用上所占用的体积，更可以提高整体性能。现有的多芯片封装结构是将多个芯片垂直对齐堆叠、交叉错位堆叠或阶梯状堆叠，接着通过打线直接与基板电连接，其中多个半导体芯片堆叠封装技术中，多个相同尺寸芯片的堆叠封装技术是常见的封装技术。目前的多芯片的层叠封装技术，不仅芯片在层叠后造成打线区域浪费，特定的空间内芯片保有量较少；而且此种结构金属引线过多，工艺较为复杂，容易出现短路或断路现象，降低了芯片层叠后的稳定性。
发明内容
本实用新型需要解决的技术问题是提供一种集成度高、工艺简单的的半导体封装结构，在保证芯片质量稳定性的基础上，提高特定封装空间内芯片的保有量。
为解决上述技术问题，本实用新型所采取的技术方案如下。
层叠封装结构，包括顶端面设置有若干基板焊垫的基板，基板的底端面上设置有植球，基板的顶端面上附着有内置芯片互联结构的塑封体；所述芯片互联结构包括自基板顶端面的中心朝向基板斜上方逐级层叠设置的阶梯式第一芯片组，第一芯片组包括多个水平芯片，最底层水平芯片粘接于基板顶端面上，其他水平芯片以阶梯式逐次层叠在下层水平芯片上，第一芯片组中的下层水平芯片与上层水平芯片不相重叠一端的上端面设置有芯片焊垫，且上层水平芯片的芯片焊垫与与之相邻的下层水平芯片的芯片焊垫之间通过金属引线电连接，最底层水平芯片的芯片焊垫与基板上的基板焊垫电连接；所述第一芯片组中的所有金属引线通过倾斜设置在第一芯片组阶梯面上的绝缘胶层固定；所述绝缘胶层的倾斜顶端面上设置有第二芯片组，第二芯片组包括呈同一平面设置的若干倾斜芯片，倾斜芯片上同样设置有芯片焊垫，倾斜芯片的芯片焊垫与基板上的基板焊垫之间分别通过独立的金属引线连接。
上述层叠封装结构，所述第一芯片组中的各水平芯片为统一规格型号的芯片。
上述层叠封装结构，所述第二芯片组中最高位置的倾斜芯片高度不高于第一芯片组中最高位置金属引线的高度。
由于采用了以上技术方案，本实用新型所取得技术进步如下。
本实用新型工艺简单、制作方便、集成度高，在保证了芯片质量稳定可靠的基础上，提高了特定空间内芯片的保有量，并且还可实现对不同尺寸芯片的层叠封装，满足不同功能封装结构的要求。
附图说明
图1为本实用新型的结构示意图；
其中：1.塑封体，2.金属导线，3.芯片焊垫，4.基板焊垫，5.基板，6.植球，7.水平芯片，8.粘接层，9.绝缘胶层，10.倾斜芯片。
具体实施方式
下面将结合附图和具体实施例对本实用新型进行进一步详细说明。
一种层叠封装结构，其结构如图1所示，包括基板5和塑封体1，基板5的顶端面上设置有若干基板焊垫4，基板的底端面上设置有植球6，塑封体附着在基板的顶端面上，塑封体1内置有与植球电连接的芯片互联结构。
芯片互联结构的结构如图1所示，包括第一芯片组、绝缘胶层9和第二芯片组，绝缘胶层设置与第一芯片组和第二芯片组之间，第一芯片组和第二芯片组分别与基板上的基板焊垫电连接。
阶梯式第一芯片组自基板顶端面的中心朝向基板斜上方逐级层叠设置，包括多个水平芯片7，最底层水平芯片粘接于基板顶端面上，其他水平芯片以阶梯式逐次层叠在下层水平芯片上，第一芯片组中的下层水平芯片与上层水平芯片不相重叠一端的上端面设置有芯片焊垫3，且上层水平芯片的芯片焊垫与与之相邻的下层水平芯片的芯片焊垫之间通过金属引线2电连接，最底层水平芯片的芯片焊垫与基板上的基板焊垫电连接。本实施例中，第一芯片组中的各水平芯片为统一规格型号的芯片。
绝缘胶层9用于固定并保护第一芯片组中的金属引线，通过胶水浇注形成，绝缘胶层倾斜设置在第一芯片组的阶梯面上，如图1所示。
第二芯片组粘附在绝缘胶层的倾斜顶端面上，包括呈同一平面设置的若干倾斜芯片，倾斜芯片上同样设置有芯片焊垫，倾斜芯片的芯片焊垫与基板上的基板焊垫之间分别通过独立的金属引线连接。本实施例中，第二芯片组中的各芯片可为不同规格型号的芯片；但第二芯片组中最高位置的倾斜芯片高度应不高于第一芯片组中最高位置金属引线的高度。
本实用新型的具体制备方法为：在基板上根据芯片设计的功能布设基板焊垫，将最底层水平芯片通过粘接层粘附在基板中心，再通过粘接层将其他水平芯片按照阶梯式进行逐级层叠设置，并通过金属引线逐级连接水平芯片的芯片焊垫至基板的基板焊垫上，形成第一芯片组；其次通过浇注胶水在第一芯片组的倾斜阶梯面上形成覆盖金属引线的绝缘胶层；再在绝缘胶层的倾斜顶端面上粘附倾斜芯片，倾斜芯片与基板焊垫之间分别通过金属引线连接，形成第二芯片组；然后进行塑封，将由第一芯片组、绝缘胶层和第二芯片组构成的芯片互联结构封装起来；最后在基板的底端面上植球，即完成封装工艺。

Claims (3)

1.层叠封装结构，包括顶端面设置有若干基板焊垫（4）的基板（5），基板的底端面上设置有植球（6），基板的顶端面上附着有内置芯片互联结构的塑封体（1）；其特征在于：所述芯片互联结构包括自基板顶端面的中心朝向基板斜上方逐级层叠设置的阶梯式第一芯片组，第一芯片组包括多个水平芯片，最底层水平芯片粘接于基板顶端面上，其他水平芯片以阶梯式逐次层叠在下层水平芯片上，第一芯片组中的下层水平芯片与上层水平芯片不相重叠一端的上端面设置有芯片焊垫（3），且上层水平芯片的芯片焊垫与之相邻的下层水平芯片的芯片焊垫之间通过金属引线（2）电连接，最底层水平芯片的芯片焊垫与基板上的基板焊垫电连接；所述第一芯片组中的所有金属引线通过倾斜设置在第一芯片组阶梯面上的绝缘胶层（9）固定；所述绝缘胶层的倾斜顶端面上设置有第二芯片组，第二芯片组包括呈同一平面设置的若干倾斜芯片，倾斜芯片上同样设置有芯片焊垫，倾斜芯片的芯片焊垫与基板上的基板焊垫之间分别通过独立的金属引线连接。
2.根据权利要求1所述的层叠封装结构，其特征在于：所述第一芯片组中的各水平芯片为统一规格型号的芯片。
3.根据权利要求1所述的层叠封装结构，其特征在于：所述第二芯片组中最高位置的倾斜芯片高度不高于第一芯片组中最高位置金属引线的高度。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111009521A (zh) * 2019-12-31 2020-04-14 悦虎晶芯电路(苏州)股份有限公司 多芯片封装模组

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111009521A (zh) * 2019-12-31 2020-04-14 悦虎晶芯电路(苏州)股份有限公司 多芯片封装模组

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