CN208173577U - A kind of encapsulating structure of chip - Google Patents
A kind of encapsulating structure of chip Download PDFInfo
- Publication number
- CN208173577U CN208173577U CN201820875695.1U CN201820875695U CN208173577U CN 208173577 U CN208173577 U CN 208173577U CN 201820875695 U CN201820875695 U CN 201820875695U CN 208173577 U CN208173577 U CN 208173577U
- Authority
- CN
- China
- Prior art keywords
- chip
- shell
- substrate
- cableties
- groups
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a kind of encapsulating structures of chip, including shell and substrate, two groups of L-type stands are fixedly installed between the lower surface of the substrate and the inner wall bottom of shell, the upper surface of the substrate is provided with pad, the upper surface edge position of the pad offers the same locating slot, and locating slot is internally provided with chip, the upper surface of the chip is provided with cableties, the surrounding of the chip offers the same silver paste filled cavity, the inner surface of the shell offers resin filled cavity, the inside of the resin filled cavity has poured epoxy resin, the front and rear sides outer wall of the shell is provided with several groups cooling fin.The utility model improves the stability of chip operation by setting L-type stand and cableties, and the locating slot of setting improves the accuracy of welding, to improve the yield rate of encapsulation, pass through the heat dissipation film and cooling fin of setting, enhance the heat dissipation effect of sealing structure, it is more practical, it is suitble to be widely popularized and uses.
Description
Technical field
The utility model relates to chip package field, in particular to a kind of encapsulating structure of chip.
Background technique
Encapsulation, which refers to the circuit pin on silicon wafer to be connect with conducting wire, to be guided at external lug, in order to which other devices connect,
Because chip must be isolated from the outside, to prevent the impurity in air from causing electric property to decline the corrosion of chip circuit,
On the other hand, the chip after encapsulation is also more convenient for installing and be transported, since the quality of encapsulating structure directly influences chip itself
The performance of performance and the printed circuit board being attached thereto design and manufacture, therefore it is vital, existing encapsulation knot
Complicated operation for welding of the structure to chip, and welding accuracy is bad, and yield rate is lower, meanwhile, heat dissipation effect is bad, heat collection
It is poly- to be easy to congeal into steam and lead to chip failure, in this regard, existing encapsulating structure need to be improved, to solve the above problems,
It is proposed that a kind of encapsulating structure of chip.
Utility model content
The main purpose of the utility model is to provide a kind of encapsulating structures of chip, can be to core by setting L-type stand
The welding assembly of piece is fixed, and the cableties of setting reinforce the connection of inner lead, improves the stability of chip operation,
Meanwhile the locating slot of setting is marked and positions to the welding position of chip, improves the accuracy of welding, to improve encapsulation
Yield rate, can effectively solve the problems in background technique.
To achieve the above object, the technical solution that the utility model is taken is：
A kind of inner wall bottom of the encapsulating structure of chip, including shell and substrate, the lower surface of the substrate and shell it
Between be fixedly installed with two groups of L-type stands, the lower surface both sides of the edge position of substrate, two groups of institutes are arranged in L-type stand described in two groups
The opening direction of L-type stand is stated on the contrary, the upper surface of the substrate is provided with pad, the upper surface edge position of the pad
It sets and offers the same locating slot, and locating slot is internally provided with chip, the chip is welded on the upper surface of pad, described
The two sides outer wall of shell is fixedly installed with pin, and pin is internally provided with lead fixed frame, the upper surface of the chip
Cableties are provided with, the surrounding of the chip offers the same silver paste filled cavity, and the inner surface of the shell offers resin and fills out
Chamber is filled, the inside of the resin filled cavity has poured epoxy resin, and the front and rear sides outer wall of the shell is provided with several groups
Cooling fin, and heat dissipation film is provided between cooling fin described in shell and several groups.
Further, sticky piece is fixedly connected between the pad and substrate.
Further, the quantity of the cableties is eight groups, and cableties described in eight groups are symmetrically distributed in the upper surface two sides of chip
Marginal position.
Further, the one side wall of the lead fixed frame and shell is through connection.
Further, gold thread is provided between the cableties and lead fixed frame.
Compared with prior art, the utility model has the advantages that：
1. the encapsulating structure of the chip of the utility model can consolidate the welding assembly of chip by the way that L-type stand is arranged
Fixed, the cableties of setting reinforce the connection of inner lead, improve the stability of chip operation, meanwhile, the locating slot of setting
The welding position of chip is marked and is positioned, the accuracy of welding is improved, to improve the yield rate of encapsulation.
2. the encapsulating structure of the chip of the utility model, by the heat dissipation film and cooling fin of setting, when chip is run
The heat transmission of generation enhances the heat dissipation effect of sealing structure to external environment, avoid heat it is not to be released in time congeal into steam and
Make chip failure.
Detailed description of the invention
Fig. 1 is the overall structure diagram of the encapsulating structure of the utility model chip；
Fig. 2 is the explosion views of the encapsulating structure of the utility model chip；
Fig. 3 is the partial structural diagram of the encapsulating structure of the utility model chip.
In figure：1, shell；2, substrate；3, sticky piece；4, pad；5, chip；6, locating slot；7, pin；8, lead is fixed
Frame；9, cableties；10, gold thread；11, silver paste filled cavity；12, resin filled cavity；13, radiate film；14, cooling fin, 15, L-type are stood
Frame.
Specific embodiment
To be easy to understand the technical means, creative features, achievement of purpose, and effectiveness of the utility model, below
In conjunction with specific embodiment, the utility model is further described.
As shown in Figure 1-3, a kind of encapsulating structure of chip, including shell 1 and substrate 2, the lower surface of the substrate 2 and outer
Two groups of L-type stands 15 are fixedly installed between the inner wall bottom of shell 1, the lower surface of substrate 2 is arranged in L-type stand 15 described in two groups
Both sides of the edge position, the opening direction of L-type stand 15 described in two groups is on the contrary, the upper surface of the substrate 2 is provided with pad 4, institute
The upper surface edge position for stating pad 4 offers the same locating slot 6, and locating slot 6 is internally provided with chip 5, institute
The upper surface that chip 5 is welded on pad 4 is stated, the two sides outer wall of the shell 1 is fixedly installed with pin 7, and the inside of pin 7
It is provided with lead fixed frame 8, the upper surface of the chip 5 is provided with cableties 9, and the surrounding of the chip 5 offers the same silver
Filled cavity 11 is starched, the inner surface of the shell 1 offers resin filled cavity 12, and the inside of the resin filled cavity 12 has poured ring
Oxygen resin, the front and rear sides outer wall of the shell 1 are provided with several groups cooling fin 14, and radiate described in shell 1 and several groups
Heat dissipation film 13 is provided between piece 14.
Wherein, sticky piece 3 is fixedly connected between the pad 4 and substrate 2.
Wherein, the quantity of the cableties 9 is eight groups, and cableties 9 described in eight groups are symmetrically distributed in the upper surface two sides of chip 5
Edge position.
Wherein, the one side wall of the lead fixed frame 8 and shell 1 is through connection.
Wherein, gold thread 10 is provided between the cableties 9 and lead fixed frame 8.
Working principle：When encapsulation, outline border of the shell 1 as encapsulating structure plays protection to internal chip 5 and connecting line
Substrate 2 is fixed in effect, L-type stand 15, and the convenient welding to chip 5 operates, and has poured epoxy in resin filled cavity 12
Resin, has a good heat-conducting effect while playing sealing effect, by the pad 4 that sticky piece 3 connects be chip 5 on substrate 2
Installation space is provided, locating slot 6 is marked and positions to the welding position of chip 5, the accuracy of welding is improved, to mention
The yield rate of height encapsulation, fixed gold thread 10 and chip 5 connect on the lead fixed frame 8 inside pin 7, progress electric current conduction,
The silver paste filled in silver paste filled cavity 11 plays conductive effect, and cableties 9 reinforce the connection of inner lead, improves chip
The stability of 5 operations, radiate film 13 and cooling fin 14, the heat transmission generated when chip 5 is run to external environment, enhancing
The heat dissipation effect of sealing structure avoids heat is not to be released in time from congealing into steam and chip 5 is made to fail, easy to operate, using effect
It is ideal, it is more practical.
The basic principles and main features of the present invention and the advantages of the present invention have been shown and described above.Current row
The technical staff of industry is described in above embodiments and description it should be appreciated that the present utility model is not limited to the above embodiments
Only illustrate the principles of the present invention, on the premise of not departing from the spirit and scope of the utility model, the utility model is also
It will have various changes and improvements, these various changes and improvements fall within the scope of the claimed invention.The utility model
Claimed range is defined by the appending claims and its equivalent thereof.
Claims (5)
1. a kind of encapsulating structure of chip, including shell (1) and substrate (2), it is characterised in that：The lower surface of the substrate (2)
Two groups of L-type stands (15) are fixedly installed between the inner wall bottom of shell (1), L-type stand (15) described in two groups is arranged in base
The lower surface both sides of the edge position of plate (2), the opening direction of L-type stand (15) described in two groups on the contrary, the substrate (2) upper table
Face is provided with pad (4), and the upper surface edge position of the pad (4) offers the same locating slot (6), and locating slot
(6) be internally provided with chip (5), the chip (5) is welded on the upper surface of pad (4), the two sides outer wall of the shell (1)
It is fixedly installed with pin (7), and pin (7) is internally provided with lead fixed frame (8), the upper surface of the chip (5) sets
It is equipped with cableties (9), the surrounding of the chip (5) offers the same silver paste filled cavity (11), and the inner surface of the shell (1) is opened
Equipped with resin filled cavity (12), the inside of the resin filled cavity (12) has poured epoxy resin, the front and back two of the shell (1)
Side outer wall is provided with several groups cooling fin (14), and is provided between cooling fin (14) described in shell (1) and several groups scattered
Hot glue piece (13).
2. the encapsulating structure of chip according to claim 1, it is characterised in that：It is solid between the pad (4) and substrate (2)
Surely sticky piece (3) are connected with.
3. the encapsulating structure of chip according to claim 1, it is characterised in that：The quantity of the cableties (9) be eight groups, eight
The group cableties (9) are symmetrically distributed in the upper surface both sides of the edge position of chip (5).
4. the encapsulating structure of chip according to claim 1, it is characterised in that：The lead fixed frame (8) and shell (1)
One side wall through connection.
5. the encapsulating structure of chip according to claim 1, it is characterised in that：The cableties (9) and lead fixed frame (8)
Between be provided with gold thread (10).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820875695.1U CN208173577U (en) | 2018-06-07 | 2018-06-07 | A kind of encapsulating structure of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820875695.1U CN208173577U (en) | 2018-06-07 | 2018-06-07 | A kind of encapsulating structure of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208173577U true CN208173577U (en) | 2018-11-30 |
Family
ID=64365948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820875695.1U Active CN208173577U (en) | 2018-06-07 | 2018-06-07 | A kind of encapsulating structure of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208173577U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109719381A (en) * | 2019-02-21 | 2019-05-07 | 巴中市特兴智能科技有限公司 | A kind of process of automatic welding bonding gold thread |
| CN109860130A (en) * | 2019-01-18 | 2019-06-07 | 南京双电科技实业有限公司 | A kind of packaging body reducing laminated packaging structure for communication chip |
| CN112051646A (en) * | 2019-06-06 | 2020-12-08 | 青岛海信宽带多媒体技术有限公司 | Optical module |
-
2018
- 2018-06-07 CN CN201820875695.1U patent/CN208173577U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109860130A (en) * | 2019-01-18 | 2019-06-07 | 南京双电科技实业有限公司 | A kind of packaging body reducing laminated packaging structure for communication chip |
| CN109719381A (en) * | 2019-02-21 | 2019-05-07 | 巴中市特兴智能科技有限公司 | A kind of process of automatic welding bonding gold thread |
| CN112051646A (en) * | 2019-06-06 | 2020-12-08 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN112051646B (en) * | 2019-06-06 | 2022-06-14 | 青岛海信宽带多媒体技术有限公司 | Optical module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN208173577U (en) | A kind of encapsulating structure of chip | |
| CN102683302A (en) | Radiating structure for single chip package and system-in-package | |
| CN206532771U (en) | Cooling type semiconductor device | |
| CN209357719U (en) | A kind of package structure of semiconductor device with low thermal resistance | |
| CN204792892U (en) | High -power LED packaging structure of back -off formula small -size | |
| CN103413802B (en) | A kind of large power dissipating chip encapsulating structure | |
| CN205582931U (en) | Part frame exposes multicore piece singly takes flip -chip tiling clamp core packaging structure | |
| CN205984948U (en) | That uses heat abstractor exempts from to weld ultra -thin diode | |
| CN204067374U (en) | A kind of high-power high-current diode package structure | |
| CN209199909U (en) | A kind of novel TO-220 type semiconductor package | |
| CN205582917U (en) | Frame exposes multicore piece takes flip -chip tiling clamp core packaging structure more | |
| CN209298116U (en) | The solar energy of base island separate type bypasses core component frame | |
| CN207517660U (en) | It is a kind of to manufacture ic chip package structure with ultrasonic copper wire | |
| CN109860130A (en) | A kind of packaging body reducing laminated packaging structure for communication chip | |
| CN202816904U (en) | Encapsulation structure of naked-die device | |
| CN205582923U (en) | Frame exposes multicore piece to be taken flip -chip more and piles up double -layered core packaging structure | |
| CN205582928U (en) | Multicore piece is taken flip -chip tiling more and is pressed from both sides core packaging structure | |
| CN207250511U (en) | A kind of super high power COB light source | |
| CN205355046U (en) | Frame exposes multicore piece to be taken more and loading in mixture tiling and press from both sides core packaging structure | |
| CN206742234U (en) | Ceramic pinboard for the installation of large-size ceramic shell | |
| CN220895531U (en) | Anti-continuous tin flip LED bracket | |
| CN217822750U (en) | Packaging structure of IC chip | |
| CN216354187U (en) | IC chip packaging device | |
| CN206610801U (en) | A kind of integrated circuit package body | |
| CN211858627U (en) | Semiconductor packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |