CN208111430U - A kind of intelligent card chip pad arrangement structure - Google Patents
A kind of intelligent card chip pad arrangement structure Download PDFInfo
- Publication number
- CN208111430U CN208111430U CN201721331999.3U CN201721331999U CN208111430U CN 208111430 U CN208111430 U CN 208111430U CN 201721331999 U CN201721331999 U CN 201721331999U CN 208111430 U CN208111430 U CN 208111430U
- Authority
- CN
- China
- Prior art keywords
- chip
- pad
- intelligent card
- welding tray
- encapsulation welding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/4811—Connecting to a bonding area of the semiconductor or solid-state body located at the far end of the body with respect to the bonding area outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Abstract
The utility model provides a kind of intelligent card chip pad arrangement structure, including chip, encapsulation welding tray and testing weld pad, wherein encapsulation welding tray is linearly arranged, and linear distance chip is 50 ~ 120um on one side.And testing weld pad and encapsulation welding tray can arrange in a straight line, alternatively, the distance between testing weld pad and encapsulation welding tray are 100~200um, in the arrangement that is staggered.When this intelligent card chip pad arrangement structure makes chip testing, adjacent chips spacing is fixed, and alignment is unique, can be obtained using biggish space, and then shortens the testing time, reduces manufacturing cost.
Description
Technical field
The present invention relates to intelligent card chip technical field more particularly to a kind of intelligent card chip pad arrangement configuration aspects.
Background technique
For intelligent card chip, in conventional pad layout structure, encapsulation welding tray is symmetrical in chip edge, such as Fig. 1
It is shown, it is existing intelligent card chip pad layout structure, which includes chip 101, testing weld pad 102, envelope
Welding equipment disk 103.Such pad layout structure, although can be convenient encapsulation bonding wire, also constrain power of test.Because
Due to the bilateral distributed architecture of this pad, so that probe spacing is from close between adjacent chips, on the one hand, exist and be required to needle blocking
Higher, the production cycle is long, and maintenance is difficult；On the other hand, since the upper layer cabling of linking probe must also be placed side by side, wave
A large amount of wiring space is taken, probe is limited, and under the arrangement mode, more satisfactory state also only accomplishes 64 so that accommodating
Left and right chip parallel test.
Utility model content
In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a kind of intelligent card chip pad arrangements
Structure, wherein pad is divided into testing weld pad and encapsulation welding tray, has testing weld pad and encapsulation welding tray in straight line arrangement or mistake
Begin to rehearse cloth the characteristics of so that adjacent chips spacing is fixed, alignment is unique, and such mechanism testing probe card can accommodate more tests and visit
Needle, it is easy to accomplish 128 and the above chip parallel test, reach and shorten the testing time, reduce the purpose of manufacturing cost.
In order to reach above-mentioned technical purpose, the technical scheme adopted by the invention is that：
A kind of intelligent card chip pad arrangement structure, including chip, encapsulation welding tray and testing weld pad, wherein the encapsulation
Pad is linearly arranged, and linear distance chip is 50 ~ 120um on one side；Testing weld pad and encapsulation welding tray are in be staggered arrangement and test
The distance between pad and encapsulation welding tray are that 100~200um or testing weld pad and encapsulation welding tray are arranged in a straight line.
Preferably, the chip is contact intelligent card.
The utility model is due to using above-mentioned testing weld pad and encapsulation welding tray in straight line arrangement or the arrangement knot that is staggered
Structure, beneficial effect obtained are, so that adjacent chips spacing is fixed, and alignment is unique when chip testing, this simple intelligence
Card chip pad arrangement structure can be obtained using biggish space, be conducive to the upper layer cabling of linking probe, and then expand and visit
Needle so that chip and survey number increase, it is easy to realize the concurrent testing scheme of 128,256,512 chips so that test
The output of board unit time increases, and then shortens the testing time, reduces manufacturing cost.
The utility model is described further with reference to the accompanying drawings and detailed description.
Detailed description of the invention
Fig. 1 is existing intelligent card chip pad layout structure figure.
Fig. 2 is the intelligent card chip pad layout structure figure of one of the utility model specific implementation.
Fig. 3 is the intelligent card chip pad layout structure figure of the two of the utility model specific implementation.
Specific embodiment
Referring to Fig. 2, the intelligent card chip pad layout structure figure of one of the utility model specific implementation.The intelligent card chip
In pad arrangement structure, including chip 201, testing weld pad 202 and encapsulation welding tray 203, wherein encapsulation welding tray 203 is linearly arranged
Cloth, linear distance chip 201 are 50 ~ 120um on one side.And testing weld pad 202 and encapsulation welding tray 203 are arranged in a straight line.Wherein,
Chip 201 is contact intelligent card.Chip selects different pad sizes, encapsulating material size, bonding wire parameter in the domain stage
Simulation optimization is carried out, packaging and testing pad best coordinates, size are obtained, achievees the purpose that implement pad layout.
Referring to Fig. 3, the intelligent card chip pad layout structure figure of the two of the utility model specific implementation.The intelligent card chip
In pad arrangement structure, including chip 301, testing weld pad 302 and encapsulation welding tray 303, wherein encapsulation welding tray 303 is linearly arranged
Cloth, linear distance chip 301 are 50 ~ 120um on one side.And the distance between testing weld pad 302 and encapsulation welding tray 303 be 100~
200um, in the arrangement that is staggered.Wherein, chip 301 is contact intelligent card.Chip selects different pad rulers in the domain stage
Very little, encapsulating material size, bonding wire parameter carry out simulation optimization, obtain packaging and testing pad best coordinates, size, reach implementation
The purpose of pad layout.
The utility model is not limited to embodiment discussed above.Obvious change based on the utility model enlightenment
Changing or substituting should also be as being considered within the protection scope of the utility model.Above specific embodiment is used to disclose practical
Novel best implementation method, so that those skilled in the art can apply the numerous embodiments of the utility model
And a variety of alternatives reach the purpose of this utility model.
Claims (2)
1. a kind of intelligent card chip pad arrangement structure, including chip, encapsulation welding tray and testing weld pad, which is characterized in that described
Encapsulation welding tray is linearly arranged, and linear distance chip is 50 ~ 120um on one side；Testing weld pad and encapsulation welding tray in be staggered arrangement and
The distance between testing weld pad and encapsulation welding tray are that 100~200um or testing weld pad and encapsulation welding tray are arranged in a straight line.
2. intelligent card chip pad arrangement structure as described in claim 1, it is characterised in that the chip is contact intelligence
Card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721331999.3U CN208111430U (en) | 2017-10-17 | 2017-10-17 | A kind of intelligent card chip pad arrangement structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721331999.3U CN208111430U (en) | 2017-10-17 | 2017-10-17 | A kind of intelligent card chip pad arrangement structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208111430U true CN208111430U (en) | 2018-11-16 |
Family
ID=64130433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721331999.3U Active CN208111430U (en) | 2017-10-17 | 2017-10-17 | A kind of intelligent card chip pad arrangement structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208111430U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020248212A1 (en) * | 2019-06-14 | 2020-12-17 | 深圳市汇顶科技股份有限公司 | Chip encapsulation structure and electronic device |
-
2017
- 2017-10-17 CN CN201721331999.3U patent/CN208111430U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020248212A1 (en) * | 2019-06-14 | 2020-12-17 | 深圳市汇顶科技股份有限公司 | Chip encapsulation structure and electronic device |
| US11302621B2 (en) | 2019-06-14 | 2022-04-12 | Shenzhen GOODIX Technology Co., Ltd. | Chip package structure and electronic device |
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