CN1979202A - Method for parallelly detecting synchronous communication chips - Google Patents
Method for parallelly detecting synchronous communication chips Download PDFInfo
- Publication number
- CN1979202A CN1979202A CN 200510111292 CN200510111292A CN1979202A CN 1979202 A CN1979202 A CN 1979202A CN 200510111292 CN200510111292 CN 200510111292 CN 200510111292 A CN200510111292 A CN 200510111292A CN 1979202 A CN1979202 A CN 1979202A
- Authority
- CN
- China
- Prior art keywords
- chip
- data
- input
- shift register
- tester
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a method to take multi-chip parallel testing by using synchronous communication chip. It includes the following steps: connecting plural chips on silicon slice by shift register, outputting the testing signal to tested chips by the method of series to parallel, inputting the output data to I/O pins of tester from plural chips by the method of parallel to series, and reading the data and taking data process to gain the PASS/FAIL result of the chips. The invention could improve testing efficiency of testing chip and lower testing time and cost.
Description
Technical field
The present invention relates to a kind of method of testing of large scale integrated circuit, particularly relate to a kind of method of a plurality of large scale integrated circuit synchronous communication chips being carried out concurrent testing.
Background technology
Along with the development of large scale integrated circuit, circuit becomes increasingly complex, and the needed test duration is also just more and more longer, must improve the same quantitation that a plurality of chips is carried out concurrent testing in order to save the test duration.Simultaneously, because employed critical size is more and more littler on semiconductor is made, the core number on same silicon chip is also more and more.So both increase the test duration, increased the number of times of having an acupuncture treatment on the probe station again.Because acupuncture treatment too much can make probe pollute, and makes the probe oxidation easily, so pricking times too much can produce the bad problem of test.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method for parallelly detecting synchronous communication chips, and it can improve the same quantitation of parallelly detecting synchronous communication chips, and then improves concurrent testing efficient, reduces test duration and cost.
For solving the problems of the technologies described above, method for parallelly detecting synchronous communication chips of the present invention is to adopt following technical scheme to realize, at first, on silicon chip, use shift register that a plurality of chips are coupled together, change method also by string test signal is input on all chip under test; Then, be input on the I/O mouth of tester by the method for also changeing string by the output data of shift register a plurality of chips; The last test instrument obtains PASS/FAIL (pass/fail) result of each chip under test by the data of reading in being carried out data processing.
Adopt method of the present invention can obviously shorten the test duration of chip.For example adopt general tester to test simultaneously to 16 chips.And 16 chip simultaneous tests can further be extended to 64 chip simultaneous tests after adopting method of the present invention, testing efficiency has reached about 3～4 times of 16 chip simultaneous tests, it is about about 70% that this means that also the test duration of one piece of chip has shortened, and greatly reduces the testing cost of chip.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the connection diagram of a plurality of chips when adopting method of the present invention to carry out concurrent testing;
Fig. 2 adopts two test channel of method of the present invention (I/O mouth) to carry out the synoptic diagram of 8 chip simultaneous tests.
Embodiment
Boundary scan is a kind of more advanced means of testing, and it couples together each module in the chip by shift register and tests, and realizes controllability and the ornamental tested with this.The present invention promptly adopts the method for boundary scan that a plurality of synchronous communication chips are carried out concurrent testing, can effectively improve testing efficiency.
Method for parallelly detecting synchronous communication chips of the present invention is to regard a plurality of chips on the silicon chip as on the chip a plurality of modules, is connected on a plurality of chips with the parallel port on the shift register.Concrete solution is: as shown in Figure 1, on same silicon chip, on marking groove, make four two-way input and output shift registers, the PAD (pressure point) that the parallel delivery outlet of shift register is connected to each chip goes up on the signal end (for example I/O PAD), the probe of tester is pricked on the serial input port of four two-way input and output shift registers.PAD among Fig. 1 is the thin slice of an aluminium on each input/output port on the chip, and probe will be pricked in the above during test, is used to connect external pin during encapsulation.Like this, change method also by string test signal is input to all chip under test.
Utilize data setup time, export the data of concurrent testing successively on the I/O of tester mouth, (before rising edge clock) is with each data parallel output before data are effective.When the chip output data, earlier shift register is set to input state, and the output data (the last signal of PAD) of each chip is input in the I/O mouth of tester successively by shift register.Like this, by the method for also changeing string the output data of a plurality of chips is input to the I/O mouth of tester.On the ECR that on the tester I/O mouth input signal is write successively tester (ERROR CATCH ram error is handled internal memory), tester carries out the judgement of PASS/FAIL by the last data of ECR are handled realization to four corresponding on shift register chips, obtains test result.
As one embodiment of the present of invention, as seen in Figure 2, adopt method of the present invention to expand to the test resource of an original test channel.Make original two test channel can only carry out the same survey of two chips, can carry out the same survey of 8 chips, even under the situation of frequency and test duration permission, can also further increase the same survey number of chip through increasing shift register.
In test process, earlier the data in the shift register are moved to left at signal before effective time (be data effectively before) by tester, the data that needs are input on each chip (being DUT, measured device) move on on each chip.Then, be in input state, the data on the shift register are input on the chip, realize with of PATTERN (test vector) input test of a test channel a plurality of chip under test with this by the clock enabling signal chip.
When chip is in output state, make shift register be in parallel input state earlier, the output of a plurality of chip under test is input on the shift register.Then, before the next clock period arrives, the data on the shift register are moved to right, realize with of the collection of a test channel to a plurality of chip under test data.
At last, the data with the shift register input deposit among the ECR of tester laterally storage continuously in.Horizontal width is the same survey number on the same test channel.Vertically reading of data and effect reference value relatively just can be judged the current vertically PASS/FAIL result of this row chip under test successively as long as pass through when judging chip PASS/FAIL.
It is 4,8,16 or 32 that a test channel of tester can be pricked the chip of realizing concurrent testing on a shift register.
The probe of each test channel of tester can be pricked the shift register of chip chamber and expand, and realizes more chip is carried out with surveying.
The used probe of tester only need be made the probe of a chip, probe is pricked the test that realizes on the serial I/O port of shift register a plurality of chips.
After silicon chip was cut apart, the shift register in the scribe line all will be scratched with the line that is connected a plurality of chip chambers.The chip that originally links together on silicon chip will be separated.
Claims (10)
1, a kind of method for parallelly detecting synchronous communication chips is characterized in that: at first, use shift register that a plurality of chips are coupled together on silicon chip, change method also by string test signal is input on all chip under test; Then, be input on the I/O mouth of tester by the method for also changeing string by the output data of shift register a plurality of chips; The last test instrument is by carrying out the PASS/FAIL result that data processing obtains each chip under test to the data of reading in.
2, method for parallelly detecting synchronous communication chips as claimed in claim 1, it is characterized in that: described string commentaries on classics method also is input to test signal on all chip under test and is meant, on same silicon chip, be connected with shift register by the pad signal end of marking groove, the probe of tester pricked on the serial input port of shift register each chip.
3, method for parallelly detecting synchronous communication chips as claimed in claim 1 or 2, it is characterized in that: the process that test signal is input on all chip under test is, earlier the data in the shift register were moved to left before effective time at signal by tester, the data that needs are input on each chip move on on the data input pin of each chip; Then, be in input state by the clock enabling signal chip.
4, method for parallelly detecting synchronous communication chips as claimed in claim 1, it is characterized in that: the described and method of changeing string is meant the I/O mouth that the output data of a plurality of chips is input to tester, utilize data setup time, on the I/O of tester mouth, export the data of concurrent testing successively, before data are effective, each data parallel is exported; When chip signal output, first shift register is set to input state, and the last signal of the PAD of each chip is input in the I/O mouth of tester successively by shift register.
5, as claim 1 or 4 described method for parallelly detecting synchronous communication chips, it is characterized in that: after the output data of each chip is input to shift register, before arriving, the next clock period, realizes of the collection of an I/O mouth of tester to a plurality of chip under test data with the data shift right in the shift register.
6, as claim 1 or 4 described method for parallelly detecting synchronous communication chips, it is characterized in that: be input to the data on the I/O mouth of tester, deposit among the ECR of tester, and laterally storage continuously, horizontal width is the same survey number on same test I/O mouth.
7, method for parallelly detecting synchronous communication chips as claimed in claim 1 is characterized in that: the described PASS/FAIL result who obtains each chip under test by data processing is meant, vertically successively reading of data and with the effect reference value relatively.
8, method for parallelly detecting synchronous communication chips as claimed in claim 1 is characterized in that: described shift register adopts four two-way input and output shift registers.
9, method for parallelly detecting synchronous communication chips as claimed in claim 1 is characterized in that: it is 4,8,16 or 32 that a test I of described tester/O mouth passage can be pricked the chip of realizing concurrent testing on a shift register.
10, method for parallelly detecting synchronous communication chips as claimed in claim 1 is characterized in that: the probe of each test I/O mouth of tester can be pricked the shift register of chip chamber and expand, and realizes more chip is carried out with surveying.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101112927A CN100501434C (en) | 2005-12-08 | 2005-12-08 | Method for parallel detecting synchronous communication chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101112927A CN100501434C (en) | 2005-12-08 | 2005-12-08 | Method for parallel detecting synchronous communication chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1979202A true CN1979202A (en) | 2007-06-13 |
| CN100501434C CN100501434C (en) | 2009-06-17 |
Family
ID=38130436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101112927A Active CN100501434C (en) | 2005-12-08 | 2005-12-08 | Method for parallel detecting synchronous communication chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100501434C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010075815A1 (en) * | 2009-01-03 | 2010-07-08 | 上海芯豪微电子有限公司 | Method, apparatus and system for testing integrated circuits |
| CN102520340A (en) * | 2012-01-06 | 2012-06-27 | 日月光半导体制造股份有限公司 | Semiconductor packaging component with testing structure and testing method thereof |
| CN104215843A (en) * | 2013-06-05 | 2014-12-17 | 上海华虹宏力半导体制造有限公司 | Chip arranging method for improving concurrent test of chips |
| CN106872874A (en) * | 2015-12-11 | 2017-06-20 | 华大半导体有限公司 | One kind concentrates CP method of testings for RFID label chip |
| CN107918086A (en) * | 2017-11-09 | 2018-04-17 | 武汉理工大学 | One kind communication parallel intelligent detecting method of wire rod |
| CN108008275A (en) * | 2017-11-20 | 2018-05-08 | 上海华力微电子有限公司 | A kind of system level chip production method for possessing fault diagnosis |
| CN108919006A (en) * | 2018-07-12 | 2018-11-30 | 长江存储科技有限责任公司 | Interface Expanding mould group, aging testing system, ageing testing method and storage medium |
| CN111983270A (en) * | 2020-07-30 | 2020-11-24 | 华润赛美科微电子(深圳)有限公司 | Expansion circuit, tester and test method |
-
2005
- 2005-12-08 CN CNB2005101112927A patent/CN100501434C/en active Active
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010075815A1 (en) * | 2009-01-03 | 2010-07-08 | 上海芯豪微电子有限公司 | Method, apparatus and system for testing integrated circuits |
| CN102520340A (en) * | 2012-01-06 | 2012-06-27 | 日月光半导体制造股份有限公司 | Semiconductor packaging component with testing structure and testing method thereof |
| CN105977180A (en) * | 2012-01-06 | 2016-09-28 | 日月光半导体制造股份有限公司 | Semiconductor packaging component with test structure and test method of semiconductor packaging component |
| CN105977180B (en) * | 2012-01-06 | 2020-05-08 | 日月光半导体制造股份有限公司 | Semiconductor packaging element with test structure and test method thereof |
| CN104215843A (en) * | 2013-06-05 | 2014-12-17 | 上海华虹宏力半导体制造有限公司 | Chip arranging method for improving concurrent test of chips |
| CN106872874A (en) * | 2015-12-11 | 2017-06-20 | 华大半导体有限公司 | One kind concentrates CP method of testings for RFID label chip |
| CN107918086A (en) * | 2017-11-09 | 2018-04-17 | 武汉理工大学 | One kind communication parallel intelligent detecting method of wire rod |
| CN108008275A (en) * | 2017-11-20 | 2018-05-08 | 上海华力微电子有限公司 | A kind of system level chip production method for possessing fault diagnosis |
| CN108008275B (en) * | 2017-11-20 | 2020-05-01 | 上海华力微电子有限公司 | System-on-chip production method with fault diagnosis function |
| CN108919006A (en) * | 2018-07-12 | 2018-11-30 | 长江存储科技有限责任公司 | Interface Expanding mould group, aging testing system, ageing testing method and storage medium |
| CN111983270A (en) * | 2020-07-30 | 2020-11-24 | 华润赛美科微电子(深圳)有限公司 | Expansion circuit, tester and test method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100501434C (en) | 2009-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100442069C (en) | Method for parallelly detecting multiple chips of synchronous communication | |
| CN100501434C (en) | Method for parallel detecting synchronous communication chips | |
| US7870452B2 (en) | Scan testing methods | |
| US7906982B1 (en) | Interface apparatus and methods of testing integrated circuits using the same | |
| CN104237766B (en) | Chip detecting method and device | |
| CN102305907A (en) | Test method and system for multichip encapsulating structure | |
| CN100442070C (en) | Method for parallelly detecting synchronous communication chips | |
| CN101196553A (en) | Method for improving SOC chip testing efficiency | |
| US20140264331A1 (en) | Daisy chain connection for testing continuity in a semiconductor die | |
| CN103487744A (en) | Dynamic EMMI system, implementing method of dynamic EMMI system and application method of dynamic EMMI system | |
| CN103630824A (en) | Chip concurrent test system | |
| CN102338848A (en) | Method and system for wafer level testing of semiconductor chips | |
| CN102446557A (en) | Chip and chip parallel test method | |
| CN102998497A (en) | Production method of skip type probe card | |
| KR20080099495A (en) | Pipeline test apparatus and method | |
| CN101470170B (en) | JTAG link test method and apparatus | |
| US7805647B2 (en) | System and method for testing a plurality of circuits | |
| WO2017113883A1 (en) | Method and device for testing interconnections of multiple chips in system-in-package chip | |
| CN101957430B (en) | Boundary scan test method and device for reducing noise | |
| CN108983072A (en) | Crystal round test approach, wafer tester and wafer test system | |
| CN102565664A (en) | Evaluation method for testing coverage rate | |
| CN100575975C (en) | Asynchronous chip simultaneous test method | |
| CN1779479A (en) | Realization of multiple-chip parallel test for asynchronous communication chip | |
| CN207250460U (en) | A kind of fast positioning and the high-density test chip for measuring defect | |
| KR20090075515A (en) | Probe card and test apparatus comprising the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |